1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/
4 *
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 * (C) Copyright 2023 - 2024, Advanced Micro D
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11 /dts-v1/;
12
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h
19
20 / {
21 model = "ZynqMP SM-K26 Rev2/1/B/A";
22 compatible = "xlnx,zynqmp-sm-k26-rev2"
23 "xlnx,zynqmp-sm-k26-rev1"
24 "xlnx,zynqmp-sm-k26-revA"
25 "xlnx,zynqmp";
26
27 aliases {
28 i2c0 = &i2c0;
29 i2c1 = &i2c1;
30 mmc0 = &sdhci0;
31 mmc1 = &sdhci1;
32 nvmem0 = &eeprom;
33 nvmem1 = &eeprom_cc;
34 rtc0 = &rtc;
35 serial0 = &uart0;
36 serial1 = &uart1;
37 serial2 = &dcc;
38 spi0 = &qspi;
39 spi1 = &spi0;
40 spi2 = &spi1;
41 usb0 = &usb0;
42 usb1 = &usb1;
43 };
44
45 chosen {
46 bootargs = "earlycon";
47 stdout-path = "serial1:115200n
48 };
49
50 memory@0 {
51 device_type = "memory"; /* 4GB
52 reg = <0x0 0x0 0x0 0x80000000>
53 };
54
55 reserved-memory {
56 #address-cells = <2>;
57 #size-cells = <2>;
58 ranges;
59
60 pmu_region: pmu@7ff00000 {
61 reg = <0x0 0x7ff00000
62 no-map;
63 };
64 };
65
66 gpio-keys {
67 compatible = "gpio-keys";
68 autorepeat;
69 key-fwuen {
70 label = "fwuen";
71 gpios = <&gpio 12 GPIO
72 linux,code = <BTN_MISC
73 wakeup-source;
74 autorepeat;
75 };
76 };
77
78 leds {
79 compatible = "gpio-leds";
80 ds35-led {
81 label = "heartbeat";
82 gpios = <&gpio 7 GPIO_
83 linux,default-trigger
84 };
85
86 ds36-led {
87 label = "vbus_det";
88 gpios = <&gpio 8 GPIO_
89 default-state = "on";
90 };
91 };
92
93 ams {
94 compatible = "iio-hwmon";
95 io-channels = <&xilinx_ams 0>,
96 <&xilinx_ams 3>, <&xil
97 <&xilinx_ams 6>, <&xil
98 <&xilinx_ams 9>, <&xil
99 <&xilinx_ams 12>, <&xi
100 <&xilinx_ams 15>, <&xi
101 <&xilinx_ams 18>, <&xi
102 <&xilinx_ams 21>, <&xi
103 <&xilinx_ams 24>, <&xi
104 <&xilinx_ams 27>, <&xi
105 };
106
107 pwm-fan {
108 compatible = "pwm-fan";
109 status = "okay";
110 pwms = <&ttc0 2 40000 0>;
111 };
112 };
113
114 &modepin_gpio {
115 label = "modepin";
116 };
117
118 &ttc0 {
119 status = "okay";
120 #pwm-cells = <3>;
121 };
122
123 &uart1 { /* MIO36/MIO37 */
124 status = "okay";
125 };
126
127 &pinctrl0 {
128 status = "okay";
129 pinctrl_sdhci0_default: sdhci0-default
130 conf {
131 groups = "sdio0_0_grp"
132 slew-rate = <SLEW_RATE
133 power-source = <IO_STA
134 bias-disable;
135 };
136
137 mux {
138 groups = "sdio0_0_grp"
139 function = "sdio0";
140 };
141 };
142 };
143
144 &qspi { /* MIO 0-5 - U143 */
145 status = "okay";
146 spi_flash: flash@0 { /* MT25QU512A */
147 compatible = "jedec,spi-nor";
148 reg = <0>;
149 spi-tx-bus-width = <4>;
150 spi-rx-bus-width = <4>;
151 spi-max-frequency = <40000000>
152
153 partitions {
154 compatible = "fixed-pa
155 #address-cells = <1>;
156 #size-cells = <1>;
157
158 partition@0 {
159 label = "Image
160 reg = <0x0 0x8
161 read-only;
162 lock;
163 };
164 partition@80000 {
165 label = "Image
166 reg = <0x80000
167 read-only;
168 lock;
169 };
170 partition@100000 {
171 label = "Persi
172 reg = <0x10000
173 };
174 partition@120000 {
175 label = "Persi
176 reg = <0x12000
177 };
178 partition@140000 {
179 label = "Open_
180 reg = <0x14000
181 };
182 partition@200000 {
183 label = "Image
184 reg = <0x20000
185 };
186 partition@f00000 {
187 label = "ImgSe
188 reg = <0xF0000
189 read-only;
190 lock;
191 };
192 partition@f80000 {
193 label = "Image
194 reg = <0xF8000
195 };
196 partition@1c80000 {
197 label = "ImgSe
198 reg = <0x1C800
199 read-only;
200 lock;
201 };
202 partition@1d00000 {
203 label = "Open_
204 reg = <0x1D000
205 };
206 partition@1e00000 {
207 label = "Recov
208 reg = <0x1E000
209 read-only;
210 lock;
211 };
212 partition@2000000 {
213 label = "Recov
214 reg = <0x20000
215 read-only;
216 lock;
217 };
218 partition@2200000 {
219 label = "U-Boo
220 reg = <0x22000
221 };
222 partition@2220000 {
223 label = "U-Boo
224 reg = <0x22200
225 };
226 partition@2240000 {
227 label = "SHA25
228 reg = <0x22400
229 read-only;
230 lock;
231 };
232 partition@2280000 {
233 label = "Secur
234 reg = <0x22800
235 };
236 partition@22a0000 {
237 label = "User"
238 reg = <0x22a00
239 };
240 };
241 };
242 };
243
244 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALB
245 status = "okay";
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_sdhci0_default>;
248 non-removable;
249 disable-wp;
250 bus-width = <8>;
251 xlnx,mio-bank = <0>;
252 assigned-clock-rates = <187498123>;
253 };
254
255 &spi1 { /* MIO6, 9-11 */
256 status = "okay";
257 label = "TPM";
258 num-cs = <1>;
259 tpm@0 { /* slm9670 - U144 */
260 compatible = "infineon,slb9670
261 reg = <0>;
262 spi-max-frequency = <18500000>
263 };
264 };
265
266 &i2c1 {
267 status = "okay";
268 bootph-all;
269 clock-frequency = <400000>;
270 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIG
271 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIG
272
273 eeprom: eeprom@50 { /* u46 - also at a
274 bootph-all;
275 compatible = "st,24c64", "atme
276 reg = <0x50>;
277 /* WP pin EE_WP_EN connected t
278 };
279
280 eeprom_cc: eeprom@51 { /* required by
281 bootph-all;
282 compatible = "st,24c64", "atme
283 reg = <0x51>;
284 };
285
286 /* da9062@30 - u170 - also at address
287 /* da9131@33 - u167 */
288 da9131: pmic@33 {
289 compatible = "dlg,da9131";
290 reg = <0x33>;
291 regulators {
292 da9131_buck1: buck1 {
293 regulator-name
294 regulator-boot
295 regulator-alwa
296 };
297 da9131_buck2: buck2 {
298 regulator-name
299 regulator-boot
300 regulator-alwa
301 };
302 };
303 };
304
305 /* da9130@32 - u166 */
306 da9130: pmic@32 {
307 compatible = "dlg,da9130";
308 reg = <0x32>;
309 regulators {
310 da9130_buck1: buck1 {
311 regulator-name
312 regulator-boot
313 regulator-alwa
314 };
315 };
316 };
317
318 /* slg7x644091@70 - u168 NOT accessibl
319 /*
320 * stdp4320 - u27 FW has below two iss
321 * Device acknowledging to addresses 0
322 * Address conflict with slg7x644091@7
323 * With the FW fix, stdp4320 should re
324 */
325 /* slg7x644092@68 - u169 */
326 /* Also connected via JA1C as C23/C24
327 };
328
329 &gpio {
330 status = "okay";
331 gpio-line-names = "QSPI_CLK", "QSPI_DQ
332 "QSPI_CS_B", "SPI_CL
333 "SPI_MISO", "SPI_MOS
334 "EMMC_DAT2", "EMMC_D
335 "EMMC_DAT7", "EMMC_C
336 "I2C1_SDA", "", "",
337 "", "", "", "", "",
338 "", "", "", "", "",
339 "", "", "", "", "",
340 "", "", "", "", "",
341 "", "", "", "", "",
342 "", "", "", "", "",
343 "", "", "", "", "",
344 "", "", "", "", "",
345 "", "", "", "", "",
346 "", "", "", /* 75 -
347 "", "", /* 78 - 79 *
348 "", "", "", "", "",
349 "", "", "", "", "",
350 "", "", "", "", "",
351 "", "", "", "", "",
352 "", "", "", "", "",
353 "", "", "", "", "",
354 "", "", "", "", "",
355 "", "", "", "", "",
356 "", "", "", "", "",
357 "", "", "", "", "",
358 "", "", "", "", "",
359 "", "", "", "", "",
360 "", "", "", "", "",
361 "", "", "", "", "",
362 "", "", "", "", "",
363 "", "", "", "", "",
364 "", "", "", "", "",
365 "", "", "", "", "",
366 "", "", "", ""; /* 1
367 };
368
369 &xilinx_ams {
370 status = "okay";
371 };
372
373 &ams_ps {
374 status = "okay";
375 };
376
377 &ams_pl {
378 status = "okay";
379 };
380
381 &zynqmp_dpsub {
382 status = "okay";
383 };
384
385 &rtc {
386 status = "okay";
387 };
388
389 &lpd_dma_chan1 {
390 status = "okay";
391 };
392
393 &lpd_dma_chan2 {
394 status = "okay";
395 };
396
397 &lpd_dma_chan3 {
398 status = "okay";
399 };
400
401 &lpd_dma_chan4 {
402 status = "okay";
403 };
404
405 &lpd_dma_chan5 {
406 status = "okay";
407 };
408
409 &lpd_dma_chan6 {
410 status = "okay";
411 };
412
413 &lpd_dma_chan7 {
414 status = "okay";
415 };
416
417 &lpd_dma_chan8 {
418 status = "okay";
419 };
420
421 &fpd_dma_chan1 {
422 status = "okay";
423 };
424
425 &fpd_dma_chan2 {
426 status = "okay";
427 };
428
429 &fpd_dma_chan3 {
430 status = "okay";
431 };
432
433 &fpd_dma_chan4 {
434 status = "okay";
435 };
436
437 &fpd_dma_chan5 {
438 status = "okay";
439 };
440
441 &fpd_dma_chan6 {
442 status = "okay";
443 };
444
445 &fpd_dma_chan7 {
446 status = "okay";
447 };
448
449 &fpd_dma_chan8 {
450 status = "okay";
451 };
452
453 &gpu {
454 status = "okay";
455 };
456
457 &lpd_watchdog {
458 status = "okay";
459 };
460
461 &watchdog0 {
462 status = "okay";
463 };
464
465 &cpu_opp_table {
466 opp00 {
467 opp-hz = /bits/ 64 <1333333333
468 };
469 opp01 {
470 opp-hz = /bits/ 64 <666666666>
471 };
472 opp02 {
473 opp-hz = /bits/ 64 <444444444>
474 };
475 opp03 {
476 opp-hz = /bits/ 64 <333333333>
477 };
478 };
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