1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/ !! 3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
4 * 4 *
5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 * (C) Copyright 2023 - 2024, Advanced Micro D <<
7 * 6 *
8 * Michal Simek <michal.simek@amd.com> !! 7 * Michal Simek <michal.simek@xilinx.com>
9 */ 8 */
10 9
11 /dts-v1/; 10 /dts-v1/;
12 11
13 #include "zynqmp.dtsi" 12 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi" 13 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h> 14 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/phy/phy.h> 16 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h <<
19 17
20 / { 18 / {
21 model = "ZynqMP SM-K26 Rev2/1/B/A"; !! 19 model = "ZynqMP SM-K26 Rev1/B/A";
22 compatible = "xlnx,zynqmp-sm-k26-rev2" !! 20 compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
23 "xlnx,zynqmp-sm-k26-rev1" <<
24 "xlnx,zynqmp-sm-k26-revA" 21 "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
25 "xlnx,zynqmp"; 22 "xlnx,zynqmp";
26 23
27 aliases { 24 aliases {
28 i2c0 = &i2c0; 25 i2c0 = &i2c0;
29 i2c1 = &i2c1; 26 i2c1 = &i2c1;
30 mmc0 = &sdhci0; 27 mmc0 = &sdhci0;
31 mmc1 = &sdhci1; 28 mmc1 = &sdhci1;
32 nvmem0 = &eeprom; 29 nvmem0 = &eeprom;
33 nvmem1 = &eeprom_cc; 30 nvmem1 = &eeprom_cc;
34 rtc0 = &rtc; 31 rtc0 = &rtc;
35 serial0 = &uart0; 32 serial0 = &uart0;
36 serial1 = &uart1; 33 serial1 = &uart1;
37 serial2 = &dcc; 34 serial2 = &dcc;
38 spi0 = &qspi; 35 spi0 = &qspi;
39 spi1 = &spi0; 36 spi1 = &spi0;
40 spi2 = &spi1; 37 spi2 = &spi1;
41 usb0 = &usb0; 38 usb0 = &usb0;
42 usb1 = &usb1; 39 usb1 = &usb1;
43 }; 40 };
44 41
45 chosen { 42 chosen {
46 bootargs = "earlycon"; 43 bootargs = "earlycon";
47 stdout-path = "serial1:115200n 44 stdout-path = "serial1:115200n8";
48 }; 45 };
49 46
50 memory@0 { 47 memory@0 {
51 device_type = "memory"; /* 4GB 48 device_type = "memory"; /* 4GB */
52 reg = <0x0 0x0 0x0 0x80000000> 49 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
53 }; 50 };
54 51
55 reserved-memory { <<
56 #address-cells = <2>; <<
57 #size-cells = <2>; <<
58 ranges; <<
59 <<
60 pmu_region: pmu@7ff00000 { <<
61 reg = <0x0 0x7ff00000 <<
62 no-map; <<
63 }; <<
64 }; <<
65 <<
66 gpio-keys { 52 gpio-keys {
67 compatible = "gpio-keys"; 53 compatible = "gpio-keys";
68 autorepeat; 54 autorepeat;
69 key-fwuen { !! 55 fwuen {
70 label = "fwuen"; 56 label = "fwuen";
71 gpios = <&gpio 12 GPIO 57 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
72 linux,code = <BTN_MISC <<
73 wakeup-source; <<
74 autorepeat; <<
75 }; 58 };
76 }; 59 };
77 60
78 leds { 61 leds {
79 compatible = "gpio-leds"; 62 compatible = "gpio-leds";
80 ds35-led { 63 ds35-led {
81 label = "heartbeat"; 64 label = "heartbeat";
82 gpios = <&gpio 7 GPIO_ 65 gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
83 linux,default-trigger 66 linux,default-trigger = "heartbeat";
84 }; 67 };
85 68
86 ds36-led { 69 ds36-led {
87 label = "vbus_det"; 70 label = "vbus_det";
88 gpios = <&gpio 8 GPIO_ 71 gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
89 default-state = "on"; 72 default-state = "on";
90 }; 73 };
91 }; 74 };
92 <<
93 ams { <<
94 compatible = "iio-hwmon"; <<
95 io-channels = <&xilinx_ams 0>, <<
96 <&xilinx_ams 3>, <&xil <<
97 <&xilinx_ams 6>, <&xil <<
98 <&xilinx_ams 9>, <&xil <<
99 <&xilinx_ams 12>, <&xi <<
100 <&xilinx_ams 15>, <&xi <<
101 <&xilinx_ams 18>, <&xi <<
102 <&xilinx_ams 21>, <&xi <<
103 <&xilinx_ams 24>, <&xi <<
104 <&xilinx_ams 27>, <&xi <<
105 }; <<
106 <<
107 pwm-fan { <<
108 compatible = "pwm-fan"; <<
109 status = "okay"; <<
110 pwms = <&ttc0 2 40000 0>; <<
111 }; <<
112 }; <<
113 <<
114 &modepin_gpio { <<
115 label = "modepin"; <<
116 }; <<
117 <<
118 &ttc0 { <<
119 status = "okay"; <<
120 #pwm-cells = <3>; <<
121 }; 75 };
122 76
123 &uart1 { /* MIO36/MIO37 */ 77 &uart1 { /* MIO36/MIO37 */
124 status = "okay"; 78 status = "okay";
125 }; 79 };
126 80
127 &pinctrl0 { <<
128 status = "okay"; <<
129 pinctrl_sdhci0_default: sdhci0-default <<
130 conf { <<
131 groups = "sdio0_0_grp" <<
132 slew-rate = <SLEW_RATE <<
133 power-source = <IO_STA <<
134 bias-disable; <<
135 }; <<
136 <<
137 mux { <<
138 groups = "sdio0_0_grp" <<
139 function = "sdio0"; <<
140 }; <<
141 }; <<
142 }; <<
143 <<
144 &qspi { /* MIO 0-5 - U143 */ 81 &qspi { /* MIO 0-5 - U143 */
145 status = "okay"; 82 status = "okay";
146 spi_flash: flash@0 { /* MT25QU512A */ !! 83 flash@0 { /* MT25QU512A */
147 compatible = "jedec,spi-nor"; !! 84 compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
>> 85 #address-cells = <1>;
>> 86 #size-cells = <1>;
148 reg = <0>; 87 reg = <0>;
149 spi-tx-bus-width = <4>; !! 88 spi-tx-bus-width = <1>;
150 spi-rx-bus-width = <4>; 89 spi-rx-bus-width = <4>;
151 spi-max-frequency = <40000000> 90 spi-max-frequency = <40000000>; /* 40MHz */
152 !! 91 partition@0 {
153 partitions { !! 92 label = "Image Selector";
154 compatible = "fixed-pa !! 93 reg = <0x0 0x80000>; /* 512KB */
155 #address-cells = <1>; !! 94 read-only;
156 #size-cells = <1>; !! 95 lock;
157 !! 96 };
158 partition@0 { !! 97 partition@80000 {
159 label = "Image !! 98 label = "Image Selector Golden";
160 reg = <0x0 0x8 !! 99 reg = <0x80000 0x80000>; /* 512KB */
161 read-only; !! 100 read-only;
162 lock; !! 101 lock;
163 }; !! 102 };
164 partition@80000 { !! 103 partition@100000 {
165 label = "Image !! 104 label = "Persistent Register";
166 reg = <0x80000 !! 105 reg = <0x100000 0x20000>; /* 128KB */
167 read-only; !! 106 };
168 lock; !! 107 partition@120000 {
169 }; !! 108 label = "Persistent Register Backup";
170 partition@100000 { !! 109 reg = <0x120000 0x20000>; /* 128KB */
171 label = "Persi !! 110 };
172 reg = <0x10000 !! 111 partition@140000 {
173 }; !! 112 label = "Open_1";
174 partition@120000 { !! 113 reg = <0x140000 0xC0000>; /* 768KB */
175 label = "Persi !! 114 };
176 reg = <0x12000 !! 115 partition@200000 {
177 }; !! 116 label = "Image A (FSBL, PMU, ATF, U-Boot)";
178 partition@140000 { !! 117 reg = <0x200000 0xD00000>; /* 13MB */
179 label = "Open_ !! 118 };
180 reg = <0x14000 !! 119 partition@f00000 {
181 }; !! 120 label = "ImgSel Image A Catch";
182 partition@200000 { !! 121 reg = <0xF00000 0x80000>; /* 512KB */
183 label = "Image !! 122 read-only;
184 reg = <0x20000 !! 123 lock;
185 }; !! 124 };
186 partition@f00000 { !! 125 partition@f80000 {
187 label = "ImgSe !! 126 label = "Image B (FSBL, PMU, ATF, U-Boot)";
188 reg = <0xF0000 !! 127 reg = <0xF80000 0xD00000>; /* 13MB */
189 read-only; !! 128 };
190 lock; !! 129 partition@1c80000 {
191 }; !! 130 label = "ImgSel Image B Catch";
192 partition@f80000 { !! 131 reg = <0x1C80000 0x80000>; /* 512KB */
193 label = "Image !! 132 read-only;
194 reg = <0xF8000 !! 133 lock;
195 }; !! 134 };
196 partition@1c80000 { !! 135 partition@1d00000 {
197 label = "ImgSe !! 136 label = "Open_2";
198 reg = <0x1C800 !! 137 reg = <0x1D00000 0x100000>; /* 1MB */
199 read-only; !! 138 };
200 lock; !! 139 partition@1e00000 {
201 }; !! 140 label = "Recovery Image";
202 partition@1d00000 { !! 141 reg = <0x1E00000 0x200000>; /* 2MB */
203 label = "Open_ !! 142 read-only;
204 reg = <0x1D000 !! 143 lock;
205 }; !! 144 };
206 partition@1e00000 { !! 145 partition@2000000 {
207 label = "Recov !! 146 label = "Recovery Image Backup";
208 reg = <0x1E000 !! 147 reg = <0x2000000 0x200000>; /* 2MB */
209 read-only; !! 148 read-only;
210 lock; !! 149 lock;
211 }; !! 150 };
212 partition@2000000 { !! 151 partition@2200000 {
213 label = "Recov !! 152 label = "U-Boot storage variables";
214 reg = <0x20000 !! 153 reg = <0x2200000 0x20000>; /* 128KB */
215 read-only; !! 154 };
216 lock; !! 155 partition@2220000 {
217 }; !! 156 label = "U-Boot storage variables backup";
218 partition@2200000 { !! 157 reg = <0x2220000 0x20000>; /* 128KB */
219 label = "U-Boo !! 158 };
220 reg = <0x22000 !! 159 partition@2240000 {
221 }; !! 160 label = "SHA256";
222 partition@2220000 { !! 161 reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
223 label = "U-Boo !! 162 read-only;
224 reg = <0x22200 !! 163 lock;
225 }; !! 164 };
226 partition@2240000 { !! 165 partition@2250000 {
227 label = "SHA25 !! 166 label = "User";
228 reg = <0x22400 !! 167 reg = <0x2250000 0x1db0000>; /* 29.5 MB */
229 read-only; <<
230 lock; <<
231 }; <<
232 partition@2280000 { <<
233 label = "Secur <<
234 reg = <0x22800 <<
235 }; <<
236 partition@22a0000 { <<
237 label = "User" <<
238 reg = <0x22a00 <<
239 }; <<
240 }; 168 };
241 }; 169 };
242 }; 170 };
243 171
244 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALB 172 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
245 status = "okay"; 173 status = "okay";
246 pinctrl-names = "default"; <<
247 pinctrl-0 = <&pinctrl_sdhci0_default>; <<
248 non-removable; 174 non-removable;
249 disable-wp; 175 disable-wp;
250 bus-width = <8>; 176 bus-width = <8>;
251 xlnx,mio-bank = <0>; 177 xlnx,mio-bank = <0>;
252 assigned-clock-rates = <187498123>; <<
253 }; 178 };
254 179
255 &spi1 { /* MIO6, 9-11 */ 180 &spi1 { /* MIO6, 9-11 */
256 status = "okay"; 181 status = "okay";
257 label = "TPM"; 182 label = "TPM";
258 num-cs = <1>; 183 num-cs = <1>;
259 tpm@0 { /* slm9670 - U144 */ 184 tpm@0 { /* slm9670 - U144 */
260 compatible = "infineon,slb9670 185 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
261 reg = <0>; 186 reg = <0>;
262 spi-max-frequency = <18500000> 187 spi-max-frequency = <18500000>;
263 }; 188 };
264 }; 189 };
265 190
266 &i2c1 { 191 &i2c1 {
267 status = "okay"; 192 status = "okay";
268 bootph-all; <<
269 clock-frequency = <400000>; 193 clock-frequency = <400000>;
270 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIG !! 194 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
271 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIG !! 195 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
272 196
273 eeprom: eeprom@50 { /* u46 - also at a 197 eeprom: eeprom@50 { /* u46 - also at address 0x58 */
274 bootph-all; <<
275 compatible = "st,24c64", "atme 198 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
276 reg = <0x50>; 199 reg = <0x50>;
277 /* WP pin EE_WP_EN connected t 200 /* WP pin EE_WP_EN connected to slg7x644092@68 */
278 }; 201 };
279 202
280 eeprom_cc: eeprom@51 { /* required by 203 eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
281 bootph-all; <<
282 compatible = "st,24c64", "atme 204 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
283 reg = <0x51>; 205 reg = <0x51>;
284 }; 206 };
285 207
286 /* da9062@30 - u170 - also at address 208 /* da9062@30 - u170 - also at address 0x31 */
287 /* da9131@33 - u167 */ 209 /* da9131@33 - u167 */
288 da9131: pmic@33 { 210 da9131: pmic@33 {
289 compatible = "dlg,da9131"; 211 compatible = "dlg,da9131";
290 reg = <0x33>; 212 reg = <0x33>;
291 regulators { 213 regulators {
292 da9131_buck1: buck1 { 214 da9131_buck1: buck1 {
293 regulator-name 215 regulator-name = "da9131_buck1";
294 regulator-boot 216 regulator-boot-on;
295 regulator-alwa 217 regulator-always-on;
296 }; 218 };
297 da9131_buck2: buck2 { 219 da9131_buck2: buck2 {
298 regulator-name 220 regulator-name = "da9131_buck2";
299 regulator-boot 221 regulator-boot-on;
300 regulator-alwa 222 regulator-always-on;
301 }; 223 };
302 }; 224 };
303 }; 225 };
304 226
305 /* da9130@32 - u166 */ 227 /* da9130@32 - u166 */
306 da9130: pmic@32 { 228 da9130: pmic@32 {
307 compatible = "dlg,da9130"; 229 compatible = "dlg,da9130";
308 reg = <0x32>; 230 reg = <0x32>;
309 regulators { 231 regulators {
310 da9130_buck1: buck1 { 232 da9130_buck1: buck1 {
311 regulator-name 233 regulator-name = "da9130_buck1";
312 regulator-boot 234 regulator-boot-on;
313 regulator-alwa 235 regulator-always-on;
314 }; 236 };
315 }; 237 };
316 }; 238 };
317 239
318 /* slg7x644091@70 - u168 NOT accessibl 240 /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
319 /* 241 /*
320 * stdp4320 - u27 FW has below two iss 242 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
321 * Device acknowledging to addresses 0 243 * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
322 * Address conflict with slg7x644091@7 244 * Address conflict with slg7x644091@70 making both the devices NOT accessible.
323 * With the FW fix, stdp4320 should re 245 * With the FW fix, stdp4320 should respond to address 0x73 only.
324 */ 246 */
325 /* slg7x644092@68 - u169 */ 247 /* slg7x644092@68 - u169 */
326 /* Also connected via JA1C as C23/C24 248 /* Also connected via JA1C as C23/C24 */
327 }; 249 };
328 250
329 &gpio { 251 &gpio {
330 status = "okay"; 252 status = "okay";
331 gpio-line-names = "QSPI_CLK", "QSPI_DQ 253 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
332 "QSPI_CS_B", "SPI_CL 254 "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
333 "SPI_MISO", "SPI_MOS 255 "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
334 "EMMC_DAT2", "EMMC_D 256 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
335 "EMMC_DAT7", "EMMC_C 257 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
336 "I2C1_SDA", "", "", 258 "I2C1_SDA", "", "", "", "", /* 25 - 29 */
337 "", "", "", "", "", 259 "", "", "", "", "", /* 30 - 34 */
338 "", "", "", "", "", 260 "", "", "", "", "", /* 35 - 39 */
339 "", "", "", "", "", 261 "", "", "", "", "", /* 40 - 44 */
340 "", "", "", "", "", 262 "", "", "", "", "", /* 45 - 49 */
341 "", "", "", "", "", 263 "", "", "", "", "", /* 50 - 54 */
342 "", "", "", "", "", 264 "", "", "", "", "", /* 55 - 59 */
343 "", "", "", "", "", 265 "", "", "", "", "", /* 60 - 64 */
344 "", "", "", "", "", 266 "", "", "", "", "", /* 65 - 69 */
345 "", "", "", "", "", 267 "", "", "", "", "", /* 70 - 74 */
346 "", "", "", /* 75 - 268 "", "", "", /* 75 - 77, MIO end and EMIO start */
347 "", "", /* 78 - 79 * 269 "", "", /* 78 - 79 */
348 "", "", "", "", "", 270 "", "", "", "", "", /* 80 - 84 */
349 "", "", "", "", "", 271 "", "", "", "", "", /* 85 - 89 */
350 "", "", "", "", "", 272 "", "", "", "", "", /* 90 - 94 */
351 "", "", "", "", "", 273 "", "", "", "", "", /* 95 - 99 */
352 "", "", "", "", "", 274 "", "", "", "", "", /* 100 - 104 */
353 "", "", "", "", "", 275 "", "", "", "", "", /* 105 - 109 */
354 "", "", "", "", "", 276 "", "", "", "", "", /* 110 - 114 */
355 "", "", "", "", "", 277 "", "", "", "", "", /* 115 - 119 */
356 "", "", "", "", "", 278 "", "", "", "", "", /* 120 - 124 */
357 "", "", "", "", "", 279 "", "", "", "", "", /* 125 - 129 */
358 "", "", "", "", "", 280 "", "", "", "", "", /* 130 - 134 */
359 "", "", "", "", "", 281 "", "", "", "", "", /* 135 - 139 */
360 "", "", "", "", "", 282 "", "", "", "", "", /* 140 - 144 */
361 "", "", "", "", "", 283 "", "", "", "", "", /* 145 - 149 */
362 "", "", "", "", "", 284 "", "", "", "", "", /* 150 - 154 */
363 "", "", "", "", "", 285 "", "", "", "", "", /* 155 - 159 */
364 "", "", "", "", "", 286 "", "", "", "", "", /* 160 - 164 */
365 "", "", "", "", "", 287 "", "", "", "", "", /* 165 - 169 */
366 "", "", "", ""; /* 1 !! 288 "", "", "", ""; /* 170 - 174 */
367 }; <<
368 <<
369 &xilinx_ams { <<
370 status = "okay"; <<
371 }; <<
372 <<
373 &ams_ps { <<
374 status = "okay"; <<
375 }; <<
376 <<
377 &ams_pl { <<
378 status = "okay"; <<
379 }; <<
380 <<
381 &zynqmp_dpsub { <<
382 status = "okay"; <<
383 }; <<
384 <<
385 &rtc { <<
386 status = "okay"; <<
387 }; <<
388 <<
389 &lpd_dma_chan1 { <<
390 status = "okay"; <<
391 }; <<
392 <<
393 &lpd_dma_chan2 { <<
394 status = "okay"; <<
395 }; <<
396 <<
397 &lpd_dma_chan3 { <<
398 status = "okay"; <<
399 }; <<
400 <<
401 &lpd_dma_chan4 { <<
402 status = "okay"; <<
403 }; <<
404 <<
405 &lpd_dma_chan5 { <<
406 status = "okay"; <<
407 }; <<
408 <<
409 &lpd_dma_chan6 { <<
410 status = "okay"; <<
411 }; <<
412 <<
413 &lpd_dma_chan7 { <<
414 status = "okay"; <<
415 }; <<
416 <<
417 &lpd_dma_chan8 { <<
418 status = "okay"; <<
419 }; <<
420 <<
421 &fpd_dma_chan1 { <<
422 status = "okay"; <<
423 }; <<
424 <<
425 &fpd_dma_chan2 { <<
426 status = "okay"; <<
427 }; <<
428 <<
429 &fpd_dma_chan3 { <<
430 status = "okay"; <<
431 }; <<
432 <<
433 &fpd_dma_chan4 { <<
434 status = "okay"; <<
435 }; <<
436 <<
437 &fpd_dma_chan5 { <<
438 status = "okay"; <<
439 }; <<
440 <<
441 &fpd_dma_chan6 { <<
442 status = "okay"; <<
443 }; <<
444 <<
445 &fpd_dma_chan7 { <<
446 status = "okay"; <<
447 }; <<
448 <<
449 &fpd_dma_chan8 { <<
450 status = "okay"; <<
451 }; <<
452 <<
453 &gpu { <<
454 status = "okay"; <<
455 }; <<
456 <<
457 &lpd_watchdog { <<
458 status = "okay"; <<
459 }; <<
460 <<
461 &watchdog0 { <<
462 status = "okay"; <<
463 }; <<
464 <<
465 &cpu_opp_table { <<
466 opp00 { <<
467 opp-hz = /bits/ 64 <1333333333 <<
468 }; <<
469 opp01 { <<
470 opp-hz = /bits/ 64 <666666666> <<
471 }; <<
472 opp02 { <<
473 opp-hz = /bits/ 64 <444444444> <<
474 }; <<
475 opp03 { <<
476 opp-hz = /bits/ 64 <333333333> <<
477 }; <<
478 }; 289 };
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