1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/ !! 3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
4 * 4 *
5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 * (C) Copyright 2023 - 2024, Advanced Micro D <<
7 * 6 *
8 * Michal Simek <michal.simek@amd.com> 7 * Michal Simek <michal.simek@amd.com>
9 */ 8 */
10 9
11 /dts-v1/; 10 /dts-v1/;
12 11
13 #include "zynqmp.dtsi" 12 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi" 13 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h> 14 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/phy/phy.h> 16 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h 17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 18
20 / { 19 / {
21 model = "ZynqMP SM-K26 Rev2/1/B/A"; !! 20 model = "ZynqMP SM-K26 Rev1/B/A";
22 compatible = "xlnx,zynqmp-sm-k26-rev2" !! 21 compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
23 "xlnx,zynqmp-sm-k26-rev1" <<
24 "xlnx,zynqmp-sm-k26-revA" 22 "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
25 "xlnx,zynqmp"; 23 "xlnx,zynqmp";
26 24
27 aliases { 25 aliases {
28 i2c0 = &i2c0; 26 i2c0 = &i2c0;
29 i2c1 = &i2c1; 27 i2c1 = &i2c1;
30 mmc0 = &sdhci0; 28 mmc0 = &sdhci0;
31 mmc1 = &sdhci1; 29 mmc1 = &sdhci1;
32 nvmem0 = &eeprom; 30 nvmem0 = &eeprom;
33 nvmem1 = &eeprom_cc; 31 nvmem1 = &eeprom_cc;
34 rtc0 = &rtc; 32 rtc0 = &rtc;
35 serial0 = &uart0; 33 serial0 = &uart0;
36 serial1 = &uart1; 34 serial1 = &uart1;
37 serial2 = &dcc; 35 serial2 = &dcc;
38 spi0 = &qspi; 36 spi0 = &qspi;
39 spi1 = &spi0; 37 spi1 = &spi0;
40 spi2 = &spi1; 38 spi2 = &spi1;
41 usb0 = &usb0; 39 usb0 = &usb0;
42 usb1 = &usb1; 40 usb1 = &usb1;
43 }; 41 };
44 42
45 chosen { 43 chosen {
46 bootargs = "earlycon"; 44 bootargs = "earlycon";
47 stdout-path = "serial1:115200n 45 stdout-path = "serial1:115200n8";
48 }; 46 };
49 47
50 memory@0 { 48 memory@0 {
51 device_type = "memory"; /* 4GB 49 device_type = "memory"; /* 4GB */
52 reg = <0x0 0x0 0x0 0x80000000> 50 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
53 }; 51 };
54 52
55 reserved-memory { <<
56 #address-cells = <2>; <<
57 #size-cells = <2>; <<
58 ranges; <<
59 <<
60 pmu_region: pmu@7ff00000 { <<
61 reg = <0x0 0x7ff00000 <<
62 no-map; <<
63 }; <<
64 }; <<
65 <<
66 gpio-keys { 53 gpio-keys {
67 compatible = "gpio-keys"; 54 compatible = "gpio-keys";
68 autorepeat; 55 autorepeat;
69 key-fwuen { 56 key-fwuen {
70 label = "fwuen"; 57 label = "fwuen";
71 gpios = <&gpio 12 GPIO 58 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
72 linux,code = <BTN_MISC 59 linux,code = <BTN_MISC>;
73 wakeup-source; 60 wakeup-source;
74 autorepeat; 61 autorepeat;
75 }; 62 };
76 }; 63 };
77 64
78 leds { 65 leds {
79 compatible = "gpio-leds"; 66 compatible = "gpio-leds";
80 ds35-led { 67 ds35-led {
81 label = "heartbeat"; 68 label = "heartbeat";
82 gpios = <&gpio 7 GPIO_ 69 gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
83 linux,default-trigger 70 linux,default-trigger = "heartbeat";
84 }; 71 };
85 72
86 ds36-led { 73 ds36-led {
87 label = "vbus_det"; 74 label = "vbus_det";
88 gpios = <&gpio 8 GPIO_ 75 gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
89 default-state = "on"; 76 default-state = "on";
90 }; 77 };
91 }; 78 };
92 79
93 ams { 80 ams {
94 compatible = "iio-hwmon"; 81 compatible = "iio-hwmon";
95 io-channels = <&xilinx_ams 0>, 82 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
96 <&xilinx_ams 3>, <&xil 83 <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
97 <&xilinx_ams 6>, <&xil 84 <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
98 <&xilinx_ams 9>, <&xil 85 <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
99 <&xilinx_ams 12>, <&xi 86 <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
100 <&xilinx_ams 15>, <&xi 87 <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
101 <&xilinx_ams 18>, <&xi 88 <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
102 <&xilinx_ams 21>, <&xi 89 <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
103 <&xilinx_ams 24>, <&xi 90 <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
104 <&xilinx_ams 27>, <&xi 91 <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
105 }; 92 };
106 <<
107 pwm-fan { <<
108 compatible = "pwm-fan"; <<
109 status = "okay"; <<
110 pwms = <&ttc0 2 40000 0>; <<
111 }; <<
112 }; 93 };
113 94
114 &modepin_gpio { 95 &modepin_gpio {
115 label = "modepin"; 96 label = "modepin";
116 }; 97 };
117 98
118 &ttc0 { <<
119 status = "okay"; <<
120 #pwm-cells = <3>; <<
121 }; <<
122 <<
123 &uart1 { /* MIO36/MIO37 */ 99 &uart1 { /* MIO36/MIO37 */
124 status = "okay"; 100 status = "okay";
125 }; 101 };
126 102
127 &pinctrl0 { 103 &pinctrl0 {
128 status = "okay"; 104 status = "okay";
129 pinctrl_sdhci0_default: sdhci0-default 105 pinctrl_sdhci0_default: sdhci0-default {
130 conf { 106 conf {
131 groups = "sdio0_0_grp" 107 groups = "sdio0_0_grp";
132 slew-rate = <SLEW_RATE 108 slew-rate = <SLEW_RATE_SLOW>;
133 power-source = <IO_STA 109 power-source = <IO_STANDARD_LVCMOS18>;
134 bias-disable; 110 bias-disable;
135 }; 111 };
136 112
137 mux { 113 mux {
138 groups = "sdio0_0_grp" 114 groups = "sdio0_0_grp";
139 function = "sdio0"; 115 function = "sdio0";
140 }; 116 };
141 }; 117 };
142 }; 118 };
143 119
144 &qspi { /* MIO 0-5 - U143 */ 120 &qspi { /* MIO 0-5 - U143 */
145 status = "okay"; 121 status = "okay";
146 spi_flash: flash@0 { /* MT25QU512A */ 122 spi_flash: flash@0 { /* MT25QU512A */
147 compatible = "jedec,spi-nor"; !! 123 compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
>> 124 #address-cells = <1>;
>> 125 #size-cells = <1>;
148 reg = <0>; 126 reg = <0>;
149 spi-tx-bus-width = <4>; 127 spi-tx-bus-width = <4>;
150 spi-rx-bus-width = <4>; 128 spi-rx-bus-width = <4>;
151 spi-max-frequency = <40000000> 129 spi-max-frequency = <40000000>; /* 40MHz */
152 130
153 partitions { 131 partitions {
154 compatible = "fixed-pa 132 compatible = "fixed-partitions";
155 #address-cells = <1>; 133 #address-cells = <1>;
156 #size-cells = <1>; 134 #size-cells = <1>;
157 135
158 partition@0 { 136 partition@0 {
159 label = "Image 137 label = "Image Selector";
160 reg = <0x0 0x8 138 reg = <0x0 0x80000>; /* 512KB */
161 read-only; 139 read-only;
162 lock; 140 lock;
163 }; 141 };
164 partition@80000 { 142 partition@80000 {
165 label = "Image 143 label = "Image Selector Golden";
166 reg = <0x80000 144 reg = <0x80000 0x80000>; /* 512KB */
167 read-only; 145 read-only;
168 lock; 146 lock;
169 }; 147 };
170 partition@100000 { 148 partition@100000 {
171 label = "Persi 149 label = "Persistent Register";
172 reg = <0x10000 150 reg = <0x100000 0x20000>; /* 128KB */
173 }; 151 };
174 partition@120000 { 152 partition@120000 {
175 label = "Persi 153 label = "Persistent Register Backup";
176 reg = <0x12000 154 reg = <0x120000 0x20000>; /* 128KB */
177 }; 155 };
178 partition@140000 { 156 partition@140000 {
179 label = "Open_ 157 label = "Open_1";
180 reg = <0x14000 158 reg = <0x140000 0xC0000>; /* 768KB */
181 }; 159 };
182 partition@200000 { 160 partition@200000 {
183 label = "Image 161 label = "Image A (FSBL, PMU, ATF, U-Boot)";
184 reg = <0x20000 162 reg = <0x200000 0xD00000>; /* 13MB */
185 }; 163 };
186 partition@f00000 { 164 partition@f00000 {
187 label = "ImgSe 165 label = "ImgSel Image A Catch";
188 reg = <0xF0000 166 reg = <0xF00000 0x80000>; /* 512KB */
189 read-only; 167 read-only;
190 lock; 168 lock;
191 }; 169 };
192 partition@f80000 { 170 partition@f80000 {
193 label = "Image 171 label = "Image B (FSBL, PMU, ATF, U-Boot)";
194 reg = <0xF8000 172 reg = <0xF80000 0xD00000>; /* 13MB */
195 }; 173 };
196 partition@1c80000 { 174 partition@1c80000 {
197 label = "ImgSe 175 label = "ImgSel Image B Catch";
198 reg = <0x1C800 176 reg = <0x1C80000 0x80000>; /* 512KB */
199 read-only; 177 read-only;
200 lock; 178 lock;
201 }; 179 };
202 partition@1d00000 { 180 partition@1d00000 {
203 label = "Open_ 181 label = "Open_2";
204 reg = <0x1D000 182 reg = <0x1D00000 0x100000>; /* 1MB */
205 }; 183 };
206 partition@1e00000 { 184 partition@1e00000 {
207 label = "Recov 185 label = "Recovery Image";
208 reg = <0x1E000 186 reg = <0x1E00000 0x200000>; /* 2MB */
209 read-only; 187 read-only;
210 lock; 188 lock;
211 }; 189 };
212 partition@2000000 { 190 partition@2000000 {
213 label = "Recov 191 label = "Recovery Image Backup";
214 reg = <0x20000 192 reg = <0x2000000 0x200000>; /* 2MB */
215 read-only; 193 read-only;
216 lock; 194 lock;
217 }; 195 };
218 partition@2200000 { 196 partition@2200000 {
219 label = "U-Boo 197 label = "U-Boot storage variables";
220 reg = <0x22000 198 reg = <0x2200000 0x20000>; /* 128KB */
221 }; 199 };
222 partition@2220000 { 200 partition@2220000 {
223 label = "U-Boo 201 label = "U-Boot storage variables backup";
224 reg = <0x22200 202 reg = <0x2220000 0x20000>; /* 128KB */
225 }; 203 };
226 partition@2240000 { 204 partition@2240000 {
227 label = "SHA25 205 label = "SHA256";
228 reg = <0x22400 206 reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
229 read-only; 207 read-only;
230 lock; 208 lock;
231 }; 209 };
232 partition@2280000 { 210 partition@2280000 {
233 label = "Secur 211 label = "Secure OS Storage";
234 reg = <0x22800 212 reg = <0x2280000 0x20000>; /* 128KB */
235 }; 213 };
236 partition@22a0000 { !! 214 partition@22A0000 {
237 label = "User" 215 label = "User";
238 reg = <0x22a00 !! 216 reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
239 }; 217 };
240 }; 218 };
241 }; 219 };
242 }; 220 };
243 221
244 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALB 222 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
245 status = "okay"; 223 status = "okay";
246 pinctrl-names = "default"; 224 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_sdhci0_default>; 225 pinctrl-0 = <&pinctrl_sdhci0_default>;
248 non-removable; 226 non-removable;
249 disable-wp; 227 disable-wp;
250 bus-width = <8>; 228 bus-width = <8>;
251 xlnx,mio-bank = <0>; 229 xlnx,mio-bank = <0>;
252 assigned-clock-rates = <187498123>; 230 assigned-clock-rates = <187498123>;
253 }; 231 };
254 232
255 &spi1 { /* MIO6, 9-11 */ 233 &spi1 { /* MIO6, 9-11 */
256 status = "okay"; 234 status = "okay";
257 label = "TPM"; 235 label = "TPM";
258 num-cs = <1>; 236 num-cs = <1>;
259 tpm@0 { /* slm9670 - U144 */ 237 tpm@0 { /* slm9670 - U144 */
260 compatible = "infineon,slb9670 238 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
261 reg = <0>; 239 reg = <0>;
262 spi-max-frequency = <18500000> 240 spi-max-frequency = <18500000>;
263 }; 241 };
264 }; 242 };
265 243
266 &i2c1 { 244 &i2c1 {
267 status = "okay"; 245 status = "okay";
268 bootph-all; 246 bootph-all;
269 clock-frequency = <400000>; 247 clock-frequency = <400000>;
270 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIG !! 248 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
271 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIG !! 249 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
272 250
273 eeprom: eeprom@50 { /* u46 - also at a 251 eeprom: eeprom@50 { /* u46 - also at address 0x58 */
274 bootph-all; 252 bootph-all;
275 compatible = "st,24c64", "atme 253 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
276 reg = <0x50>; 254 reg = <0x50>;
277 /* WP pin EE_WP_EN connected t 255 /* WP pin EE_WP_EN connected to slg7x644092@68 */
278 }; 256 };
279 257
280 eeprom_cc: eeprom@51 { /* required by 258 eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
281 bootph-all; 259 bootph-all;
282 compatible = "st,24c64", "atme 260 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
283 reg = <0x51>; 261 reg = <0x51>;
284 }; 262 };
285 263
286 /* da9062@30 - u170 - also at address 264 /* da9062@30 - u170 - also at address 0x31 */
287 /* da9131@33 - u167 */ 265 /* da9131@33 - u167 */
288 da9131: pmic@33 { 266 da9131: pmic@33 {
289 compatible = "dlg,da9131"; 267 compatible = "dlg,da9131";
290 reg = <0x33>; 268 reg = <0x33>;
291 regulators { 269 regulators {
292 da9131_buck1: buck1 { 270 da9131_buck1: buck1 {
293 regulator-name 271 regulator-name = "da9131_buck1";
294 regulator-boot 272 regulator-boot-on;
295 regulator-alwa 273 regulator-always-on;
296 }; 274 };
297 da9131_buck2: buck2 { 275 da9131_buck2: buck2 {
298 regulator-name 276 regulator-name = "da9131_buck2";
299 regulator-boot 277 regulator-boot-on;
300 regulator-alwa 278 regulator-always-on;
301 }; 279 };
302 }; 280 };
303 }; 281 };
304 282
305 /* da9130@32 - u166 */ 283 /* da9130@32 - u166 */
306 da9130: pmic@32 { 284 da9130: pmic@32 {
307 compatible = "dlg,da9130"; 285 compatible = "dlg,da9130";
308 reg = <0x32>; 286 reg = <0x32>;
309 regulators { 287 regulators {
310 da9130_buck1: buck1 { 288 da9130_buck1: buck1 {
311 regulator-name 289 regulator-name = "da9130_buck1";
312 regulator-boot 290 regulator-boot-on;
313 regulator-alwa 291 regulator-always-on;
314 }; 292 };
315 }; 293 };
316 }; 294 };
317 295
318 /* slg7x644091@70 - u168 NOT accessibl 296 /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
319 /* 297 /*
320 * stdp4320 - u27 FW has below two iss 298 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
321 * Device acknowledging to addresses 0 299 * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
322 * Address conflict with slg7x644091@7 300 * Address conflict with slg7x644091@70 making both the devices NOT accessible.
323 * With the FW fix, stdp4320 should re 301 * With the FW fix, stdp4320 should respond to address 0x73 only.
324 */ 302 */
325 /* slg7x644092@68 - u169 */ 303 /* slg7x644092@68 - u169 */
326 /* Also connected via JA1C as C23/C24 304 /* Also connected via JA1C as C23/C24 */
327 }; 305 };
328 306
329 &gpio { 307 &gpio {
330 status = "okay"; 308 status = "okay";
331 gpio-line-names = "QSPI_CLK", "QSPI_DQ 309 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
332 "QSPI_CS_B", "SPI_CL 310 "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
333 "SPI_MISO", "SPI_MOS 311 "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
334 "EMMC_DAT2", "EMMC_D 312 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
335 "EMMC_DAT7", "EMMC_C 313 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
336 "I2C1_SDA", "", "", 314 "I2C1_SDA", "", "", "", "", /* 25 - 29 */
337 "", "", "", "", "", 315 "", "", "", "", "", /* 30 - 34 */
338 "", "", "", "", "", 316 "", "", "", "", "", /* 35 - 39 */
339 "", "", "", "", "", 317 "", "", "", "", "", /* 40 - 44 */
340 "", "", "", "", "", 318 "", "", "", "", "", /* 45 - 49 */
341 "", "", "", "", "", 319 "", "", "", "", "", /* 50 - 54 */
342 "", "", "", "", "", 320 "", "", "", "", "", /* 55 - 59 */
343 "", "", "", "", "", 321 "", "", "", "", "", /* 60 - 64 */
344 "", "", "", "", "", 322 "", "", "", "", "", /* 65 - 69 */
345 "", "", "", "", "", 323 "", "", "", "", "", /* 70 - 74 */
346 "", "", "", /* 75 - 324 "", "", "", /* 75 - 77, MIO end and EMIO start */
347 "", "", /* 78 - 79 * 325 "", "", /* 78 - 79 */
348 "", "", "", "", "", 326 "", "", "", "", "", /* 80 - 84 */
349 "", "", "", "", "", 327 "", "", "", "", "", /* 85 - 89 */
350 "", "", "", "", "", 328 "", "", "", "", "", /* 90 - 94 */
351 "", "", "", "", "", 329 "", "", "", "", "", /* 95 - 99 */
352 "", "", "", "", "", 330 "", "", "", "", "", /* 100 - 104 */
353 "", "", "", "", "", 331 "", "", "", "", "", /* 105 - 109 */
354 "", "", "", "", "", 332 "", "", "", "", "", /* 110 - 114 */
355 "", "", "", "", "", 333 "", "", "", "", "", /* 115 - 119 */
356 "", "", "", "", "", 334 "", "", "", "", "", /* 120 - 124 */
357 "", "", "", "", "", 335 "", "", "", "", "", /* 125 - 129 */
358 "", "", "", "", "", 336 "", "", "", "", "", /* 130 - 134 */
359 "", "", "", "", "", 337 "", "", "", "", "", /* 135 - 139 */
360 "", "", "", "", "", 338 "", "", "", "", "", /* 140 - 144 */
361 "", "", "", "", "", 339 "", "", "", "", "", /* 145 - 149 */
362 "", "", "", "", "", 340 "", "", "", "", "", /* 150 - 154 */
363 "", "", "", "", "", 341 "", "", "", "", "", /* 155 - 159 */
364 "", "", "", "", "", 342 "", "", "", "", "", /* 160 - 164 */
365 "", "", "", "", "", 343 "", "", "", "", "", /* 165 - 169 */
366 "", "", "", ""; /* 1 344 "", "", "", ""; /* 170 - 173 */
367 }; 345 };
368 346
369 &xilinx_ams { 347 &xilinx_ams {
370 status = "okay"; 348 status = "okay";
371 }; 349 };
372 350
373 &ams_ps { 351 &ams_ps {
374 status = "okay"; 352 status = "okay";
375 }; 353 };
376 354
377 &ams_pl { 355 &ams_pl {
378 status = "okay"; 356 status = "okay";
379 }; 357 };
380 358
381 &zynqmp_dpsub { 359 &zynqmp_dpsub {
382 status = "okay"; 360 status = "okay";
383 }; 361 };
384 362
385 &rtc { 363 &rtc {
386 status = "okay"; 364 status = "okay";
387 }; 365 };
388 366
389 &lpd_dma_chan1 { 367 &lpd_dma_chan1 {
390 status = "okay"; 368 status = "okay";
391 }; 369 };
392 370
393 &lpd_dma_chan2 { 371 &lpd_dma_chan2 {
394 status = "okay"; 372 status = "okay";
395 }; 373 };
396 374
397 &lpd_dma_chan3 { 375 &lpd_dma_chan3 {
398 status = "okay"; 376 status = "okay";
399 }; 377 };
400 378
401 &lpd_dma_chan4 { 379 &lpd_dma_chan4 {
402 status = "okay"; 380 status = "okay";
403 }; 381 };
404 382
405 &lpd_dma_chan5 { 383 &lpd_dma_chan5 {
406 status = "okay"; 384 status = "okay";
407 }; 385 };
408 386
409 &lpd_dma_chan6 { 387 &lpd_dma_chan6 {
410 status = "okay"; 388 status = "okay";
411 }; 389 };
412 390
413 &lpd_dma_chan7 { 391 &lpd_dma_chan7 {
414 status = "okay"; 392 status = "okay";
415 }; 393 };
416 394
417 &lpd_dma_chan8 { 395 &lpd_dma_chan8 {
418 status = "okay"; 396 status = "okay";
419 }; 397 };
420 398
421 &fpd_dma_chan1 { 399 &fpd_dma_chan1 {
422 status = "okay"; 400 status = "okay";
423 }; 401 };
424 402
425 &fpd_dma_chan2 { 403 &fpd_dma_chan2 {
426 status = "okay"; 404 status = "okay";
427 }; 405 };
428 406
429 &fpd_dma_chan3 { 407 &fpd_dma_chan3 {
430 status = "okay"; 408 status = "okay";
431 }; 409 };
432 410
433 &fpd_dma_chan4 { 411 &fpd_dma_chan4 {
434 status = "okay"; 412 status = "okay";
435 }; 413 };
436 414
437 &fpd_dma_chan5 { 415 &fpd_dma_chan5 {
438 status = "okay"; 416 status = "okay";
439 }; 417 };
440 418
441 &fpd_dma_chan6 { 419 &fpd_dma_chan6 {
442 status = "okay"; 420 status = "okay";
443 }; 421 };
444 422
445 &fpd_dma_chan7 { 423 &fpd_dma_chan7 {
446 status = "okay"; 424 status = "okay";
447 }; 425 };
448 426
449 &fpd_dma_chan8 { 427 &fpd_dma_chan8 {
450 status = "okay"; 428 status = "okay";
451 }; 429 };
452 430
453 &gpu { 431 &gpu {
454 status = "okay"; 432 status = "okay";
455 }; 433 };
456 434
457 &lpd_watchdog { 435 &lpd_watchdog {
458 status = "okay"; 436 status = "okay";
459 }; 437 };
460 438
461 &watchdog0 { 439 &watchdog0 {
462 status = "okay"; 440 status = "okay";
463 }; 441 };
464 442
465 &cpu_opp_table { 443 &cpu_opp_table {
466 opp00 { 444 opp00 {
467 opp-hz = /bits/ 64 <1333333333 445 opp-hz = /bits/ 64 <1333333333>;
468 }; 446 };
469 opp01 { 447 opp01 {
470 opp-hz = /bits/ 64 <666666666> 448 opp-hz = /bits/ 64 <666666666>;
471 }; 449 };
472 opp02 { 450 opp02 {
473 opp-hz = /bits/ 64 <444444444> 451 opp-hz = /bits/ 64 <444444444>;
474 }; 452 };
475 opp03 { 453 opp03 {
476 opp-hz = /bits/ 64 <333333333> 454 opp-hz = /bits/ 64 <333333333>;
477 }; 455 };
478 }; 456 };
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