1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/ !! 3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
4 * 4 *
5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 * (C) Copyright 2023 - 2024, Advanced Micro D <<
7 * 6 *
8 * Michal Simek <michal.simek@amd.com> 7 * Michal Simek <michal.simek@amd.com>
9 */ 8 */
10 9
11 /dts-v1/; 10 /dts-v1/;
12 11
13 #include "zynqmp.dtsi" 12 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi" 13 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h> 14 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/phy/phy.h> 16 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h 17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 18
20 / { 19 / {
21 model = "ZynqMP SM-K26 Rev2/1/B/A"; !! 20 model = "ZynqMP SM-K26 Rev1/B/A";
22 compatible = "xlnx,zynqmp-sm-k26-rev2" !! 21 compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
23 "xlnx,zynqmp-sm-k26-rev1" <<
24 "xlnx,zynqmp-sm-k26-revA" 22 "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
25 "xlnx,zynqmp"; 23 "xlnx,zynqmp";
26 24
27 aliases { 25 aliases {
28 i2c0 = &i2c0; 26 i2c0 = &i2c0;
29 i2c1 = &i2c1; 27 i2c1 = &i2c1;
30 mmc0 = &sdhci0; 28 mmc0 = &sdhci0;
31 mmc1 = &sdhci1; 29 mmc1 = &sdhci1;
32 nvmem0 = &eeprom; 30 nvmem0 = &eeprom;
33 nvmem1 = &eeprom_cc; 31 nvmem1 = &eeprom_cc;
34 rtc0 = &rtc; 32 rtc0 = &rtc;
35 serial0 = &uart0; 33 serial0 = &uart0;
36 serial1 = &uart1; 34 serial1 = &uart1;
37 serial2 = &dcc; 35 serial2 = &dcc;
38 spi0 = &qspi; 36 spi0 = &qspi;
39 spi1 = &spi0; 37 spi1 = &spi0;
40 spi2 = &spi1; 38 spi2 = &spi1;
41 usb0 = &usb0; 39 usb0 = &usb0;
42 usb1 = &usb1; 40 usb1 = &usb1;
43 }; 41 };
44 42
45 chosen { 43 chosen {
46 bootargs = "earlycon"; 44 bootargs = "earlycon";
47 stdout-path = "serial1:115200n 45 stdout-path = "serial1:115200n8";
48 }; 46 };
49 47
50 memory@0 { 48 memory@0 {
51 device_type = "memory"; /* 4GB 49 device_type = "memory"; /* 4GB */
52 reg = <0x0 0x0 0x0 0x80000000> 50 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
53 }; 51 };
54 52
55 reserved-memory { 53 reserved-memory {
56 #address-cells = <2>; 54 #address-cells = <2>;
57 #size-cells = <2>; 55 #size-cells = <2>;
58 ranges; 56 ranges;
59 57
60 pmu_region: pmu@7ff00000 { 58 pmu_region: pmu@7ff00000 {
61 reg = <0x0 0x7ff00000 59 reg = <0x0 0x7ff00000 0x0 0x100000>;
62 no-map; 60 no-map;
63 }; 61 };
64 }; 62 };
65 63
66 gpio-keys { 64 gpio-keys {
67 compatible = "gpio-keys"; 65 compatible = "gpio-keys";
68 autorepeat; 66 autorepeat;
69 key-fwuen { 67 key-fwuen {
70 label = "fwuen"; 68 label = "fwuen";
71 gpios = <&gpio 12 GPIO 69 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
72 linux,code = <BTN_MISC 70 linux,code = <BTN_MISC>;
73 wakeup-source; 71 wakeup-source;
74 autorepeat; 72 autorepeat;
75 }; 73 };
76 }; 74 };
77 75
78 leds { 76 leds {
79 compatible = "gpio-leds"; 77 compatible = "gpio-leds";
80 ds35-led { 78 ds35-led {
81 label = "heartbeat"; 79 label = "heartbeat";
82 gpios = <&gpio 7 GPIO_ 80 gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
83 linux,default-trigger 81 linux,default-trigger = "heartbeat";
84 }; 82 };
85 83
86 ds36-led { 84 ds36-led {
87 label = "vbus_det"; 85 label = "vbus_det";
88 gpios = <&gpio 8 GPIO_ 86 gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
89 default-state = "on"; 87 default-state = "on";
90 }; 88 };
91 }; 89 };
92 90
93 ams { 91 ams {
94 compatible = "iio-hwmon"; 92 compatible = "iio-hwmon";
95 io-channels = <&xilinx_ams 0>, 93 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
96 <&xilinx_ams 3>, <&xil 94 <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
97 <&xilinx_ams 6>, <&xil 95 <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
98 <&xilinx_ams 9>, <&xil 96 <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
99 <&xilinx_ams 12>, <&xi 97 <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
100 <&xilinx_ams 15>, <&xi 98 <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
101 <&xilinx_ams 18>, <&xi 99 <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
102 <&xilinx_ams 21>, <&xi 100 <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
103 <&xilinx_ams 24>, <&xi 101 <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
104 <&xilinx_ams 27>, <&xi 102 <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
105 }; 103 };
106 <<
107 pwm-fan { <<
108 compatible = "pwm-fan"; <<
109 status = "okay"; <<
110 pwms = <&ttc0 2 40000 0>; <<
111 }; <<
112 }; 104 };
113 105
114 &modepin_gpio { 106 &modepin_gpio {
115 label = "modepin"; 107 label = "modepin";
116 }; 108 };
117 109
118 &ttc0 { <<
119 status = "okay"; <<
120 #pwm-cells = <3>; <<
121 }; <<
122 <<
123 &uart1 { /* MIO36/MIO37 */ 110 &uart1 { /* MIO36/MIO37 */
124 status = "okay"; 111 status = "okay";
125 }; 112 };
126 113
127 &pinctrl0 { 114 &pinctrl0 {
128 status = "okay"; 115 status = "okay";
129 pinctrl_sdhci0_default: sdhci0-default 116 pinctrl_sdhci0_default: sdhci0-default {
130 conf { 117 conf {
131 groups = "sdio0_0_grp" 118 groups = "sdio0_0_grp";
132 slew-rate = <SLEW_RATE 119 slew-rate = <SLEW_RATE_SLOW>;
133 power-source = <IO_STA 120 power-source = <IO_STANDARD_LVCMOS18>;
134 bias-disable; 121 bias-disable;
135 }; 122 };
136 123
137 mux { 124 mux {
138 groups = "sdio0_0_grp" 125 groups = "sdio0_0_grp";
139 function = "sdio0"; 126 function = "sdio0";
140 }; 127 };
141 }; 128 };
142 }; 129 };
143 130
144 &qspi { /* MIO 0-5 - U143 */ 131 &qspi { /* MIO 0-5 - U143 */
145 status = "okay"; 132 status = "okay";
146 spi_flash: flash@0 { /* MT25QU512A */ 133 spi_flash: flash@0 { /* MT25QU512A */
147 compatible = "jedec,spi-nor"; !! 134 compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
>> 135 #address-cells = <1>;
>> 136 #size-cells = <1>;
148 reg = <0>; 137 reg = <0>;
149 spi-tx-bus-width = <4>; 138 spi-tx-bus-width = <4>;
150 spi-rx-bus-width = <4>; 139 spi-rx-bus-width = <4>;
151 spi-max-frequency = <40000000> 140 spi-max-frequency = <40000000>; /* 40MHz */
152 141
153 partitions { 142 partitions {
154 compatible = "fixed-pa 143 compatible = "fixed-partitions";
155 #address-cells = <1>; 144 #address-cells = <1>;
156 #size-cells = <1>; 145 #size-cells = <1>;
157 146
158 partition@0 { 147 partition@0 {
159 label = "Image 148 label = "Image Selector";
160 reg = <0x0 0x8 149 reg = <0x0 0x80000>; /* 512KB */
161 read-only; 150 read-only;
162 lock; 151 lock;
163 }; 152 };
164 partition@80000 { 153 partition@80000 {
165 label = "Image 154 label = "Image Selector Golden";
166 reg = <0x80000 155 reg = <0x80000 0x80000>; /* 512KB */
167 read-only; 156 read-only;
168 lock; 157 lock;
169 }; 158 };
170 partition@100000 { 159 partition@100000 {
171 label = "Persi 160 label = "Persistent Register";
172 reg = <0x10000 161 reg = <0x100000 0x20000>; /* 128KB */
173 }; 162 };
174 partition@120000 { 163 partition@120000 {
175 label = "Persi 164 label = "Persistent Register Backup";
176 reg = <0x12000 165 reg = <0x120000 0x20000>; /* 128KB */
177 }; 166 };
178 partition@140000 { 167 partition@140000 {
179 label = "Open_ 168 label = "Open_1";
180 reg = <0x14000 169 reg = <0x140000 0xC0000>; /* 768KB */
181 }; 170 };
182 partition@200000 { 171 partition@200000 {
183 label = "Image 172 label = "Image A (FSBL, PMU, ATF, U-Boot)";
184 reg = <0x20000 173 reg = <0x200000 0xD00000>; /* 13MB */
185 }; 174 };
186 partition@f00000 { 175 partition@f00000 {
187 label = "ImgSe 176 label = "ImgSel Image A Catch";
188 reg = <0xF0000 177 reg = <0xF00000 0x80000>; /* 512KB */
189 read-only; 178 read-only;
190 lock; 179 lock;
191 }; 180 };
192 partition@f80000 { 181 partition@f80000 {
193 label = "Image 182 label = "Image B (FSBL, PMU, ATF, U-Boot)";
194 reg = <0xF8000 183 reg = <0xF80000 0xD00000>; /* 13MB */
195 }; 184 };
196 partition@1c80000 { 185 partition@1c80000 {
197 label = "ImgSe 186 label = "ImgSel Image B Catch";
198 reg = <0x1C800 187 reg = <0x1C80000 0x80000>; /* 512KB */
199 read-only; 188 read-only;
200 lock; 189 lock;
201 }; 190 };
202 partition@1d00000 { 191 partition@1d00000 {
203 label = "Open_ 192 label = "Open_2";
204 reg = <0x1D000 193 reg = <0x1D00000 0x100000>; /* 1MB */
205 }; 194 };
206 partition@1e00000 { 195 partition@1e00000 {
207 label = "Recov 196 label = "Recovery Image";
208 reg = <0x1E000 197 reg = <0x1E00000 0x200000>; /* 2MB */
209 read-only; 198 read-only;
210 lock; 199 lock;
211 }; 200 };
212 partition@2000000 { 201 partition@2000000 {
213 label = "Recov 202 label = "Recovery Image Backup";
214 reg = <0x20000 203 reg = <0x2000000 0x200000>; /* 2MB */
215 read-only; 204 read-only;
216 lock; 205 lock;
217 }; 206 };
218 partition@2200000 { 207 partition@2200000 {
219 label = "U-Boo 208 label = "U-Boot storage variables";
220 reg = <0x22000 209 reg = <0x2200000 0x20000>; /* 128KB */
221 }; 210 };
222 partition@2220000 { 211 partition@2220000 {
223 label = "U-Boo 212 label = "U-Boot storage variables backup";
224 reg = <0x22200 213 reg = <0x2220000 0x20000>; /* 128KB */
225 }; 214 };
226 partition@2240000 { 215 partition@2240000 {
227 label = "SHA25 216 label = "SHA256";
228 reg = <0x22400 217 reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
229 read-only; 218 read-only;
230 lock; 219 lock;
231 }; 220 };
232 partition@2280000 { 221 partition@2280000 {
233 label = "Secur 222 label = "Secure OS Storage";
234 reg = <0x22800 223 reg = <0x2280000 0x20000>; /* 128KB */
235 }; 224 };
236 partition@22a0000 { !! 225 partition@22A0000 {
237 label = "User" 226 label = "User";
238 reg = <0x22a00 !! 227 reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
239 }; 228 };
240 }; 229 };
241 }; 230 };
242 }; 231 };
243 232
244 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALB 233 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
245 status = "okay"; 234 status = "okay";
246 pinctrl-names = "default"; 235 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_sdhci0_default>; 236 pinctrl-0 = <&pinctrl_sdhci0_default>;
248 non-removable; 237 non-removable;
249 disable-wp; 238 disable-wp;
250 bus-width = <8>; 239 bus-width = <8>;
251 xlnx,mio-bank = <0>; 240 xlnx,mio-bank = <0>;
252 assigned-clock-rates = <187498123>; 241 assigned-clock-rates = <187498123>;
253 }; 242 };
254 243
255 &spi1 { /* MIO6, 9-11 */ 244 &spi1 { /* MIO6, 9-11 */
256 status = "okay"; 245 status = "okay";
257 label = "TPM"; 246 label = "TPM";
258 num-cs = <1>; 247 num-cs = <1>;
259 tpm@0 { /* slm9670 - U144 */ 248 tpm@0 { /* slm9670 - U144 */
260 compatible = "infineon,slb9670 249 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
261 reg = <0>; 250 reg = <0>;
262 spi-max-frequency = <18500000> 251 spi-max-frequency = <18500000>;
263 }; 252 };
264 }; 253 };
265 254
266 &i2c1 { 255 &i2c1 {
267 status = "okay"; 256 status = "okay";
268 bootph-all; 257 bootph-all;
269 clock-frequency = <400000>; 258 clock-frequency = <400000>;
270 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIG 259 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
271 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIG 260 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
272 261
273 eeprom: eeprom@50 { /* u46 - also at a 262 eeprom: eeprom@50 { /* u46 - also at address 0x58 */
274 bootph-all; 263 bootph-all;
275 compatible = "st,24c64", "atme 264 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
276 reg = <0x50>; 265 reg = <0x50>;
277 /* WP pin EE_WP_EN connected t 266 /* WP pin EE_WP_EN connected to slg7x644092@68 */
278 }; 267 };
279 268
280 eeprom_cc: eeprom@51 { /* required by 269 eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
281 bootph-all; 270 bootph-all;
282 compatible = "st,24c64", "atme 271 compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
283 reg = <0x51>; 272 reg = <0x51>;
284 }; 273 };
285 274
286 /* da9062@30 - u170 - also at address 275 /* da9062@30 - u170 - also at address 0x31 */
287 /* da9131@33 - u167 */ 276 /* da9131@33 - u167 */
288 da9131: pmic@33 { 277 da9131: pmic@33 {
289 compatible = "dlg,da9131"; 278 compatible = "dlg,da9131";
290 reg = <0x33>; 279 reg = <0x33>;
291 regulators { 280 regulators {
292 da9131_buck1: buck1 { 281 da9131_buck1: buck1 {
293 regulator-name 282 regulator-name = "da9131_buck1";
294 regulator-boot 283 regulator-boot-on;
295 regulator-alwa 284 regulator-always-on;
296 }; 285 };
297 da9131_buck2: buck2 { 286 da9131_buck2: buck2 {
298 regulator-name 287 regulator-name = "da9131_buck2";
299 regulator-boot 288 regulator-boot-on;
300 regulator-alwa 289 regulator-always-on;
301 }; 290 };
302 }; 291 };
303 }; 292 };
304 293
305 /* da9130@32 - u166 */ 294 /* da9130@32 - u166 */
306 da9130: pmic@32 { 295 da9130: pmic@32 {
307 compatible = "dlg,da9130"; 296 compatible = "dlg,da9130";
308 reg = <0x32>; 297 reg = <0x32>;
309 regulators { 298 regulators {
310 da9130_buck1: buck1 { 299 da9130_buck1: buck1 {
311 regulator-name 300 regulator-name = "da9130_buck1";
312 regulator-boot 301 regulator-boot-on;
313 regulator-alwa 302 regulator-always-on;
314 }; 303 };
315 }; 304 };
316 }; 305 };
317 306
318 /* slg7x644091@70 - u168 NOT accessibl 307 /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
319 /* 308 /*
320 * stdp4320 - u27 FW has below two iss 309 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
321 * Device acknowledging to addresses 0 310 * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
322 * Address conflict with slg7x644091@7 311 * Address conflict with slg7x644091@70 making both the devices NOT accessible.
323 * With the FW fix, stdp4320 should re 312 * With the FW fix, stdp4320 should respond to address 0x73 only.
324 */ 313 */
325 /* slg7x644092@68 - u169 */ 314 /* slg7x644092@68 - u169 */
326 /* Also connected via JA1C as C23/C24 315 /* Also connected via JA1C as C23/C24 */
327 }; 316 };
328 317
329 &gpio { 318 &gpio {
330 status = "okay"; 319 status = "okay";
331 gpio-line-names = "QSPI_CLK", "QSPI_DQ 320 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
332 "QSPI_CS_B", "SPI_CL 321 "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
333 "SPI_MISO", "SPI_MOS 322 "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
334 "EMMC_DAT2", "EMMC_D 323 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
335 "EMMC_DAT7", "EMMC_C 324 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
336 "I2C1_SDA", "", "", 325 "I2C1_SDA", "", "", "", "", /* 25 - 29 */
337 "", "", "", "", "", 326 "", "", "", "", "", /* 30 - 34 */
338 "", "", "", "", "", 327 "", "", "", "", "", /* 35 - 39 */
339 "", "", "", "", "", 328 "", "", "", "", "", /* 40 - 44 */
340 "", "", "", "", "", 329 "", "", "", "", "", /* 45 - 49 */
341 "", "", "", "", "", 330 "", "", "", "", "", /* 50 - 54 */
342 "", "", "", "", "", 331 "", "", "", "", "", /* 55 - 59 */
343 "", "", "", "", "", 332 "", "", "", "", "", /* 60 - 64 */
344 "", "", "", "", "", 333 "", "", "", "", "", /* 65 - 69 */
345 "", "", "", "", "", 334 "", "", "", "", "", /* 70 - 74 */
346 "", "", "", /* 75 - 335 "", "", "", /* 75 - 77, MIO end and EMIO start */
347 "", "", /* 78 - 79 * 336 "", "", /* 78 - 79 */
348 "", "", "", "", "", 337 "", "", "", "", "", /* 80 - 84 */
349 "", "", "", "", "", 338 "", "", "", "", "", /* 85 - 89 */
350 "", "", "", "", "", 339 "", "", "", "", "", /* 90 - 94 */
351 "", "", "", "", "", 340 "", "", "", "", "", /* 95 - 99 */
352 "", "", "", "", "", 341 "", "", "", "", "", /* 100 - 104 */
353 "", "", "", "", "", 342 "", "", "", "", "", /* 105 - 109 */
354 "", "", "", "", "", 343 "", "", "", "", "", /* 110 - 114 */
355 "", "", "", "", "", 344 "", "", "", "", "", /* 115 - 119 */
356 "", "", "", "", "", 345 "", "", "", "", "", /* 120 - 124 */
357 "", "", "", "", "", 346 "", "", "", "", "", /* 125 - 129 */
358 "", "", "", "", "", 347 "", "", "", "", "", /* 130 - 134 */
359 "", "", "", "", "", 348 "", "", "", "", "", /* 135 - 139 */
360 "", "", "", "", "", 349 "", "", "", "", "", /* 140 - 144 */
361 "", "", "", "", "", 350 "", "", "", "", "", /* 145 - 149 */
362 "", "", "", "", "", 351 "", "", "", "", "", /* 150 - 154 */
363 "", "", "", "", "", 352 "", "", "", "", "", /* 155 - 159 */
364 "", "", "", "", "", 353 "", "", "", "", "", /* 160 - 164 */
365 "", "", "", "", "", 354 "", "", "", "", "", /* 165 - 169 */
366 "", "", "", ""; /* 1 355 "", "", "", ""; /* 170 - 173 */
367 }; 356 };
368 357
369 &xilinx_ams { 358 &xilinx_ams {
370 status = "okay"; 359 status = "okay";
371 }; 360 };
372 361
373 &ams_ps { 362 &ams_ps {
374 status = "okay"; 363 status = "okay";
375 }; 364 };
376 365
377 &ams_pl { 366 &ams_pl {
378 status = "okay"; 367 status = "okay";
379 }; 368 };
380 369
381 &zynqmp_dpsub { 370 &zynqmp_dpsub {
382 status = "okay"; 371 status = "okay";
383 }; 372 };
384 373
385 &rtc { 374 &rtc {
386 status = "okay"; 375 status = "okay";
387 }; 376 };
388 377
389 &lpd_dma_chan1 { 378 &lpd_dma_chan1 {
390 status = "okay"; 379 status = "okay";
391 }; 380 };
392 381
393 &lpd_dma_chan2 { 382 &lpd_dma_chan2 {
394 status = "okay"; 383 status = "okay";
395 }; 384 };
396 385
397 &lpd_dma_chan3 { 386 &lpd_dma_chan3 {
398 status = "okay"; 387 status = "okay";
399 }; 388 };
400 389
401 &lpd_dma_chan4 { 390 &lpd_dma_chan4 {
402 status = "okay"; 391 status = "okay";
403 }; 392 };
404 393
405 &lpd_dma_chan5 { 394 &lpd_dma_chan5 {
406 status = "okay"; 395 status = "okay";
407 }; 396 };
408 397
409 &lpd_dma_chan6 { 398 &lpd_dma_chan6 {
410 status = "okay"; 399 status = "okay";
411 }; 400 };
412 401
413 &lpd_dma_chan7 { 402 &lpd_dma_chan7 {
414 status = "okay"; 403 status = "okay";
415 }; 404 };
416 405
417 &lpd_dma_chan8 { 406 &lpd_dma_chan8 {
418 status = "okay"; 407 status = "okay";
419 }; 408 };
420 409
421 &fpd_dma_chan1 { 410 &fpd_dma_chan1 {
422 status = "okay"; 411 status = "okay";
423 }; 412 };
424 413
425 &fpd_dma_chan2 { 414 &fpd_dma_chan2 {
426 status = "okay"; 415 status = "okay";
427 }; 416 };
428 417
429 &fpd_dma_chan3 { 418 &fpd_dma_chan3 {
430 status = "okay"; 419 status = "okay";
431 }; 420 };
432 421
433 &fpd_dma_chan4 { 422 &fpd_dma_chan4 {
434 status = "okay"; 423 status = "okay";
435 }; 424 };
436 425
437 &fpd_dma_chan5 { 426 &fpd_dma_chan5 {
438 status = "okay"; 427 status = "okay";
439 }; 428 };
440 429
441 &fpd_dma_chan6 { 430 &fpd_dma_chan6 {
442 status = "okay"; 431 status = "okay";
443 }; 432 };
444 433
445 &fpd_dma_chan7 { 434 &fpd_dma_chan7 {
446 status = "okay"; 435 status = "okay";
447 }; 436 };
448 437
449 &fpd_dma_chan8 { 438 &fpd_dma_chan8 {
450 status = "okay"; 439 status = "okay";
451 }; 440 };
452 441
453 &gpu { 442 &gpu {
454 status = "okay"; 443 status = "okay";
455 }; 444 };
456 445
457 &lpd_watchdog { 446 &lpd_watchdog {
458 status = "okay"; 447 status = "okay";
459 }; 448 };
460 449
461 &watchdog0 { 450 &watchdog0 {
462 status = "okay"; 451 status = "okay";
463 }; 452 };
464 453
465 &cpu_opp_table { 454 &cpu_opp_table {
466 opp00 { 455 opp00 {
467 opp-hz = /bits/ 64 <1333333333 456 opp-hz = /bits/ 64 <1333333333>;
468 }; 457 };
469 opp01 { 458 opp01 {
470 opp-hz = /bits/ 64 <666666666> 459 opp-hz = /bits/ 64 <666666666>;
471 }; 460 };
472 opp02 { 461 opp02 {
473 opp-hz = /bits/ 64 <444444444> 462 opp-hz = /bits/ 64 <444444444>;
474 }; 463 };
475 opp03 { 464 opp03 {
476 opp-hz = /bits/ 64 <333333333> 465 opp-hz = /bits/ 64 <333333333>;
477 }; 466 };
478 }; 467 };
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