1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4 3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
4 * 4 *
5 * (C) Copyright 2015 - 2021, Xilinx, Inc. !! 5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
6 * 6 *
7 * Michal Simek <michal.simek@amd.com> !! 7 * Michal Simek <michal.simek@xilinx.com>
8 */ 8 */
9 9
10 /dts-v1/; 10 /dts-v1/;
11 11
12 #include "zynqmp.dtsi" 12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi" !! 13 #include "zynqmp-clk.dtsi"
14 14
15 / { 15 / {
16 model = "ZynqMP zc1751-xm018-dc4"; 16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xl 17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
18 18
19 aliases { 19 aliases {
20 ethernet0 = &gem0; 20 ethernet0 = &gem0;
21 ethernet1 = &gem1; 21 ethernet1 = &gem1;
22 ethernet2 = &gem2; 22 ethernet2 = &gem2;
23 ethernet3 = &gem3; 23 ethernet3 = &gem3;
24 i2c0 = &i2c0; 24 i2c0 = &i2c0;
25 i2c1 = &i2c1; 25 i2c1 = &i2c1;
26 rtc0 = &rtc; 26 rtc0 = &rtc;
27 serial0 = &uart0; 27 serial0 = &uart0;
28 serial1 = &uart1; 28 serial1 = &uart1;
29 spi0 = &qspi; <<
30 }; 29 };
31 30
32 chosen { 31 chosen {
33 bootargs = "earlycon"; 32 bootargs = "earlycon";
34 stdout-path = "serial0:115200n 33 stdout-path = "serial0:115200n8";
35 }; 34 };
36 35
37 memory@0 { 36 memory@0 {
38 device_type = "memory"; 37 device_type = "memory";
39 reg = <0x0 0x0 0x0 0x80000000> 38 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40 }; 39 };
41 }; 40 };
42 41
43 &can0 { 42 &can0 {
44 status = "okay"; 43 status = "okay";
45 }; 44 };
46 45
47 &can1 { 46 &can1 {
48 status = "okay"; 47 status = "okay";
49 }; 48 };
50 49
51 &fpd_dma_chan1 { 50 &fpd_dma_chan1 {
52 status = "okay"; 51 status = "okay";
53 }; 52 };
54 53
55 &fpd_dma_chan2 { 54 &fpd_dma_chan2 {
56 status = "okay"; 55 status = "okay";
57 }; 56 };
58 57
59 &fpd_dma_chan3 { 58 &fpd_dma_chan3 {
60 status = "okay"; 59 status = "okay";
61 }; 60 };
62 61
63 &fpd_dma_chan4 { 62 &fpd_dma_chan4 {
64 status = "okay"; 63 status = "okay";
65 }; 64 };
66 65
67 &fpd_dma_chan5 { 66 &fpd_dma_chan5 {
68 status = "okay"; 67 status = "okay";
69 }; 68 };
70 69
71 &fpd_dma_chan6 { 70 &fpd_dma_chan6 {
72 status = "okay"; 71 status = "okay";
73 }; 72 };
74 73
75 &fpd_dma_chan7 { 74 &fpd_dma_chan7 {
76 status = "okay"; 75 status = "okay";
77 }; 76 };
78 77
79 &fpd_dma_chan8 { 78 &fpd_dma_chan8 {
80 status = "okay"; 79 status = "okay";
81 }; 80 };
82 81
83 &lpd_dma_chan1 { 82 &lpd_dma_chan1 {
84 status = "okay"; 83 status = "okay";
85 }; 84 };
86 85
87 &lpd_dma_chan2 { 86 &lpd_dma_chan2 {
88 status = "okay"; 87 status = "okay";
89 }; 88 };
90 89
91 &lpd_dma_chan3 { 90 &lpd_dma_chan3 {
92 status = "okay"; 91 status = "okay";
93 }; 92 };
94 93
95 &lpd_dma_chan4 { 94 &lpd_dma_chan4 {
96 status = "okay"; 95 status = "okay";
97 }; 96 };
98 97
99 &lpd_dma_chan5 { 98 &lpd_dma_chan5 {
100 status = "okay"; 99 status = "okay";
101 }; 100 };
102 101
103 &lpd_dma_chan6 { 102 &lpd_dma_chan6 {
104 status = "okay"; 103 status = "okay";
105 }; 104 };
106 105
107 &lpd_dma_chan7 { 106 &lpd_dma_chan7 {
108 status = "okay"; 107 status = "okay";
109 }; 108 };
110 109
111 &lpd_dma_chan8 { 110 &lpd_dma_chan8 {
112 status = "okay"; 111 status = "okay";
113 }; 112 };
114 113
115 &gem0 { 114 &gem0 {
116 status = "okay"; 115 status = "okay";
117 phy-mode = "rgmii-id"; 116 phy-mode = "rgmii-id";
118 phy-handle = <ðernet_phy0>; 117 phy-handle = <ðernet_phy0>;
119 mdio: mdio { !! 118 ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
120 #address-cells = <1>; !! 119 reg = <0>;
121 #size-cells = <0>; !! 120 };
122 ethernet_phy0: ethernet-phy@0 !! 121 ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
123 reg = <0>; !! 122 reg = <7>;
124 }; !! 123 };
125 ethernet_phy7: ethernet-phy@7 !! 124 ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
126 reg = <7>; !! 125 reg = <3>;
127 }; !! 126 };
128 ethernet_phy3: ethernet-phy@3 !! 127 ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
129 reg = <3>; !! 128 reg = <8>;
130 }; <<
131 ethernet_phy8: ethernet-phy@8 <<
132 reg = <8>; <<
133 }; <<
134 }; 129 };
135 }; 130 };
136 131
137 &gem1 { 132 &gem1 {
138 status = "okay"; 133 status = "okay";
139 phy-mode = "rgmii-id"; 134 phy-mode = "rgmii-id";
140 phy-handle = <ðernet_phy7>; 135 phy-handle = <ðernet_phy7>;
141 }; 136 };
142 137
143 &gem2 { 138 &gem2 {
144 status = "okay"; 139 status = "okay";
145 phy-mode = "rgmii-id"; 140 phy-mode = "rgmii-id";
146 phy-handle = <ðernet_phy3>; 141 phy-handle = <ðernet_phy3>;
147 }; 142 };
148 143
149 &gem3 { 144 &gem3 {
150 status = "okay"; 145 status = "okay";
151 phy-mode = "rgmii-id"; 146 phy-mode = "rgmii-id";
152 phy-handle = <ðernet_phy8>; 147 phy-handle = <ðernet_phy8>;
153 }; 148 };
154 149
155 &gpio { 150 &gpio {
156 status = "okay"; 151 status = "okay";
157 }; 152 };
158 153
159 &gpu { <<
160 status = "okay"; <<
161 }; <<
162 <<
163 &i2c0 { 154 &i2c0 {
164 clock-frequency = <400000>; 155 clock-frequency = <400000>;
165 status = "okay"; 156 status = "okay";
166 }; 157 };
167 158
168 &i2c1 { 159 &i2c1 {
169 clock-frequency = <400000>; 160 clock-frequency = <400000>;
170 status = "okay"; 161 status = "okay";
171 }; 162 };
172 163
173 &qspi { <<
174 status = "okay"; <<
175 flash@0 { <<
176 compatible = "m25p80", "jedec, <<
177 #address-cells = <1>; <<
178 #size-cells = <1>; <<
179 reg = <0x0>; <<
180 spi-tx-bus-width = <4>; <<
181 spi-rx-bus-width = <4>; /* als <<
182 spi-max-frequency = <108000000 <<
183 }; <<
184 }; <<
185 <<
186 &rtc { 164 &rtc {
187 status = "okay"; 165 status = "okay";
188 }; 166 };
189 167
190 &uart0 { 168 &uart0 {
191 status = "okay"; 169 status = "okay";
192 }; 170 };
193 171
194 &uart1 { 172 &uart1 {
195 status = "okay"; 173 status = "okay";
196 }; 174 };
197 175
198 &watchdog0 { 176 &watchdog0 {
199 status = "okay"; <<
200 }; <<
201 <<
202 &zynqmp_dpdma { <<
203 status = "okay"; <<
204 }; <<
205 <<
206 &zynqmp_dpsub { <<
207 status = "okay"; 177 status = "okay";
208 }; 178 };
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