1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4 3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
4 * 4 *
5 * (C) Copyright 2015 - 2021, Xilinx, Inc. 5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
6 * 6 *
7 * Michal Simek <michal.simek@amd.com> !! 7 * Michal Simek <michal.simek@xilinx.com>
8 */ 8 */
9 9
10 /dts-v1/; 10 /dts-v1/;
11 11
12 #include "zynqmp.dtsi" 12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi" 13 #include "zynqmp-clk-ccf.dtsi"
14 14
15 / { 15 / {
16 model = "ZynqMP zc1751-xm018-dc4"; 16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xl 17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
18 18
19 aliases { 19 aliases {
20 ethernet0 = &gem0; 20 ethernet0 = &gem0;
21 ethernet1 = &gem1; 21 ethernet1 = &gem1;
22 ethernet2 = &gem2; 22 ethernet2 = &gem2;
23 ethernet3 = &gem3; 23 ethernet3 = &gem3;
24 i2c0 = &i2c0; 24 i2c0 = &i2c0;
25 i2c1 = &i2c1; 25 i2c1 = &i2c1;
26 rtc0 = &rtc; 26 rtc0 = &rtc;
27 serial0 = &uart0; 27 serial0 = &uart0;
28 serial1 = &uart1; 28 serial1 = &uart1;
29 spi0 = &qspi; 29 spi0 = &qspi;
30 }; 30 };
31 31
32 chosen { 32 chosen {
33 bootargs = "earlycon"; 33 bootargs = "earlycon";
34 stdout-path = "serial0:115200n 34 stdout-path = "serial0:115200n8";
35 }; 35 };
36 36
37 memory@0 { 37 memory@0 {
38 device_type = "memory"; 38 device_type = "memory";
39 reg = <0x0 0x0 0x0 0x80000000> 39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40 }; 40 };
41 }; 41 };
42 42
43 &can0 { 43 &can0 {
44 status = "okay"; 44 status = "okay";
45 }; 45 };
46 46
47 &can1 { 47 &can1 {
48 status = "okay"; 48 status = "okay";
49 }; 49 };
50 50
51 &fpd_dma_chan1 { 51 &fpd_dma_chan1 {
52 status = "okay"; 52 status = "okay";
53 }; 53 };
54 54
55 &fpd_dma_chan2 { 55 &fpd_dma_chan2 {
56 status = "okay"; 56 status = "okay";
57 }; 57 };
58 58
59 &fpd_dma_chan3 { 59 &fpd_dma_chan3 {
60 status = "okay"; 60 status = "okay";
61 }; 61 };
62 62
63 &fpd_dma_chan4 { 63 &fpd_dma_chan4 {
64 status = "okay"; 64 status = "okay";
65 }; 65 };
66 66
67 &fpd_dma_chan5 { 67 &fpd_dma_chan5 {
68 status = "okay"; 68 status = "okay";
69 }; 69 };
70 70
71 &fpd_dma_chan6 { 71 &fpd_dma_chan6 {
72 status = "okay"; 72 status = "okay";
73 }; 73 };
74 74
75 &fpd_dma_chan7 { 75 &fpd_dma_chan7 {
76 status = "okay"; 76 status = "okay";
77 }; 77 };
78 78
79 &fpd_dma_chan8 { 79 &fpd_dma_chan8 {
80 status = "okay"; 80 status = "okay";
81 }; 81 };
82 82
83 &lpd_dma_chan1 { 83 &lpd_dma_chan1 {
84 status = "okay"; 84 status = "okay";
85 }; 85 };
86 86
87 &lpd_dma_chan2 { 87 &lpd_dma_chan2 {
88 status = "okay"; 88 status = "okay";
89 }; 89 };
90 90
91 &lpd_dma_chan3 { 91 &lpd_dma_chan3 {
92 status = "okay"; 92 status = "okay";
93 }; 93 };
94 94
95 &lpd_dma_chan4 { 95 &lpd_dma_chan4 {
96 status = "okay"; 96 status = "okay";
97 }; 97 };
98 98
99 &lpd_dma_chan5 { 99 &lpd_dma_chan5 {
100 status = "okay"; 100 status = "okay";
101 }; 101 };
102 102
103 &lpd_dma_chan6 { 103 &lpd_dma_chan6 {
104 status = "okay"; 104 status = "okay";
105 }; 105 };
106 106
107 &lpd_dma_chan7 { 107 &lpd_dma_chan7 {
108 status = "okay"; 108 status = "okay";
109 }; 109 };
110 110
111 &lpd_dma_chan8 { 111 &lpd_dma_chan8 {
112 status = "okay"; 112 status = "okay";
113 }; 113 };
114 114
115 &gem0 { 115 &gem0 {
116 status = "okay"; 116 status = "okay";
117 phy-mode = "rgmii-id"; 117 phy-mode = "rgmii-id";
118 phy-handle = <ðernet_phy0>; 118 phy-handle = <ðernet_phy0>;
119 mdio: mdio { !! 119 ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
120 #address-cells = <1>; !! 120 reg = <0>;
121 #size-cells = <0>; !! 121 };
122 ethernet_phy0: ethernet-phy@0 !! 122 ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
123 reg = <0>; !! 123 reg = <7>;
124 }; !! 124 };
125 ethernet_phy7: ethernet-phy@7 !! 125 ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
126 reg = <7>; !! 126 reg = <3>;
127 }; !! 127 };
128 ethernet_phy3: ethernet-phy@3 !! 128 ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
129 reg = <3>; !! 129 reg = <8>;
130 }; <<
131 ethernet_phy8: ethernet-phy@8 <<
132 reg = <8>; <<
133 }; <<
134 }; 130 };
135 }; 131 };
136 132
137 &gem1 { 133 &gem1 {
138 status = "okay"; 134 status = "okay";
139 phy-mode = "rgmii-id"; 135 phy-mode = "rgmii-id";
140 phy-handle = <ðernet_phy7>; 136 phy-handle = <ðernet_phy7>;
141 }; 137 };
142 138
143 &gem2 { 139 &gem2 {
144 status = "okay"; 140 status = "okay";
145 phy-mode = "rgmii-id"; 141 phy-mode = "rgmii-id";
146 phy-handle = <ðernet_phy3>; 142 phy-handle = <ðernet_phy3>;
147 }; 143 };
148 144
149 &gem3 { 145 &gem3 {
150 status = "okay"; 146 status = "okay";
151 phy-mode = "rgmii-id"; 147 phy-mode = "rgmii-id";
152 phy-handle = <ðernet_phy8>; 148 phy-handle = <ðernet_phy8>;
153 }; 149 };
154 150
155 &gpio { 151 &gpio {
156 status = "okay"; 152 status = "okay";
157 }; 153 };
158 154
159 &gpu { <<
160 status = "okay"; <<
161 }; <<
162 <<
163 &i2c0 { 155 &i2c0 {
164 clock-frequency = <400000>; 156 clock-frequency = <400000>;
165 status = "okay"; 157 status = "okay";
166 }; 158 };
167 159
168 &i2c1 { 160 &i2c1 {
169 clock-frequency = <400000>; 161 clock-frequency = <400000>;
170 status = "okay"; 162 status = "okay";
171 }; 163 };
172 164
173 &qspi { 165 &qspi {
174 status = "okay"; 166 status = "okay";
175 flash@0 { 167 flash@0 {
176 compatible = "m25p80", "jedec, 168 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
177 #address-cells = <1>; 169 #address-cells = <1>;
178 #size-cells = <1>; 170 #size-cells = <1>;
179 reg = <0x0>; 171 reg = <0x0>;
180 spi-tx-bus-width = <4>; !! 172 spi-tx-bus-width = <1>;
181 spi-rx-bus-width = <4>; /* als 173 spi-rx-bus-width = <4>; /* also DUAL configuration possible */
182 spi-max-frequency = <108000000 174 spi-max-frequency = <108000000>; /* Based on DC1 spec */
183 }; 175 };
184 }; 176 };
185 177
186 &rtc { 178 &rtc {
187 status = "okay"; 179 status = "okay";
188 }; 180 };
189 181
190 &uart0 { 182 &uart0 {
191 status = "okay"; 183 status = "okay";
192 }; 184 };
193 185
194 &uart1 { 186 &uart1 {
195 status = "okay"; 187 status = "okay";
196 }; 188 };
197 189
198 &watchdog0 { 190 &watchdog0 {
199 status = "okay"; 191 status = "okay";
200 }; 192 };
201 193
202 &zynqmp_dpdma { 194 &zynqmp_dpdma {
203 status = "okay"; 195 status = "okay";
204 }; 196 };
205 197
206 &zynqmp_dpsub { 198 &zynqmp_dpsub {
207 status = "okay"; 199 status = "okay";
208 }; 200 };
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