1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * dts file for Xilinx ZynqMP ZCU102 Rev1.0 3 * dts file for Xilinx ZynqMP ZCU102 Rev1.0
4 * 4 *
5 * (C) Copyright 2016 - 2018, Xilinx, Inc. 5 * (C) Copyright 2016 - 2018, Xilinx, Inc.
6 * 6 *
7 * Michal Simek <michal.simek@amd.com> 7 * Michal Simek <michal.simek@amd.com>
8 */ 8 */
9 9
10 #include "zynqmp-zcu102-revB.dts" 10 #include "zynqmp-zcu102-revB.dts"
11 11
12 / { 12 / {
13 model = "ZynqMP ZCU102 Rev1.0"; 13 model = "ZynqMP ZCU102 Rev1.0";
14 compatible = "xlnx,zynqmp-zcu102-rev1. 14 compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
15 }; 15 };
16 16
17 &rproc_split { <<
18 status = "okay"; <<
19 }; <<
20 <<
21 &rproc_lockstep { <<
22 status = "disabled"; <<
23 }; <<
24 <<
25 &eeprom { 17 &eeprom {
26 #address-cells = <1>; 18 #address-cells = <1>;
27 #size-cells = <1>; 19 #size-cells = <1>;
28 20
29 board_sn: board-sn@0 { 21 board_sn: board-sn@0 {
30 reg = <0x0 0x14>; 22 reg = <0x0 0x14>;
31 }; 23 };
32 24
33 eth_mac: eth-mac@20 { 25 eth_mac: eth-mac@20 {
34 reg = <0x20 0x6>; 26 reg = <0x20 0x6>;
35 }; 27 };
36 28
37 board_name: board-name@d0 { 29 board_name: board-name@d0 {
38 reg = <0xd0 0x6>; 30 reg = <0xd0 0x6>;
39 }; 31 };
40 32
41 board_revision: board-revision@e0 { 33 board_revision: board-revision@e0 {
42 reg = <0xe0 0x3>; 34 reg = <0xe0 0x3>;
43 }; 35 };
44 }; 36 };
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