1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * dts file for Xilinx ZynqMP ZCU102 RevA 3 * dts file for Xilinx ZynqMP ZCU102 RevA
4 * 4 *
5 * (C) Copyright 2015 - 2022, Xilinx, Inc. !! 5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro D <<
7 * 6 *
8 * Michal Simek <michal.simek@amd.com> !! 7 * Michal Simek <michal.simek@xilinx.com>
9 */ 8 */
10 9
11 /dts-v1/; 10 /dts-v1/;
12 11
13 #include "zynqmp.dtsi" 12 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi" !! 13 #include "zynqmp-clk.dtsi"
15 #include <dt-bindings/input/input.h> 14 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h <<
18 #include <dt-bindings/phy/phy.h> <<
19 16
20 / { 17 / {
21 model = "ZynqMP ZCU102 RevA"; 18 model = "ZynqMP ZCU102 RevA";
22 compatible = "xlnx,zynqmp-zcu102-revA" 19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
23 20
24 aliases { 21 aliases {
25 ethernet0 = &gem3; 22 ethernet0 = &gem3;
26 i2c0 = &i2c0; 23 i2c0 = &i2c0;
27 i2c1 = &i2c1; 24 i2c1 = &i2c1;
28 mmc0 = &sdhci1; 25 mmc0 = &sdhci1;
29 nvmem0 = &eeprom; <<
30 rtc0 = &rtc; 26 rtc0 = &rtc;
31 serial0 = &uart0; 27 serial0 = &uart0;
32 serial1 = &uart1; 28 serial1 = &uart1;
33 serial2 = &dcc; 29 serial2 = &dcc;
34 spi0 = &qspi; <<
35 usb0 = &usb0; <<
36 }; 30 };
37 31
38 chosen { 32 chosen {
39 bootargs = "earlycon"; 33 bootargs = "earlycon";
40 stdout-path = "serial0:115200n 34 stdout-path = "serial0:115200n8";
41 }; 35 };
42 36
43 memory@0 { 37 memory@0 {
44 device_type = "memory"; 38 device_type = "memory";
45 reg = <0x0 0x0 0x0 0x80000000> 39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46 }; 40 };
47 41
48 gpio-keys { 42 gpio-keys {
49 compatible = "gpio-keys"; 43 compatible = "gpio-keys";
>> 44 #address-cells = <1>;
>> 45 #size-cells = <0>;
50 autorepeat; 46 autorepeat;
51 switch-19 { !! 47 sw19 {
52 label = "sw19"; 48 label = "sw19";
53 gpios = <&gpio 22 GPIO 49 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN 50 linux,code = <KEY_DOWN>;
55 wakeup-source; !! 51 gpio-key,wakeup;
56 autorepeat; 52 autorepeat;
57 }; 53 };
58 }; 54 };
59 55
60 leds { 56 leds {
61 compatible = "gpio-leds"; 57 compatible = "gpio-leds";
62 heartbeat-led { !! 58 heartbeat_led {
63 label = "heartbeat"; 59 label = "heartbeat";
64 gpios = <&gpio 23 GPIO 60 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger 61 linux,default-trigger = "heartbeat";
66 }; 62 };
67 }; 63 };
68 <<
69 ina226-u76 { <<
70 compatible = "iio-hwmon"; <<
71 io-channels = <&u76 0>, <&u76 <<
72 }; <<
73 ina226-u77 { <<
74 compatible = "iio-hwmon"; <<
75 io-channels = <&u77 0>, <&u77 <<
76 }; <<
77 ina226-u78 { <<
78 compatible = "iio-hwmon"; <<
79 io-channels = <&u78 0>, <&u78 <<
80 }; <<
81 ina226-u87 { <<
82 compatible = "iio-hwmon"; <<
83 io-channels = <&u87 0>, <&u87 <<
84 }; <<
85 ina226-u85 { <<
86 compatible = "iio-hwmon"; <<
87 io-channels = <&u85 0>, <&u85 <<
88 }; <<
89 ina226-u86 { <<
90 compatible = "iio-hwmon"; <<
91 io-channels = <&u86 0>, <&u86 <<
92 }; <<
93 ina226-u93 { <<
94 compatible = "iio-hwmon"; <<
95 io-channels = <&u93 0>, <&u93 <<
96 }; <<
97 ina226-u88 { <<
98 compatible = "iio-hwmon"; <<
99 io-channels = <&u88 0>, <&u88 <<
100 }; <<
101 ina226-u15 { <<
102 compatible = "iio-hwmon"; <<
103 io-channels = <&u15 0>, <&u15 <<
104 }; <<
105 ina226-u92 { <<
106 compatible = "iio-hwmon"; <<
107 io-channels = <&u92 0>, <&u92 <<
108 }; <<
109 ina226-u79 { <<
110 compatible = "iio-hwmon"; <<
111 io-channels = <&u79 0>, <&u79 <<
112 }; <<
113 ina226-u81 { <<
114 compatible = "iio-hwmon"; <<
115 io-channels = <&u81 0>, <&u81 <<
116 }; <<
117 ina226-u80 { <<
118 compatible = "iio-hwmon"; <<
119 io-channels = <&u80 0>, <&u80 <<
120 }; <<
121 ina226-u84 { <<
122 compatible = "iio-hwmon"; <<
123 io-channels = <&u84 0>, <&u84 <<
124 }; <<
125 ina226-u16 { <<
126 compatible = "iio-hwmon"; <<
127 io-channels = <&u16 0>, <&u16 <<
128 }; <<
129 ina226-u65 { <<
130 compatible = "iio-hwmon"; <<
131 io-channels = <&u65 0>, <&u65 <<
132 }; <<
133 ina226-u74 { <<
134 compatible = "iio-hwmon"; <<
135 io-channels = <&u74 0>, <&u74 <<
136 }; <<
137 ina226-u75 { <<
138 compatible = "iio-hwmon"; <<
139 io-channels = <&u75 0>, <&u75 <<
140 }; <<
141 <<
142 /* 48MHz reference crystal */ <<
143 ref48: ref48M { <<
144 compatible = "fixed-clock"; <<
145 #clock-cells = <0>; <<
146 clock-frequency = <48000000>; <<
147 }; <<
148 <<
149 refhdmi: refhdmi { <<
150 compatible = "fixed-clock"; <<
151 #clock-cells = <0>; <<
152 clock-frequency = <114285000>; <<
153 }; <<
154 }; 64 };
155 65
156 &can1 { 66 &can1 {
157 status = "okay"; 67 status = "okay";
158 pinctrl-names = "default"; <<
159 pinctrl-0 = <&pinctrl_can1_default>; <<
160 }; 68 };
161 69
162 &dcc { 70 &dcc {
163 status = "okay"; 71 status = "okay";
164 }; 72 };
165 73
166 &fpd_dma_chan1 { 74 &fpd_dma_chan1 {
167 status = "okay"; 75 status = "okay";
168 }; 76 };
169 77
170 &fpd_dma_chan2 { 78 &fpd_dma_chan2 {
171 status = "okay"; 79 status = "okay";
172 }; 80 };
173 81
174 &fpd_dma_chan3 { 82 &fpd_dma_chan3 {
175 status = "okay"; 83 status = "okay";
176 }; 84 };
177 85
178 &fpd_dma_chan4 { 86 &fpd_dma_chan4 {
179 status = "okay"; 87 status = "okay";
180 }; 88 };
181 89
182 &fpd_dma_chan5 { 90 &fpd_dma_chan5 {
183 status = "okay"; 91 status = "okay";
184 }; 92 };
185 93
186 &fpd_dma_chan6 { 94 &fpd_dma_chan6 {
187 status = "okay"; 95 status = "okay";
188 }; 96 };
189 97
190 &fpd_dma_chan7 { 98 &fpd_dma_chan7 {
191 status = "okay"; 99 status = "okay";
192 }; 100 };
193 101
194 &fpd_dma_chan8 { 102 &fpd_dma_chan8 {
195 status = "okay"; 103 status = "okay";
196 }; 104 };
197 105
198 &gem3 { 106 &gem3 {
199 status = "okay"; 107 status = "okay";
200 phy-handle = <&phy0>; 108 phy-handle = <&phy0>;
201 phy-mode = "rgmii-id"; 109 phy-mode = "rgmii-id";
202 pinctrl-names = "default"; !! 110 phy0: phy@21 {
203 pinctrl-0 = <&pinctrl_gem3_default>; !! 111 reg = <21>;
204 mdio: mdio { !! 112 ti,rx-internal-delay = <0x8>;
205 #address-cells = <1>; !! 113 ti,tx-internal-delay = <0xa>;
206 #size-cells = <0>; !! 114 ti,fifo-depth = <0x1>;
207 phy0: ethernet-phy@21 { <<
208 #phy-cells = <1>; <<
209 compatible = "ethernet <<
210 reg = <21>; <<
211 ti,rx-internal-delay = <<
212 ti,tx-internal-delay = <<
213 ti,fifo-depth = <0x1>; <<
214 ti,dp83867-rxctrl-stra <<
215 reset-gpios = <&tca641 <<
216 }; <<
217 }; 115 };
218 }; 116 };
219 117
220 &gpio { 118 &gpio {
221 status = "okay"; 119 status = "okay";
222 pinctrl-names = "default"; <<
223 pinctrl-0 = <&pinctrl_gpio_default>; <<
224 }; <<
225 <<
226 &gpu { <<
227 status = "okay"; <<
228 }; 120 };
229 121
230 &i2c0 { 122 &i2c0 {
231 status = "okay"; 123 status = "okay";
232 clock-frequency = <400000>; 124 clock-frequency = <400000>;
233 pinctrl-names = "default", "gpio"; <<
234 pinctrl-0 = <&pinctrl_i2c0_default>; <<
235 pinctrl-1 = <&pinctrl_i2c0_gpio>; <<
236 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIG <<
237 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIG <<
238 125
239 tca6416_u97: gpio@20 { 126 tca6416_u97: gpio@20 {
240 compatible = "ti,tca6416"; 127 compatible = "ti,tca6416";
241 reg = <0x20>; 128 reg = <0x20>;
242 gpio-controller; /* IRQ not co !! 129 gpio-controller;
243 #gpio-cells = <2>; 130 #gpio-cells = <2>;
244 gpio-line-names = "PS_GTR_LAN_ !! 131 /*
245 "PCI_CLK_DIR_S !! 132 * IRQ not connected
246 "", "", "", "" !! 133 * Lines:
247 gtr-sel0-hog { !! 134 * 0 - PS_GTR_LAN_SEL0
>> 135 * 1 - PS_GTR_LAN_SEL1
>> 136 * 2 - PS_GTR_LAN_SEL2
>> 137 * 3 - PS_GTR_LAN_SEL3
>> 138 * 4 - PCI_CLK_DIR_SEL
>> 139 * 5 - IIC_MUX_RESET_B
>> 140 * 6 - GEM3_EXP_RESET_B
>> 141 * 7, 10 - 17 - not connected
>> 142 */
>> 143
>> 144 gtr_sel0 {
248 gpio-hog; 145 gpio-hog;
249 gpios = <0 0>; 146 gpios = <0 0>;
250 output-low; /* PCIE = 147 output-low; /* PCIE = 0, DP = 1 */
251 line-name = "sel0"; 148 line-name = "sel0";
252 }; 149 };
253 gtr-sel1-hog { !! 150 gtr_sel1 {
254 gpio-hog; 151 gpio-hog;
255 gpios = <1 0>; 152 gpios = <1 0>;
256 output-high; /* PCIE = 153 output-high; /* PCIE = 0, DP = 1 */
257 line-name = "sel1"; 154 line-name = "sel1";
258 }; 155 };
259 gtr-sel2-hog { !! 156 gtr_sel2 {
260 gpio-hog; 157 gpio-hog;
261 gpios = <2 0>; 158 gpios = <2 0>;
262 output-high; /* PCIE = 159 output-high; /* PCIE = 0, USB0 = 1 */
263 line-name = "sel2"; 160 line-name = "sel2";
264 }; 161 };
265 gtr-sel3-hog { !! 162 gtr_sel3 {
266 gpio-hog; 163 gpio-hog;
267 gpios = <3 0>; 164 gpios = <3 0>;
268 output-high; /* PCIE = 165 output-high; /* PCIE = 0, SATA = 1 */
269 line-name = "sel3"; 166 line-name = "sel3";
270 }; 167 };
271 }; 168 };
272 169
273 tca6416_u61: gpio@21 { 170 tca6416_u61: gpio@21 {
274 compatible = "ti,tca6416"; 171 compatible = "ti,tca6416";
275 reg = <0x21>; 172 reg = <0x21>;
276 gpio-controller; /* IRQ not co !! 173 gpio-controller;
277 #gpio-cells = <2>; 174 #gpio-cells = <2>;
278 gpio-line-names = "VCCPSPLL_EN !! 175 /*
279 "PL_PMBUS_ALER !! 176 * IRQ not connected
280 "PL_DDR4_VPP_2 !! 177 * Lines:
281 "PS_DDR4_VTERM !! 178 * 0 - VCCPSPLL_EN
>> 179 * 1 - MGTRAVCC_EN
>> 180 * 2 - MGTRAVTT_EN
>> 181 * 3 - VCCPSDDRPLL_EN
>> 182 * 4 - MIO26_PMU_INPUT_LS
>> 183 * 5 - PL_PMBUS_ALERT
>> 184 * 6 - PS_PMBUS_ALERT
>> 185 * 7 - MAXIM_PMBUS_ALERT
>> 186 * 10 - PL_DDR4_VTERM_EN
>> 187 * 11 - PL_DDR4_VPP_2V5_EN
>> 188 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
>> 189 * 13 - PS_DIMM_SUSPEND_EN
>> 190 * 14 - PS_DDR4_VTERM_EN
>> 191 * 15 - PS_DDR4_VPP_2V5_EN
>> 192 * 16 - 17 - not connected
>> 193 */
282 }; 194 };
283 195
284 i2c-mux@75 { /* u60 */ 196 i2c-mux@75 { /* u60 */
285 compatible = "nxp,pca9544"; 197 compatible = "nxp,pca9544";
286 #address-cells = <1>; 198 #address-cells = <1>;
287 #size-cells = <0>; 199 #size-cells = <0>;
288 reg = <0x75>; 200 reg = <0x75>;
289 i2c@0 { 201 i2c@0 {
290 #address-cells = <1>; 202 #address-cells = <1>;
291 #size-cells = <0>; 203 #size-cells = <0>;
292 reg = <0>; 204 reg = <0>;
293 /* PS_PMBUS */ 205 /* PS_PMBUS */
294 u76: ina226@40 { /* u7 !! 206 ina226@40 { /* u76 */
295 compatible = " 207 compatible = "ti,ina226";
296 #io-channel-ce <<
297 label = "ina22 <<
298 reg = <0x40>; 208 reg = <0x40>;
299 shunt-resistor 209 shunt-resistor = <5000>;
300 }; 210 };
301 u77: ina226@41 { /* u7 !! 211 ina226@41 { /* u77 */
302 compatible = " 212 compatible = "ti,ina226";
303 #io-channel-ce <<
304 label = "ina22 <<
305 reg = <0x41>; 213 reg = <0x41>;
306 shunt-resistor 214 shunt-resistor = <5000>;
307 }; 215 };
308 u78: ina226@42 { /* u7 !! 216 ina226@42 { /* u78 */
309 compatible = " 217 compatible = "ti,ina226";
310 #io-channel-ce <<
311 label = "ina22 <<
312 reg = <0x42>; 218 reg = <0x42>;
313 shunt-resistor 219 shunt-resistor = <5000>;
314 }; 220 };
315 u87: ina226@43 { /* u8 !! 221 ina226@43 { /* u87 */
316 compatible = " 222 compatible = "ti,ina226";
317 #io-channel-ce <<
318 label = "ina22 <<
319 reg = <0x43>; 223 reg = <0x43>;
320 shunt-resistor 224 shunt-resistor = <5000>;
321 }; 225 };
322 u85: ina226@44 { /* u8 !! 226 ina226@44 { /* u85 */
323 compatible = " 227 compatible = "ti,ina226";
324 #io-channel-ce <<
325 label = "ina22 <<
326 reg = <0x44>; 228 reg = <0x44>;
327 shunt-resistor 229 shunt-resistor = <5000>;
328 }; 230 };
329 u86: ina226@45 { /* u8 !! 231 ina226@45 { /* u86 */
330 compatible = " 232 compatible = "ti,ina226";
331 #io-channel-ce <<
332 label = "ina22 <<
333 reg = <0x45>; 233 reg = <0x45>;
334 shunt-resistor 234 shunt-resistor = <5000>;
335 }; 235 };
336 u93: ina226@46 { /* u9 !! 236 ina226@46 { /* u93 */
337 compatible = " 237 compatible = "ti,ina226";
338 #io-channel-ce <<
339 label = "ina22 <<
340 reg = <0x46>; 238 reg = <0x46>;
341 shunt-resistor 239 shunt-resistor = <5000>;
342 }; 240 };
343 u88: ina226@47 { /* u8 !! 241 ina226@47 { /* u88 */
344 compatible = " 242 compatible = "ti,ina226";
345 #io-channel-ce <<
346 label = "ina22 <<
347 reg = <0x47>; 243 reg = <0x47>;
348 shunt-resistor 244 shunt-resistor = <5000>;
349 }; 245 };
350 u15: ina226@4a { /* u1 !! 246 ina226@4a { /* u15 */
351 compatible = " 247 compatible = "ti,ina226";
352 #io-channel-ce <<
353 label = "ina22 <<
354 reg = <0x4a>; 248 reg = <0x4a>;
355 shunt-resistor 249 shunt-resistor = <5000>;
356 }; 250 };
357 u92: ina226@4b { /* u9 !! 251 ina226@4b { /* u92 */
358 compatible = " 252 compatible = "ti,ina226";
359 #io-channel-ce <<
360 label = "ina22 <<
361 reg = <0x4b>; 253 reg = <0x4b>;
362 shunt-resistor 254 shunt-resistor = <5000>;
363 }; 255 };
364 }; 256 };
365 i2c@1 { 257 i2c@1 {
366 #address-cells = <1>; 258 #address-cells = <1>;
367 #size-cells = <0>; 259 #size-cells = <0>;
368 reg = <1>; 260 reg = <1>;
369 /* PL_PMBUS */ 261 /* PL_PMBUS */
370 u79: ina226@40 { /* u7 !! 262 ina226@40 { /* u79 */
371 compatible = " 263 compatible = "ti,ina226";
372 #io-channel-ce <<
373 label = "ina22 <<
374 reg = <0x40>; 264 reg = <0x40>;
375 shunt-resistor 265 shunt-resistor = <2000>;
376 }; 266 };
377 u81: ina226@41 { /* u8 !! 267 ina226@41 { /* u81 */
378 compatible = " 268 compatible = "ti,ina226";
379 #io-channel-ce <<
380 label = "ina22 <<
381 reg = <0x41>; 269 reg = <0x41>;
382 shunt-resistor 270 shunt-resistor = <5000>;
383 }; 271 };
384 u80: ina226@42 { /* u8 !! 272 ina226@42 { /* u80 */
385 compatible = " 273 compatible = "ti,ina226";
386 #io-channel-ce <<
387 label = "ina22 <<
388 reg = <0x42>; 274 reg = <0x42>;
389 shunt-resistor 275 shunt-resistor = <5000>;
390 }; 276 };
391 u84: ina226@43 { /* u8 !! 277 ina226@43 { /* u84 */
392 compatible = " 278 compatible = "ti,ina226";
393 #io-channel-ce <<
394 label = "ina22 <<
395 reg = <0x43>; 279 reg = <0x43>;
396 shunt-resistor 280 shunt-resistor = <5000>;
397 }; 281 };
398 u16: ina226@44 { /* u1 !! 282 ina226@44 { /* u16 */
399 compatible = " 283 compatible = "ti,ina226";
400 #io-channel-ce <<
401 label = "ina22 <<
402 reg = <0x44>; 284 reg = <0x44>;
403 shunt-resistor 285 shunt-resistor = <5000>;
404 }; 286 };
405 u65: ina226@45 { /* u6 !! 287 ina226@45 { /* u65 */
406 compatible = " 288 compatible = "ti,ina226";
407 #io-channel-ce <<
408 label = "ina22 <<
409 reg = <0x45>; 289 reg = <0x45>;
410 shunt-resistor 290 shunt-resistor = <5000>;
411 }; 291 };
412 u74: ina226@46 { /* u7 !! 292 ina226@46 { /* u74 */
413 compatible = " 293 compatible = "ti,ina226";
414 #io-channel-ce <<
415 label = "ina22 <<
416 reg = <0x46>; 294 reg = <0x46>;
417 shunt-resistor 295 shunt-resistor = <5000>;
418 }; 296 };
419 u75: ina226@47 { /* u7 !! 297 ina226@47 { /* u75 */
420 compatible = " 298 compatible = "ti,ina226";
421 #io-channel-ce <<
422 label = "ina22 <<
423 reg = <0x47>; 299 reg = <0x47>;
424 shunt-resistor 300 shunt-resistor = <5000>;
425 }; 301 };
426 }; 302 };
427 i2c@2 { 303 i2c@2 {
428 #address-cells = <1>; 304 #address-cells = <1>;
429 #size-cells = <0>; 305 #size-cells = <0>;
430 reg = <2>; 306 reg = <2>;
431 /* MAXIM_PMBUS - 00 */ 307 /* MAXIM_PMBUS - 00 */
432 max15301@a { /* u46 */ 308 max15301@a { /* u46 */
433 compatible = " 309 compatible = "maxim,max15301";
434 reg = <0xa>; 310 reg = <0xa>;
435 }; 311 };
436 max15303@b { /* u4 */ 312 max15303@b { /* u4 */
437 compatible = " 313 compatible = "maxim,max15303";
438 reg = <0xb>; 314 reg = <0xb>;
439 }; 315 };
440 max15303@10 { /* u13 * 316 max15303@10 { /* u13 */
441 compatible = " 317 compatible = "maxim,max15303";
442 reg = <0x10>; 318 reg = <0x10>;
443 }; 319 };
444 max15301@13 { /* u47 * 320 max15301@13 { /* u47 */
445 compatible = " 321 compatible = "maxim,max15301";
446 reg = <0x13>; 322 reg = <0x13>;
447 }; 323 };
448 max15303@14 { /* u7 */ 324 max15303@14 { /* u7 */
449 compatible = " 325 compatible = "maxim,max15303";
450 reg = <0x14>; 326 reg = <0x14>;
451 }; 327 };
452 max15303@15 { /* u6 */ 328 max15303@15 { /* u6 */
453 compatible = " 329 compatible = "maxim,max15303";
454 reg = <0x15>; 330 reg = <0x15>;
455 }; 331 };
456 max15303@16 { /* u10 * 332 max15303@16 { /* u10 */
457 compatible = " 333 compatible = "maxim,max15303";
458 reg = <0x16>; 334 reg = <0x16>;
459 }; 335 };
460 max15303@17 { /* u9 */ 336 max15303@17 { /* u9 */
461 compatible = " 337 compatible = "maxim,max15303";
462 reg = <0x17>; 338 reg = <0x17>;
463 }; 339 };
464 max15301@18 { /* u63 * 340 max15301@18 { /* u63 */
465 compatible = " 341 compatible = "maxim,max15301";
466 reg = <0x18>; 342 reg = <0x18>;
467 }; 343 };
468 max15303@1a { /* u49 * 344 max15303@1a { /* u49 */
469 compatible = " 345 compatible = "maxim,max15303";
470 reg = <0x1a>; 346 reg = <0x1a>;
471 }; 347 };
472 max15303@1d { /* u18 * 348 max15303@1d { /* u18 */
473 compatible = " 349 compatible = "maxim,max15303";
474 reg = <0x1d>; 350 reg = <0x1d>;
475 }; 351 };
476 max15303@20 { /* u8 */ 352 max15303@20 { /* u8 */
477 compatible = " 353 compatible = "maxim,max15303";
478 status = "disa 354 status = "disabled"; /* unreachable */
479 reg = <0x20>; 355 reg = <0x20>;
480 }; 356 };
>> 357
481 max20751@72 { /* u95 * 358 max20751@72 { /* u95 */
482 compatible = " 359 compatible = "maxim,max20751";
483 reg = <0x72>; 360 reg = <0x72>;
484 }; 361 };
485 max20751@73 { /* u96 * 362 max20751@73 { /* u96 */
486 compatible = " 363 compatible = "maxim,max20751";
487 reg = <0x73>; 364 reg = <0x73>;
488 }; 365 };
489 }; 366 };
490 /* Bus 3 is not connected */ 367 /* Bus 3 is not connected */
491 }; 368 };
492 }; 369 };
493 370
494 &i2c1 { 371 &i2c1 {
495 status = "okay"; 372 status = "okay";
496 clock-frequency = <400000>; 373 clock-frequency = <400000>;
497 pinctrl-names = "default", "gpio"; <<
498 pinctrl-0 = <&pinctrl_i2c1_default>; <<
499 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
500 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIG <<
501 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIG <<
502 374
503 /* PL i2c via PCA9306 - u45 */ 375 /* PL i2c via PCA9306 - u45 */
504 i2c-mux@74 { /* u34 */ 376 i2c-mux@74 { /* u34 */
505 compatible = "nxp,pca9548"; 377 compatible = "nxp,pca9548";
506 #address-cells = <1>; 378 #address-cells = <1>;
507 #size-cells = <0>; 379 #size-cells = <0>;
508 reg = <0x74>; 380 reg = <0x74>;
509 i2c@0 { 381 i2c@0 {
510 #address-cells = <1>; 382 #address-cells = <1>;
511 #size-cells = <0>; 383 #size-cells = <0>;
512 reg = <0>; 384 reg = <0>;
513 /* 385 /*
514 * IIC_EEPROM 1kB memo 386 * IIC_EEPROM 1kB memory which uses 256B blocks
515 * where every block h 387 * where every block has different address.
516 * 0 - 256B address 388 * 0 - 256B address 0x54
517 * 256B - 512B address 389 * 256B - 512B address 0x55
518 * 512B - 768B address 390 * 512B - 768B address 0x56
519 * 768B - 1024B addres 391 * 768B - 1024B address 0x57
520 */ 392 */
521 eeprom: eeprom@54 { /* 393 eeprom: eeprom@54 { /* u23 */
522 compatible = " 394 compatible = "atmel,24c08";
523 reg = <0x54>; 395 reg = <0x54>;
524 }; 396 };
525 }; 397 };
526 i2c@1 { 398 i2c@1 {
527 #address-cells = <1>; 399 #address-cells = <1>;
528 #size-cells = <0>; 400 #size-cells = <0>;
529 reg = <1>; 401 reg = <1>;
530 si5341: clock-generato 402 si5341: clock-generator@36 { /* SI5341 - u69 */
531 compatible = " <<
532 reg = <0x36>; 403 reg = <0x36>;
533 #clock-cells = <<
534 #address-cells <<
535 #size-cells = <<
536 clocks = <&ref <<
537 clock-names = <<
538 clock-output-n <<
539 <<
540 si5341_0: out@ <<
541 /* ref <<
542 reg = <<
543 always <<
544 }; <<
545 si5341_2: out@ <<
546 /* ref <<
547 reg = <<
548 always <<
549 }; <<
550 si5341_3: out@ <<
551 /* ref <<
552 reg = <<
553 always <<
554 }; <<
555 si5341_4: out@ <<
556 /* ref <<
557 reg = <<
558 always <<
559 }; <<
560 si5341_5: out@ <<
561 /* ref <<
562 reg = <<
563 always <<
564 }; <<
565 si5341_6: out@ <<
566 /* ref <<
567 reg = <<
568 always <<
569 }; <<
570 si5341_7: out@ <<
571 /* ref <<
572 reg = <<
573 always <<
574 }; <<
575 si5341_9: out@ <<
576 /* ref <<
577 reg = <<
578 always <<
579 }; <<
580 }; 404 };
>> 405
581 }; 406 };
582 i2c@2 { 407 i2c@2 {
583 #address-cells = <1>; 408 #address-cells = <1>;
584 #size-cells = <0>; 409 #size-cells = <0>;
585 reg = <2>; 410 reg = <2>;
586 si570_1: clock-generat 411 si570_1: clock-generator@5d { /* USER SI570 - u42 */
587 #clock-cells = 412 #clock-cells = <0>;
588 compatible = " 413 compatible = "silabs,si570";
589 reg = <0x5d>; 414 reg = <0x5d>;
590 temperature-st 415 temperature-stability = <50>;
591 factory-fout = 416 factory-fout = <300000000>;
592 clock-frequenc 417 clock-frequency = <300000000>;
593 clock-output-n <<
594 }; 418 };
595 }; 419 };
596 i2c@3 { 420 i2c@3 {
597 #address-cells = <1>; 421 #address-cells = <1>;
598 #size-cells = <0>; 422 #size-cells = <0>;
599 reg = <3>; 423 reg = <3>;
600 si570_2: clock-generat 424 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
601 #clock-cells = 425 #clock-cells = <0>;
602 compatible = " 426 compatible = "silabs,si570";
603 reg = <0x5d>; 427 reg = <0x5d>;
604 temperature-st 428 temperature-stability = <50>; /* copy from zc702 */
605 factory-fout = 429 factory-fout = <156250000>;
606 clock-frequenc !! 430 clock-frequency = <148500000>;
607 clock-output-n <<
608 }; 431 };
609 }; 432 };
610 i2c@4 { 433 i2c@4 {
611 #address-cells = <1>; 434 #address-cells = <1>;
612 #size-cells = <0>; 435 #size-cells = <0>;
613 reg = <4>; 436 reg = <4>;
614 /* SI5328 - u20 */ !! 437 si5328: clock-generator@69 {/* SI5328 - u20 */
>> 438 reg = <0x69>;
>> 439 /*
>> 440 * Chip has interrupt present connected to PL
>> 441 * interrupt-parent = <&>;
>> 442 * interrupts = <>;
>> 443 */
>> 444 };
615 }; 445 };
616 /* 5 - 7 unconnected */ 446 /* 5 - 7 unconnected */
617 }; 447 };
618 448
619 i2c-mux@75 { 449 i2c-mux@75 {
620 compatible = "nxp,pca9548"; /* 450 compatible = "nxp,pca9548"; /* u135 */
621 #address-cells = <1>; 451 #address-cells = <1>;
622 #size-cells = <0>; 452 #size-cells = <0>;
623 reg = <0x75>; 453 reg = <0x75>;
624 454
625 i2c@0 { 455 i2c@0 {
626 #address-cells = <1>; 456 #address-cells = <1>;
627 #size-cells = <0>; 457 #size-cells = <0>;
628 reg = <0>; 458 reg = <0>;
629 /* HPC0_IIC */ 459 /* HPC0_IIC */
630 }; 460 };
631 i2c@1 { 461 i2c@1 {
632 #address-cells = <1>; 462 #address-cells = <1>;
633 #size-cells = <0>; 463 #size-cells = <0>;
634 reg = <1>; 464 reg = <1>;
635 /* HPC1_IIC */ 465 /* HPC1_IIC */
636 }; 466 };
637 i2c@2 { 467 i2c@2 {
638 #address-cells = <1>; 468 #address-cells = <1>;
639 #size-cells = <0>; 469 #size-cells = <0>;
640 reg = <2>; 470 reg = <2>;
641 /* SYSMON */ 471 /* SYSMON */
642 }; 472 };
643 i2c@3 { 473 i2c@3 {
644 #address-cells = <1>; 474 #address-cells = <1>;
645 #size-cells = <0>; 475 #size-cells = <0>;
646 reg = <3>; 476 reg = <3>;
647 /* DDR4 SODIMM */ 477 /* DDR4 SODIMM */
648 }; 478 };
649 i2c@4 { 479 i2c@4 {
650 #address-cells = <1>; 480 #address-cells = <1>;
651 #size-cells = <0>; 481 #size-cells = <0>;
652 reg = <4>; 482 reg = <4>;
653 /* SEP 3 */ 483 /* SEP 3 */
654 }; 484 };
655 i2c@5 { 485 i2c@5 {
656 #address-cells = <1>; 486 #address-cells = <1>;
657 #size-cells = <0>; 487 #size-cells = <0>;
658 reg = <5>; 488 reg = <5>;
659 /* SEP 2 */ 489 /* SEP 2 */
660 }; 490 };
661 i2c@6 { 491 i2c@6 {
662 #address-cells = <1>; 492 #address-cells = <1>;
663 #size-cells = <0>; 493 #size-cells = <0>;
664 reg = <6>; 494 reg = <6>;
665 /* SEP 1 */ 495 /* SEP 1 */
666 }; 496 };
667 i2c@7 { 497 i2c@7 {
668 #address-cells = <1>; 498 #address-cells = <1>;
669 #size-cells = <0>; 499 #size-cells = <0>;
670 reg = <7>; 500 reg = <7>;
671 /* SEP 0 */ 501 /* SEP 0 */
672 }; 502 };
673 }; 503 };
674 }; 504 };
675 505
676 &pinctrl0 { <<
677 status = "okay"; <<
678 pinctrl_i2c0_default: i2c0-default { <<
679 mux { <<
680 groups = "i2c0_3_grp"; <<
681 function = "i2c0"; <<
682 }; <<
683 <<
684 conf { <<
685 groups = "i2c0_3_grp"; <<
686 bias-pull-up; <<
687 slew-rate = <SLEW_RATE <<
688 power-source = <IO_STA <<
689 }; <<
690 }; <<
691 <<
692 pinctrl_i2c0_gpio: i2c0-gpio-grp { <<
693 mux { <<
694 groups = "gpio0_14_grp <<
695 function = "gpio0"; <<
696 }; <<
697 <<
698 conf { <<
699 groups = "gpio0_14_grp <<
700 slew-rate = <SLEW_RATE <<
701 power-source = <IO_STA <<
702 }; <<
703 }; <<
704 <<
705 pinctrl_i2c1_default: i2c1-default { <<
706 mux { <<
707 groups = "i2c1_4_grp"; <<
708 function = "i2c1"; <<
709 }; <<
710 <<
711 conf { <<
712 groups = "i2c1_4_grp"; <<
713 bias-pull-up; <<
714 slew-rate = <SLEW_RATE <<
715 power-source = <IO_STA <<
716 }; <<
717 }; <<
718 <<
719 pinctrl_i2c1_gpio: i2c1-gpio-grp { <<
720 mux { <<
721 groups = "gpio0_16_grp <<
722 function = "gpio0"; <<
723 }; <<
724 <<
725 conf { <<
726 groups = "gpio0_16_grp <<
727 slew-rate = <SLEW_RATE <<
728 power-source = <IO_STA <<
729 }; <<
730 }; <<
731 <<
732 pinctrl_uart0_default: uart0-default { <<
733 mux { <<
734 groups = "uart0_4_grp" <<
735 function = "uart0"; <<
736 }; <<
737 <<
738 conf { <<
739 groups = "uart0_4_grp" <<
740 slew-rate = <SLEW_RATE <<
741 power-source = <IO_STA <<
742 }; <<
743 <<
744 conf-rx { <<
745 pins = "MIO18"; <<
746 bias-high-impedance; <<
747 }; <<
748 <<
749 conf-tx { <<
750 pins = "MIO19"; <<
751 bias-disable; <<
752 }; <<
753 }; <<
754 <<
755 pinctrl_uart1_default: uart1-default { <<
756 mux { <<
757 groups = "uart1_5_grp" <<
758 function = "uart1"; <<
759 }; <<
760 <<
761 conf { <<
762 groups = "uart1_5_grp" <<
763 slew-rate = <SLEW_RATE <<
764 power-source = <IO_STA <<
765 }; <<
766 <<
767 conf-rx { <<
768 pins = "MIO21"; <<
769 bias-high-impedance; <<
770 }; <<
771 <<
772 conf-tx { <<
773 pins = "MIO20"; <<
774 bias-disable; <<
775 }; <<
776 }; <<
777 <<
778 pinctrl_usb0_default: usb0-default { <<
779 mux { <<
780 groups = "usb0_0_grp"; <<
781 function = "usb0"; <<
782 }; <<
783 <<
784 conf { <<
785 groups = "usb0_0_grp"; <<
786 power-source = <IO_STA <<
787 }; <<
788 <<
789 conf-rx { <<
790 pins = "MIO52", "MIO53 <<
791 bias-high-impedance; <<
792 drive-strength = <12>; <<
793 slew-rate = <SLEW_RATE <<
794 }; <<
795 <<
796 conf-tx { <<
797 pins = "MIO54", "MIO56 <<
798 "MIO60", "MIO61 <<
799 bias-disable; <<
800 drive-strength = <4>; <<
801 slew-rate = <SLEW_RATE <<
802 }; <<
803 }; <<
804 <<
805 pinctrl_gem3_default: gem3-default { <<
806 mux { <<
807 function = "ethernet3" <<
808 groups = "ethernet3_0_ <<
809 }; <<
810 <<
811 conf { <<
812 groups = "ethernet3_0_ <<
813 slew-rate = <SLEW_RATE <<
814 power-source = <IO_STA <<
815 }; <<
816 <<
817 conf-rx { <<
818 pins = "MIO70", "MIO71 <<
819 <<
820 bias-high-impedance; <<
821 low-power-disable; <<
822 }; <<
823 <<
824 conf-tx { <<
825 pins = "MIO64", "MIO65 <<
826 <<
827 bias-disable; <<
828 low-power-enable; <<
829 }; <<
830 <<
831 mux-mdio { <<
832 function = "mdio3"; <<
833 groups = "mdio3_0_grp" <<
834 }; <<
835 <<
836 conf-mdio { <<
837 groups = "mdio3_0_grp" <<
838 slew-rate = <SLEW_RATE <<
839 power-source = <IO_STA <<
840 bias-disable; <<
841 }; <<
842 }; <<
843 <<
844 pinctrl_can1_default: can1-default { <<
845 mux { <<
846 function = "can1"; <<
847 groups = "can1_6_grp"; <<
848 }; <<
849 <<
850 conf { <<
851 groups = "can1_6_grp"; <<
852 slew-rate = <SLEW_RATE <<
853 power-source = <IO_STA <<
854 }; <<
855 <<
856 conf-rx { <<
857 pins = "MIO25"; <<
858 bias-high-impedance; <<
859 }; <<
860 <<
861 conf-tx { <<
862 pins = "MIO24"; <<
863 bias-disable; <<
864 }; <<
865 }; <<
866 <<
867 pinctrl_sdhci1_default: sdhci1-default <<
868 mux { <<
869 groups = "sdio1_0_grp" <<
870 function = "sdio1"; <<
871 }; <<
872 <<
873 conf { <<
874 groups = "sdio1_0_grp" <<
875 slew-rate = <SLEW_RATE <<
876 power-source = <IO_STA <<
877 bias-disable; <<
878 }; <<
879 <<
880 mux-cd { <<
881 groups = "sdio1_cd_0_g <<
882 function = "sdio1_cd"; <<
883 }; <<
884 <<
885 conf-cd { <<
886 groups = "sdio1_cd_0_g <<
887 bias-high-impedance; <<
888 bias-pull-up; <<
889 slew-rate = <SLEW_RATE <<
890 power-source = <IO_STA <<
891 }; <<
892 <<
893 mux-wp { <<
894 groups = "sdio1_wp_0_g <<
895 function = "sdio1_wp"; <<
896 }; <<
897 <<
898 conf-wp { <<
899 groups = "sdio1_wp_0_g <<
900 bias-high-impedance; <<
901 bias-pull-up; <<
902 slew-rate = <SLEW_RATE <<
903 power-source = <IO_STA <<
904 }; <<
905 }; <<
906 <<
907 pinctrl_gpio_default: gpio-default { <<
908 mux-sw { <<
909 function = "gpio0"; <<
910 groups = "gpio0_22_grp <<
911 }; <<
912 <<
913 conf-sw { <<
914 groups = "gpio0_22_grp <<
915 slew-rate = <SLEW_RATE <<
916 power-source = <IO_STA <<
917 }; <<
918 <<
919 mux-msp { <<
920 function = "gpio0"; <<
921 groups = "gpio0_13_grp <<
922 }; <<
923 <<
924 conf-msp { <<
925 groups = "gpio0_13_grp <<
926 slew-rate = <SLEW_RATE <<
927 power-source = <IO_STA <<
928 }; <<
929 <<
930 conf-pull-up { <<
931 pins = "MIO22", "MIO23 <<
932 bias-pull-up; <<
933 }; <<
934 <<
935 conf-pull-none { <<
936 pins = "MIO13", "MIO38 <<
937 bias-disable; <<
938 }; <<
939 }; <<
940 }; <<
941 <<
942 &pcie { 506 &pcie {
943 status = "okay"; 507 status = "okay";
944 phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; <<
945 }; <<
946 <<
947 &psgtr { <<
948 status = "okay"; <<
949 /* pcie, sata, usb3, dp */ <<
950 clocks = <&si5341 0 5>, <&si5341 0 3>, <<
951 clock-names = "ref0", "ref1", "ref2", <<
952 }; <<
953 <<
954 &qspi { <<
955 status = "okay"; <<
956 flash@0 { <<
957 compatible = "m25p80", "jedec, <<
958 #address-cells = <1>; <<
959 #size-cells = <1>; <<
960 reg = <0x0>; <<
961 spi-tx-bus-width = <4>; <<
962 spi-rx-bus-width = <4>; /* FIX <<
963 spi-max-frequency = <108000000 <<
964 }; <<
965 }; 508 };
966 509
967 &rtc { 510 &rtc {
968 status = "okay"; 511 status = "okay";
969 }; 512 };
970 513
971 &sata { 514 &sata {
972 status = "okay"; 515 status = "okay";
973 /* SATA OOB timing settings */ 516 /* SATA OOB timing settings */
974 ceva,p0-cominit-params = /bits/ 8 <0x1 517 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
975 ceva,p0-comwake-params = /bits/ 8 <0x0 518 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
976 ceva,p0-burst-params = /bits/ 8 <0x13 519 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
977 ceva,p0-retry-params = /bits/ 16 <0x96 520 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
978 ceva,p1-cominit-params = /bits/ 8 <0x1 521 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
979 ceva,p1-comwake-params = /bits/ 8 <0x0 522 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
980 ceva,p1-burst-params = /bits/ 8 <0x13 523 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
981 ceva,p1-retry-params = /bits/ 16 <0x96 524 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
982 phy-names = "sata-phy"; <<
983 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; <<
984 }; 525 };
985 526
986 /* SD1 with level shifter */ 527 /* SD1 with level shifter */
987 &sdhci1 { 528 &sdhci1 {
988 status = "okay"; 529 status = "okay";
989 /* <<
990 * 1.0 revision has level shifter and <<
991 * removed for supporting UHS mode <<
992 */ <<
993 no-1-8-v; 530 no-1-8-v;
994 pinctrl-names = "default"; <<
995 pinctrl-0 = <&pinctrl_sdhci1_default>; <<
996 xlnx,mio-bank = <1>; <<
997 }; 531 };
998 532
999 &uart0 { 533 &uart0 {
1000 status = "okay"; 534 status = "okay";
1001 pinctrl-names = "default"; <<
1002 pinctrl-0 = <&pinctrl_uart0_default>; <<
1003 }; 535 };
1004 536
1005 &uart1 { 537 &uart1 {
1006 status = "okay"; 538 status = "okay";
1007 pinctrl-names = "default"; <<
1008 pinctrl-0 = <&pinctrl_uart1_default>; <<
1009 }; 539 };
1010 540
1011 /* ULPI SMSC USB3320 */ 541 /* ULPI SMSC USB3320 */
1012 &usb0 { 542 &usb0 {
1013 status = "okay"; 543 status = "okay";
1014 pinctrl-names = "default"; <<
1015 pinctrl-0 = <&pinctrl_usb0_default>; <<
1016 phy-names = "usb3-phy"; <<
1017 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; <<
1018 }; <<
1019 <<
1020 &dwc3_0 { <<
1021 status = "okay"; <<
1022 dr_mode = "host"; <<
1023 snps,usb3_lpm_capable; <<
1024 maximum-speed = "super-speed"; <<
1025 }; 544 };
1026 545
1027 &watchdog0 { 546 &watchdog0 {
1028 status = "okay"; 547 status = "okay";
1029 }; <<
1030 <<
1031 &xilinx_ams { <<
1032 status = "okay"; <<
1033 }; <<
1034 <<
1035 &ams_ps { <<
1036 status = "okay"; <<
1037 }; <<
1038 <<
1039 &ams_pl { <<
1040 status = "okay"; <<
1041 }; <<
1042 <<
1043 &zynqmp_dpdma { <<
1044 status = "okay"; <<
1045 }; <<
1046 <<
1047 &zynqmp_dpsub { <<
1048 status = "okay"; <<
1049 phy-names = "dp-phy0"; <<
1050 phys = <&psgtr 1 PHY_TYPE_DP 0 3>; <<
1051 }; 548 };
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