1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * dts file for Xilinx ZynqMP ZCU102 RevA 3 * dts file for Xilinx ZynqMP ZCU102 RevA
4 * 4 *
5 * (C) Copyright 2015 - 2022, Xilinx, Inc. !! 5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro D <<
7 * 6 *
8 * Michal Simek <michal.simek@amd.com> !! 7 * Michal Simek <michal.simek@xilinx.com>
9 */ 8 */
10 9
11 /dts-v1/; 10 /dts-v1/;
12 11
13 #include "zynqmp.dtsi" 12 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi" 13 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h> 14 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h <<
18 #include <dt-bindings/phy/phy.h> 16 #include <dt-bindings/phy/phy.h>
19 17
20 / { 18 / {
21 model = "ZynqMP ZCU102 RevA"; 19 model = "ZynqMP ZCU102 RevA";
22 compatible = "xlnx,zynqmp-zcu102-revA" 20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
23 21
24 aliases { 22 aliases {
25 ethernet0 = &gem3; 23 ethernet0 = &gem3;
26 i2c0 = &i2c0; 24 i2c0 = &i2c0;
27 i2c1 = &i2c1; 25 i2c1 = &i2c1;
28 mmc0 = &sdhci1; 26 mmc0 = &sdhci1;
29 nvmem0 = &eeprom; <<
30 rtc0 = &rtc; 27 rtc0 = &rtc;
31 serial0 = &uart0; 28 serial0 = &uart0;
32 serial1 = &uart1; 29 serial1 = &uart1;
33 serial2 = &dcc; 30 serial2 = &dcc;
34 spi0 = &qspi; <<
35 usb0 = &usb0; <<
36 }; 31 };
37 32
38 chosen { 33 chosen {
39 bootargs = "earlycon"; 34 bootargs = "earlycon";
40 stdout-path = "serial0:115200n 35 stdout-path = "serial0:115200n8";
41 }; 36 };
42 37
43 memory@0 { 38 memory@0 {
44 device_type = "memory"; 39 device_type = "memory";
45 reg = <0x0 0x0 0x0 0x80000000> 40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46 }; 41 };
47 42
48 gpio-keys { 43 gpio-keys {
49 compatible = "gpio-keys"; 44 compatible = "gpio-keys";
50 autorepeat; 45 autorepeat;
51 switch-19 { !! 46 sw19 {
52 label = "sw19"; 47 label = "sw19";
53 gpios = <&gpio 22 GPIO 48 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN 49 linux,code = <KEY_DOWN>;
55 wakeup-source; 50 wakeup-source;
56 autorepeat; 51 autorepeat;
57 }; 52 };
58 }; 53 };
59 54
60 leds { 55 leds {
61 compatible = "gpio-leds"; 56 compatible = "gpio-leds";
62 heartbeat-led { 57 heartbeat-led {
63 label = "heartbeat"; 58 label = "heartbeat";
64 gpios = <&gpio 23 GPIO 59 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger 60 linux,default-trigger = "heartbeat";
66 }; 61 };
67 }; 62 };
68 63
69 ina226-u76 { 64 ina226-u76 {
70 compatible = "iio-hwmon"; 65 compatible = "iio-hwmon";
71 io-channels = <&u76 0>, <&u76 66 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
72 }; 67 };
73 ina226-u77 { 68 ina226-u77 {
74 compatible = "iio-hwmon"; 69 compatible = "iio-hwmon";
75 io-channels = <&u77 0>, <&u77 70 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
76 }; 71 };
77 ina226-u78 { 72 ina226-u78 {
78 compatible = "iio-hwmon"; 73 compatible = "iio-hwmon";
79 io-channels = <&u78 0>, <&u78 74 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
80 }; 75 };
81 ina226-u87 { 76 ina226-u87 {
82 compatible = "iio-hwmon"; 77 compatible = "iio-hwmon";
83 io-channels = <&u87 0>, <&u87 78 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
84 }; 79 };
85 ina226-u85 { 80 ina226-u85 {
86 compatible = "iio-hwmon"; 81 compatible = "iio-hwmon";
87 io-channels = <&u85 0>, <&u85 82 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
88 }; 83 };
89 ina226-u86 { 84 ina226-u86 {
90 compatible = "iio-hwmon"; 85 compatible = "iio-hwmon";
91 io-channels = <&u86 0>, <&u86 86 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
92 }; 87 };
93 ina226-u93 { 88 ina226-u93 {
94 compatible = "iio-hwmon"; 89 compatible = "iio-hwmon";
95 io-channels = <&u93 0>, <&u93 90 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
96 }; 91 };
97 ina226-u88 { 92 ina226-u88 {
98 compatible = "iio-hwmon"; 93 compatible = "iio-hwmon";
99 io-channels = <&u88 0>, <&u88 94 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
100 }; 95 };
101 ina226-u15 { 96 ina226-u15 {
102 compatible = "iio-hwmon"; 97 compatible = "iio-hwmon";
103 io-channels = <&u15 0>, <&u15 98 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
104 }; 99 };
105 ina226-u92 { 100 ina226-u92 {
106 compatible = "iio-hwmon"; 101 compatible = "iio-hwmon";
107 io-channels = <&u92 0>, <&u92 102 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
108 }; 103 };
109 ina226-u79 { 104 ina226-u79 {
110 compatible = "iio-hwmon"; 105 compatible = "iio-hwmon";
111 io-channels = <&u79 0>, <&u79 106 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
112 }; 107 };
113 ina226-u81 { 108 ina226-u81 {
114 compatible = "iio-hwmon"; 109 compatible = "iio-hwmon";
115 io-channels = <&u81 0>, <&u81 110 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
116 }; 111 };
117 ina226-u80 { 112 ina226-u80 {
118 compatible = "iio-hwmon"; 113 compatible = "iio-hwmon";
119 io-channels = <&u80 0>, <&u80 114 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
120 }; 115 };
121 ina226-u84 { 116 ina226-u84 {
122 compatible = "iio-hwmon"; 117 compatible = "iio-hwmon";
123 io-channels = <&u84 0>, <&u84 118 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
124 }; 119 };
125 ina226-u16 { 120 ina226-u16 {
126 compatible = "iio-hwmon"; 121 compatible = "iio-hwmon";
127 io-channels = <&u16 0>, <&u16 122 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
128 }; 123 };
129 ina226-u65 { 124 ina226-u65 {
130 compatible = "iio-hwmon"; 125 compatible = "iio-hwmon";
131 io-channels = <&u65 0>, <&u65 126 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
132 }; 127 };
133 ina226-u74 { 128 ina226-u74 {
134 compatible = "iio-hwmon"; 129 compatible = "iio-hwmon";
135 io-channels = <&u74 0>, <&u74 130 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
136 }; 131 };
137 ina226-u75 { 132 ina226-u75 {
138 compatible = "iio-hwmon"; 133 compatible = "iio-hwmon";
139 io-channels = <&u75 0>, <&u75 134 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
140 }; 135 };
141 136
142 /* 48MHz reference crystal */ 137 /* 48MHz reference crystal */
143 ref48: ref48M { 138 ref48: ref48M {
144 compatible = "fixed-clock"; 139 compatible = "fixed-clock";
145 #clock-cells = <0>; 140 #clock-cells = <0>;
146 clock-frequency = <48000000>; 141 clock-frequency = <48000000>;
147 }; 142 };
148 143
149 refhdmi: refhdmi { 144 refhdmi: refhdmi {
150 compatible = "fixed-clock"; 145 compatible = "fixed-clock";
151 #clock-cells = <0>; 146 #clock-cells = <0>;
152 clock-frequency = <114285000>; 147 clock-frequency = <114285000>;
153 }; 148 };
154 }; 149 };
155 150
156 &can1 { 151 &can1 {
157 status = "okay"; 152 status = "okay";
158 pinctrl-names = "default"; <<
159 pinctrl-0 = <&pinctrl_can1_default>; <<
160 }; 153 };
161 154
162 &dcc { 155 &dcc {
163 status = "okay"; 156 status = "okay";
164 }; 157 };
165 158
166 &fpd_dma_chan1 { 159 &fpd_dma_chan1 {
167 status = "okay"; 160 status = "okay";
168 }; 161 };
169 162
170 &fpd_dma_chan2 { 163 &fpd_dma_chan2 {
171 status = "okay"; 164 status = "okay";
172 }; 165 };
173 166
174 &fpd_dma_chan3 { 167 &fpd_dma_chan3 {
175 status = "okay"; 168 status = "okay";
176 }; 169 };
177 170
178 &fpd_dma_chan4 { 171 &fpd_dma_chan4 {
179 status = "okay"; 172 status = "okay";
180 }; 173 };
181 174
182 &fpd_dma_chan5 { 175 &fpd_dma_chan5 {
183 status = "okay"; 176 status = "okay";
184 }; 177 };
185 178
186 &fpd_dma_chan6 { 179 &fpd_dma_chan6 {
187 status = "okay"; 180 status = "okay";
188 }; 181 };
189 182
190 &fpd_dma_chan7 { 183 &fpd_dma_chan7 {
191 status = "okay"; 184 status = "okay";
192 }; 185 };
193 186
194 &fpd_dma_chan8 { 187 &fpd_dma_chan8 {
195 status = "okay"; 188 status = "okay";
196 }; 189 };
197 190
198 &gem3 { 191 &gem3 {
199 status = "okay"; 192 status = "okay";
200 phy-handle = <&phy0>; 193 phy-handle = <&phy0>;
201 phy-mode = "rgmii-id"; 194 phy-mode = "rgmii-id";
202 pinctrl-names = "default"; !! 195 phy0: ethernet-phy@21 {
203 pinctrl-0 = <&pinctrl_gem3_default>; !! 196 reg = <21>;
204 mdio: mdio { !! 197 ti,rx-internal-delay = <0x8>;
205 #address-cells = <1>; !! 198 ti,tx-internal-delay = <0xa>;
206 #size-cells = <0>; !! 199 ti,fifo-depth = <0x1>;
207 phy0: ethernet-phy@21 { !! 200 ti,dp83867-rxctrl-strap-quirk;
208 #phy-cells = <1>; <<
209 compatible = "ethernet <<
210 reg = <21>; <<
211 ti,rx-internal-delay = <<
212 ti,tx-internal-delay = <<
213 ti,fifo-depth = <0x1>; <<
214 ti,dp83867-rxctrl-stra <<
215 reset-gpios = <&tca641 <<
216 }; <<
217 }; 201 };
218 }; 202 };
219 203
220 &gpio { 204 &gpio {
221 status = "okay"; 205 status = "okay";
222 pinctrl-names = "default"; <<
223 pinctrl-0 = <&pinctrl_gpio_default>; <<
224 }; <<
225 <<
226 &gpu { <<
227 status = "okay"; <<
228 }; 206 };
229 207
230 &i2c0 { 208 &i2c0 {
231 status = "okay"; 209 status = "okay";
232 clock-frequency = <400000>; 210 clock-frequency = <400000>;
233 pinctrl-names = "default", "gpio"; <<
234 pinctrl-0 = <&pinctrl_i2c0_default>; <<
235 pinctrl-1 = <&pinctrl_i2c0_gpio>; <<
236 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIG <<
237 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIG <<
238 211
239 tca6416_u97: gpio@20 { 212 tca6416_u97: gpio@20 {
240 compatible = "ti,tca6416"; 213 compatible = "ti,tca6416";
241 reg = <0x20>; 214 reg = <0x20>;
242 gpio-controller; /* IRQ not co 215 gpio-controller; /* IRQ not connected */
243 #gpio-cells = <2>; 216 #gpio-cells = <2>;
244 gpio-line-names = "PS_GTR_LAN_ 217 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
245 "PCI_CLK_DIR_S 218 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
246 "", "", "", "" 219 "", "", "", "", "", "", "", "", "";
247 gtr-sel0-hog { 220 gtr-sel0-hog {
248 gpio-hog; 221 gpio-hog;
249 gpios = <0 0>; 222 gpios = <0 0>;
250 output-low; /* PCIE = 223 output-low; /* PCIE = 0, DP = 1 */
251 line-name = "sel0"; 224 line-name = "sel0";
252 }; 225 };
253 gtr-sel1-hog { 226 gtr-sel1-hog {
254 gpio-hog; 227 gpio-hog;
255 gpios = <1 0>; 228 gpios = <1 0>;
256 output-high; /* PCIE = 229 output-high; /* PCIE = 0, DP = 1 */
257 line-name = "sel1"; 230 line-name = "sel1";
258 }; 231 };
259 gtr-sel2-hog { 232 gtr-sel2-hog {
260 gpio-hog; 233 gpio-hog;
261 gpios = <2 0>; 234 gpios = <2 0>;
262 output-high; /* PCIE = 235 output-high; /* PCIE = 0, USB0 = 1 */
263 line-name = "sel2"; 236 line-name = "sel2";
264 }; 237 };
265 gtr-sel3-hog { 238 gtr-sel3-hog {
266 gpio-hog; 239 gpio-hog;
267 gpios = <3 0>; 240 gpios = <3 0>;
268 output-high; /* PCIE = 241 output-high; /* PCIE = 0, SATA = 1 */
269 line-name = "sel3"; 242 line-name = "sel3";
270 }; 243 };
271 }; 244 };
272 245
273 tca6416_u61: gpio@21 { 246 tca6416_u61: gpio@21 {
274 compatible = "ti,tca6416"; 247 compatible = "ti,tca6416";
275 reg = <0x21>; 248 reg = <0x21>;
276 gpio-controller; /* IRQ not co 249 gpio-controller; /* IRQ not connected */
277 #gpio-cells = <2>; 250 #gpio-cells = <2>;
278 gpio-line-names = "VCCPSPLL_EN 251 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
279 "PL_PMBUS_ALER 252 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
280 "PL_DDR4_VPP_2 253 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
281 "PS_DDR4_VTERM 254 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
282 }; 255 };
283 256
284 i2c-mux@75 { /* u60 */ 257 i2c-mux@75 { /* u60 */
285 compatible = "nxp,pca9544"; 258 compatible = "nxp,pca9544";
286 #address-cells = <1>; 259 #address-cells = <1>;
287 #size-cells = <0>; 260 #size-cells = <0>;
288 reg = <0x75>; 261 reg = <0x75>;
289 i2c@0 { 262 i2c@0 {
290 #address-cells = <1>; 263 #address-cells = <1>;
291 #size-cells = <0>; 264 #size-cells = <0>;
292 reg = <0>; 265 reg = <0>;
293 /* PS_PMBUS */ 266 /* PS_PMBUS */
294 u76: ina226@40 { /* u7 267 u76: ina226@40 { /* u76 */
295 compatible = " 268 compatible = "ti,ina226";
296 #io-channel-ce 269 #io-channel-cells = <1>;
297 label = "ina22 270 label = "ina226-u76";
298 reg = <0x40>; 271 reg = <0x40>;
299 shunt-resistor 272 shunt-resistor = <5000>;
300 }; 273 };
301 u77: ina226@41 { /* u7 274 u77: ina226@41 { /* u77 */
302 compatible = " 275 compatible = "ti,ina226";
303 #io-channel-ce 276 #io-channel-cells = <1>;
304 label = "ina22 277 label = "ina226-u77";
305 reg = <0x41>; 278 reg = <0x41>;
306 shunt-resistor 279 shunt-resistor = <5000>;
307 }; 280 };
308 u78: ina226@42 { /* u7 281 u78: ina226@42 { /* u78 */
309 compatible = " 282 compatible = "ti,ina226";
310 #io-channel-ce 283 #io-channel-cells = <1>;
311 label = "ina22 284 label = "ina226-u78";
312 reg = <0x42>; 285 reg = <0x42>;
313 shunt-resistor 286 shunt-resistor = <5000>;
314 }; 287 };
315 u87: ina226@43 { /* u8 288 u87: ina226@43 { /* u87 */
316 compatible = " 289 compatible = "ti,ina226";
317 #io-channel-ce 290 #io-channel-cells = <1>;
318 label = "ina22 291 label = "ina226-u87";
319 reg = <0x43>; 292 reg = <0x43>;
320 shunt-resistor 293 shunt-resistor = <5000>;
321 }; 294 };
322 u85: ina226@44 { /* u8 295 u85: ina226@44 { /* u85 */
323 compatible = " 296 compatible = "ti,ina226";
324 #io-channel-ce 297 #io-channel-cells = <1>;
325 label = "ina22 298 label = "ina226-u85";
326 reg = <0x44>; 299 reg = <0x44>;
327 shunt-resistor 300 shunt-resistor = <5000>;
328 }; 301 };
329 u86: ina226@45 { /* u8 302 u86: ina226@45 { /* u86 */
330 compatible = " 303 compatible = "ti,ina226";
331 #io-channel-ce 304 #io-channel-cells = <1>;
332 label = "ina22 305 label = "ina226-u86";
333 reg = <0x45>; 306 reg = <0x45>;
334 shunt-resistor 307 shunt-resistor = <5000>;
335 }; 308 };
336 u93: ina226@46 { /* u9 309 u93: ina226@46 { /* u93 */
337 compatible = " 310 compatible = "ti,ina226";
338 #io-channel-ce 311 #io-channel-cells = <1>;
339 label = "ina22 312 label = "ina226-u93";
340 reg = <0x46>; 313 reg = <0x46>;
341 shunt-resistor 314 shunt-resistor = <5000>;
342 }; 315 };
343 u88: ina226@47 { /* u8 316 u88: ina226@47 { /* u88 */
344 compatible = " 317 compatible = "ti,ina226";
345 #io-channel-ce 318 #io-channel-cells = <1>;
346 label = "ina22 319 label = "ina226-u88";
347 reg = <0x47>; 320 reg = <0x47>;
348 shunt-resistor 321 shunt-resistor = <5000>;
349 }; 322 };
350 u15: ina226@4a { /* u1 323 u15: ina226@4a { /* u15 */
351 compatible = " 324 compatible = "ti,ina226";
352 #io-channel-ce 325 #io-channel-cells = <1>;
353 label = "ina22 326 label = "ina226-u15";
354 reg = <0x4a>; 327 reg = <0x4a>;
355 shunt-resistor 328 shunt-resistor = <5000>;
356 }; 329 };
357 u92: ina226@4b { /* u9 330 u92: ina226@4b { /* u92 */
358 compatible = " 331 compatible = "ti,ina226";
359 #io-channel-ce 332 #io-channel-cells = <1>;
360 label = "ina22 333 label = "ina226-u92";
361 reg = <0x4b>; 334 reg = <0x4b>;
362 shunt-resistor 335 shunt-resistor = <5000>;
363 }; 336 };
364 }; 337 };
365 i2c@1 { 338 i2c@1 {
366 #address-cells = <1>; 339 #address-cells = <1>;
367 #size-cells = <0>; 340 #size-cells = <0>;
368 reg = <1>; 341 reg = <1>;
369 /* PL_PMBUS */ 342 /* PL_PMBUS */
370 u79: ina226@40 { /* u7 343 u79: ina226@40 { /* u79 */
371 compatible = " 344 compatible = "ti,ina226";
372 #io-channel-ce 345 #io-channel-cells = <1>;
373 label = "ina22 346 label = "ina226-u79";
374 reg = <0x40>; 347 reg = <0x40>;
375 shunt-resistor 348 shunt-resistor = <2000>;
376 }; 349 };
377 u81: ina226@41 { /* u8 350 u81: ina226@41 { /* u81 */
378 compatible = " 351 compatible = "ti,ina226";
379 #io-channel-ce 352 #io-channel-cells = <1>;
380 label = "ina22 353 label = "ina226-u81";
381 reg = <0x41>; 354 reg = <0x41>;
382 shunt-resistor 355 shunt-resistor = <5000>;
383 }; 356 };
384 u80: ina226@42 { /* u8 357 u80: ina226@42 { /* u80 */
385 compatible = " 358 compatible = "ti,ina226";
386 #io-channel-ce 359 #io-channel-cells = <1>;
387 label = "ina22 360 label = "ina226-u80";
388 reg = <0x42>; 361 reg = <0x42>;
389 shunt-resistor 362 shunt-resistor = <5000>;
390 }; 363 };
391 u84: ina226@43 { /* u8 364 u84: ina226@43 { /* u84 */
392 compatible = " 365 compatible = "ti,ina226";
393 #io-channel-ce 366 #io-channel-cells = <1>;
394 label = "ina22 367 label = "ina226-u84";
395 reg = <0x43>; 368 reg = <0x43>;
396 shunt-resistor 369 shunt-resistor = <5000>;
397 }; 370 };
398 u16: ina226@44 { /* u1 371 u16: ina226@44 { /* u16 */
399 compatible = " 372 compatible = "ti,ina226";
400 #io-channel-ce 373 #io-channel-cells = <1>;
401 label = "ina22 374 label = "ina226-u16";
402 reg = <0x44>; 375 reg = <0x44>;
403 shunt-resistor 376 shunt-resistor = <5000>;
404 }; 377 };
405 u65: ina226@45 { /* u6 378 u65: ina226@45 { /* u65 */
406 compatible = " 379 compatible = "ti,ina226";
407 #io-channel-ce 380 #io-channel-cells = <1>;
408 label = "ina22 381 label = "ina226-u65";
409 reg = <0x45>; 382 reg = <0x45>;
410 shunt-resistor 383 shunt-resistor = <5000>;
411 }; 384 };
412 u74: ina226@46 { /* u7 385 u74: ina226@46 { /* u74 */
413 compatible = " 386 compatible = "ti,ina226";
414 #io-channel-ce 387 #io-channel-cells = <1>;
415 label = "ina22 388 label = "ina226-u74";
416 reg = <0x46>; 389 reg = <0x46>;
417 shunt-resistor 390 shunt-resistor = <5000>;
418 }; 391 };
419 u75: ina226@47 { /* u7 392 u75: ina226@47 { /* u75 */
420 compatible = " 393 compatible = "ti,ina226";
421 #io-channel-ce 394 #io-channel-cells = <1>;
422 label = "ina22 395 label = "ina226-u75";
423 reg = <0x47>; 396 reg = <0x47>;
424 shunt-resistor 397 shunt-resistor = <5000>;
425 }; 398 };
426 }; 399 };
427 i2c@2 { 400 i2c@2 {
428 #address-cells = <1>; 401 #address-cells = <1>;
429 #size-cells = <0>; 402 #size-cells = <0>;
430 reg = <2>; 403 reg = <2>;
431 /* MAXIM_PMBUS - 00 */ 404 /* MAXIM_PMBUS - 00 */
432 max15301@a { /* u46 */ 405 max15301@a { /* u46 */
433 compatible = " 406 compatible = "maxim,max15301";
434 reg = <0xa>; 407 reg = <0xa>;
435 }; 408 };
436 max15303@b { /* u4 */ 409 max15303@b { /* u4 */
437 compatible = " 410 compatible = "maxim,max15303";
438 reg = <0xb>; 411 reg = <0xb>;
439 }; 412 };
440 max15303@10 { /* u13 * 413 max15303@10 { /* u13 */
441 compatible = " 414 compatible = "maxim,max15303";
442 reg = <0x10>; 415 reg = <0x10>;
443 }; 416 };
444 max15301@13 { /* u47 * 417 max15301@13 { /* u47 */
445 compatible = " 418 compatible = "maxim,max15301";
446 reg = <0x13>; 419 reg = <0x13>;
447 }; 420 };
448 max15303@14 { /* u7 */ 421 max15303@14 { /* u7 */
449 compatible = " 422 compatible = "maxim,max15303";
450 reg = <0x14>; 423 reg = <0x14>;
451 }; 424 };
452 max15303@15 { /* u6 */ 425 max15303@15 { /* u6 */
453 compatible = " 426 compatible = "maxim,max15303";
454 reg = <0x15>; 427 reg = <0x15>;
455 }; 428 };
456 max15303@16 { /* u10 * 429 max15303@16 { /* u10 */
457 compatible = " 430 compatible = "maxim,max15303";
458 reg = <0x16>; 431 reg = <0x16>;
459 }; 432 };
460 max15303@17 { /* u9 */ 433 max15303@17 { /* u9 */
461 compatible = " 434 compatible = "maxim,max15303";
462 reg = <0x17>; 435 reg = <0x17>;
463 }; 436 };
464 max15301@18 { /* u63 * 437 max15301@18 { /* u63 */
465 compatible = " 438 compatible = "maxim,max15301";
466 reg = <0x18>; 439 reg = <0x18>;
467 }; 440 };
468 max15303@1a { /* u49 * 441 max15303@1a { /* u49 */
469 compatible = " 442 compatible = "maxim,max15303";
470 reg = <0x1a>; 443 reg = <0x1a>;
471 }; 444 };
472 max15303@1d { /* u18 * 445 max15303@1d { /* u18 */
473 compatible = " 446 compatible = "maxim,max15303";
474 reg = <0x1d>; 447 reg = <0x1d>;
475 }; 448 };
476 max15303@20 { /* u8 */ 449 max15303@20 { /* u8 */
477 compatible = " 450 compatible = "maxim,max15303";
478 status = "disa 451 status = "disabled"; /* unreachable */
479 reg = <0x20>; 452 reg = <0x20>;
480 }; 453 };
>> 454
481 max20751@72 { /* u95 * 455 max20751@72 { /* u95 */
482 compatible = " 456 compatible = "maxim,max20751";
483 reg = <0x72>; 457 reg = <0x72>;
484 }; 458 };
485 max20751@73 { /* u96 * 459 max20751@73 { /* u96 */
486 compatible = " 460 compatible = "maxim,max20751";
487 reg = <0x73>; 461 reg = <0x73>;
488 }; 462 };
489 }; 463 };
490 /* Bus 3 is not connected */ 464 /* Bus 3 is not connected */
491 }; 465 };
492 }; 466 };
493 467
494 &i2c1 { 468 &i2c1 {
495 status = "okay"; 469 status = "okay";
496 clock-frequency = <400000>; 470 clock-frequency = <400000>;
497 pinctrl-names = "default", "gpio"; <<
498 pinctrl-0 = <&pinctrl_i2c1_default>; <<
499 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
500 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIG <<
501 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIG <<
502 471
503 /* PL i2c via PCA9306 - u45 */ 472 /* PL i2c via PCA9306 - u45 */
504 i2c-mux@74 { /* u34 */ 473 i2c-mux@74 { /* u34 */
505 compatible = "nxp,pca9548"; 474 compatible = "nxp,pca9548";
506 #address-cells = <1>; 475 #address-cells = <1>;
507 #size-cells = <0>; 476 #size-cells = <0>;
508 reg = <0x74>; 477 reg = <0x74>;
509 i2c@0 { 478 i2c@0 {
510 #address-cells = <1>; 479 #address-cells = <1>;
511 #size-cells = <0>; 480 #size-cells = <0>;
512 reg = <0>; 481 reg = <0>;
513 /* 482 /*
514 * IIC_EEPROM 1kB memo 483 * IIC_EEPROM 1kB memory which uses 256B blocks
515 * where every block h 484 * where every block has different address.
516 * 0 - 256B address 485 * 0 - 256B address 0x54
517 * 256B - 512B address 486 * 256B - 512B address 0x55
518 * 512B - 768B address 487 * 512B - 768B address 0x56
519 * 768B - 1024B addres 488 * 768B - 1024B address 0x57
520 */ 489 */
521 eeprom: eeprom@54 { /* 490 eeprom: eeprom@54 { /* u23 */
522 compatible = " 491 compatible = "atmel,24c08";
523 reg = <0x54>; 492 reg = <0x54>;
524 }; 493 };
525 }; 494 };
526 i2c@1 { 495 i2c@1 {
527 #address-cells = <1>; 496 #address-cells = <1>;
528 #size-cells = <0>; 497 #size-cells = <0>;
529 reg = <1>; 498 reg = <1>;
530 si5341: clock-generato 499 si5341: clock-generator@36 { /* SI5341 - u69 */
531 compatible = " 500 compatible = "silabs,si5341";
532 reg = <0x36>; 501 reg = <0x36>;
533 #clock-cells = 502 #clock-cells = <2>;
534 #address-cells 503 #address-cells = <1>;
535 #size-cells = 504 #size-cells = <0>;
536 clocks = <&ref 505 clocks = <&ref48>;
537 clock-names = 506 clock-names = "xtal";
538 clock-output-n 507 clock-output-names = "si5341";
539 508
540 si5341_0: out@ 509 si5341_0: out@0 {
541 /* ref 510 /* refclk0 for PS-GT, used for DP */
542 reg = 511 reg = <0>;
543 always 512 always-on;
544 }; 513 };
545 si5341_2: out@ 514 si5341_2: out@2 {
546 /* ref 515 /* refclk2 for PS-GT, used for USB3 */
547 reg = 516 reg = <2>;
548 always 517 always-on;
549 }; 518 };
550 si5341_3: out@ 519 si5341_3: out@3 {
551 /* ref 520 /* refclk3 for PS-GT, used for SATA */
552 reg = 521 reg = <3>;
553 always 522 always-on;
554 }; 523 };
555 si5341_4: out@ 524 si5341_4: out@4 {
556 /* ref 525 /* refclk4 for PS-GT, used for PCIE slot */
557 reg = 526 reg = <4>;
558 always 527 always-on;
559 }; 528 };
560 si5341_5: out@ 529 si5341_5: out@5 {
561 /* ref 530 /* refclk5 for PS-GT, used for PCIE */
562 reg = 531 reg = <5>;
563 always 532 always-on;
564 }; 533 };
565 si5341_6: out@ 534 si5341_6: out@6 {
566 /* ref 535 /* refclk6 PL CLK125 */
567 reg = 536 reg = <6>;
568 always 537 always-on;
569 }; 538 };
570 si5341_7: out@ 539 si5341_7: out@7 {
571 /* ref 540 /* refclk7 PL CLK74 */
572 reg = 541 reg = <7>;
573 always 542 always-on;
574 }; 543 };
575 si5341_9: out@ 544 si5341_9: out@9 {
576 /* ref 545 /* refclk9 used for PS_REF_CLK 33.3 MHz */
577 reg = 546 reg = <9>;
578 always 547 always-on;
579 }; 548 };
580 }; 549 };
581 }; 550 };
582 i2c@2 { 551 i2c@2 {
583 #address-cells = <1>; 552 #address-cells = <1>;
584 #size-cells = <0>; 553 #size-cells = <0>;
585 reg = <2>; 554 reg = <2>;
586 si570_1: clock-generat 555 si570_1: clock-generator@5d { /* USER SI570 - u42 */
587 #clock-cells = 556 #clock-cells = <0>;
588 compatible = " 557 compatible = "silabs,si570";
589 reg = <0x5d>; 558 reg = <0x5d>;
590 temperature-st 559 temperature-stability = <50>;
591 factory-fout = 560 factory-fout = <300000000>;
592 clock-frequenc 561 clock-frequency = <300000000>;
593 clock-output-n 562 clock-output-names = "si570_user";
594 }; 563 };
595 }; 564 };
596 i2c@3 { 565 i2c@3 {
597 #address-cells = <1>; 566 #address-cells = <1>;
598 #size-cells = <0>; 567 #size-cells = <0>;
599 reg = <3>; 568 reg = <3>;
600 si570_2: clock-generat 569 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
601 #clock-cells = 570 #clock-cells = <0>;
602 compatible = " 571 compatible = "silabs,si570";
603 reg = <0x5d>; 572 reg = <0x5d>;
604 temperature-st 573 temperature-stability = <50>; /* copy from zc702 */
605 factory-fout = 574 factory-fout = <156250000>;
606 clock-frequenc !! 575 clock-frequency = <148500000>;
607 clock-output-n 576 clock-output-names = "si570_mgt";
608 }; 577 };
609 }; 578 };
610 i2c@4 { 579 i2c@4 {
611 #address-cells = <1>; 580 #address-cells = <1>;
612 #size-cells = <0>; 581 #size-cells = <0>;
613 reg = <4>; 582 reg = <4>;
614 /* SI5328 - u20 */ !! 583 si5328: clock-generator@69 {/* SI5328 - u20 */
>> 584 reg = <0x69>;
>> 585 /*
>> 586 * Chip has interrupt present connected to PL
>> 587 * interrupt-parent = <&>;
>> 588 * interrupts = <>;
>> 589 */
>> 590 #address-cells = <1>;
>> 591 #size-cells = <0>;
>> 592 #clock-cells = <1>;
>> 593 clocks = <&refhdmi>;
>> 594 clock-names = "xtal";
>> 595 clock-output-names = "si5328";
>> 596
>> 597 si5328_clk: clk0@0 {
>> 598 reg = <0>;
>> 599 clock-frequency = <27000000>;
>> 600 };
>> 601 };
615 }; 602 };
616 /* 5 - 7 unconnected */ 603 /* 5 - 7 unconnected */
617 }; 604 };
618 605
619 i2c-mux@75 { 606 i2c-mux@75 {
620 compatible = "nxp,pca9548"; /* 607 compatible = "nxp,pca9548"; /* u135 */
621 #address-cells = <1>; 608 #address-cells = <1>;
622 #size-cells = <0>; 609 #size-cells = <0>;
623 reg = <0x75>; 610 reg = <0x75>;
624 611
625 i2c@0 { 612 i2c@0 {
626 #address-cells = <1>; 613 #address-cells = <1>;
627 #size-cells = <0>; 614 #size-cells = <0>;
628 reg = <0>; 615 reg = <0>;
629 /* HPC0_IIC */ 616 /* HPC0_IIC */
630 }; 617 };
631 i2c@1 { 618 i2c@1 {
632 #address-cells = <1>; 619 #address-cells = <1>;
633 #size-cells = <0>; 620 #size-cells = <0>;
634 reg = <1>; 621 reg = <1>;
635 /* HPC1_IIC */ 622 /* HPC1_IIC */
636 }; 623 };
637 i2c@2 { 624 i2c@2 {
638 #address-cells = <1>; 625 #address-cells = <1>;
639 #size-cells = <0>; 626 #size-cells = <0>;
640 reg = <2>; 627 reg = <2>;
641 /* SYSMON */ 628 /* SYSMON */
642 }; 629 };
643 i2c@3 { 630 i2c@3 {
644 #address-cells = <1>; 631 #address-cells = <1>;
645 #size-cells = <0>; 632 #size-cells = <0>;
646 reg = <3>; 633 reg = <3>;
647 /* DDR4 SODIMM */ 634 /* DDR4 SODIMM */
648 }; 635 };
649 i2c@4 { 636 i2c@4 {
650 #address-cells = <1>; 637 #address-cells = <1>;
651 #size-cells = <0>; 638 #size-cells = <0>;
652 reg = <4>; 639 reg = <4>;
653 /* SEP 3 */ 640 /* SEP 3 */
654 }; 641 };
655 i2c@5 { 642 i2c@5 {
656 #address-cells = <1>; 643 #address-cells = <1>;
657 #size-cells = <0>; 644 #size-cells = <0>;
658 reg = <5>; 645 reg = <5>;
659 /* SEP 2 */ 646 /* SEP 2 */
660 }; 647 };
661 i2c@6 { 648 i2c@6 {
662 #address-cells = <1>; 649 #address-cells = <1>;
663 #size-cells = <0>; 650 #size-cells = <0>;
664 reg = <6>; 651 reg = <6>;
665 /* SEP 1 */ 652 /* SEP 1 */
666 }; 653 };
667 i2c@7 { 654 i2c@7 {
668 #address-cells = <1>; 655 #address-cells = <1>;
669 #size-cells = <0>; 656 #size-cells = <0>;
670 reg = <7>; 657 reg = <7>;
671 /* SEP 0 */ 658 /* SEP 0 */
672 }; 659 };
673 }; 660 };
674 }; 661 };
675 662
676 &pinctrl0 { <<
677 status = "okay"; <<
678 pinctrl_i2c0_default: i2c0-default { <<
679 mux { <<
680 groups = "i2c0_3_grp"; <<
681 function = "i2c0"; <<
682 }; <<
683 <<
684 conf { <<
685 groups = "i2c0_3_grp"; <<
686 bias-pull-up; <<
687 slew-rate = <SLEW_RATE <<
688 power-source = <IO_STA <<
689 }; <<
690 }; <<
691 <<
692 pinctrl_i2c0_gpio: i2c0-gpio-grp { <<
693 mux { <<
694 groups = "gpio0_14_grp <<
695 function = "gpio0"; <<
696 }; <<
697 <<
698 conf { <<
699 groups = "gpio0_14_grp <<
700 slew-rate = <SLEW_RATE <<
701 power-source = <IO_STA <<
702 }; <<
703 }; <<
704 <<
705 pinctrl_i2c1_default: i2c1-default { <<
706 mux { <<
707 groups = "i2c1_4_grp"; <<
708 function = "i2c1"; <<
709 }; <<
710 <<
711 conf { <<
712 groups = "i2c1_4_grp"; <<
713 bias-pull-up; <<
714 slew-rate = <SLEW_RATE <<
715 power-source = <IO_STA <<
716 }; <<
717 }; <<
718 <<
719 pinctrl_i2c1_gpio: i2c1-gpio-grp { <<
720 mux { <<
721 groups = "gpio0_16_grp <<
722 function = "gpio0"; <<
723 }; <<
724 <<
725 conf { <<
726 groups = "gpio0_16_grp <<
727 slew-rate = <SLEW_RATE <<
728 power-source = <IO_STA <<
729 }; <<
730 }; <<
731 <<
732 pinctrl_uart0_default: uart0-default { <<
733 mux { <<
734 groups = "uart0_4_grp" <<
735 function = "uart0"; <<
736 }; <<
737 <<
738 conf { <<
739 groups = "uart0_4_grp" <<
740 slew-rate = <SLEW_RATE <<
741 power-source = <IO_STA <<
742 }; <<
743 <<
744 conf-rx { <<
745 pins = "MIO18"; <<
746 bias-high-impedance; <<
747 }; <<
748 <<
749 conf-tx { <<
750 pins = "MIO19"; <<
751 bias-disable; <<
752 }; <<
753 }; <<
754 <<
755 pinctrl_uart1_default: uart1-default { <<
756 mux { <<
757 groups = "uart1_5_grp" <<
758 function = "uart1"; <<
759 }; <<
760 <<
761 conf { <<
762 groups = "uart1_5_grp" <<
763 slew-rate = <SLEW_RATE <<
764 power-source = <IO_STA <<
765 }; <<
766 <<
767 conf-rx { <<
768 pins = "MIO21"; <<
769 bias-high-impedance; <<
770 }; <<
771 <<
772 conf-tx { <<
773 pins = "MIO20"; <<
774 bias-disable; <<
775 }; <<
776 }; <<
777 <<
778 pinctrl_usb0_default: usb0-default { <<
779 mux { <<
780 groups = "usb0_0_grp"; <<
781 function = "usb0"; <<
782 }; <<
783 <<
784 conf { <<
785 groups = "usb0_0_grp"; <<
786 power-source = <IO_STA <<
787 }; <<
788 <<
789 conf-rx { <<
790 pins = "MIO52", "MIO53 <<
791 bias-high-impedance; <<
792 drive-strength = <12>; <<
793 slew-rate = <SLEW_RATE <<
794 }; <<
795 <<
796 conf-tx { <<
797 pins = "MIO54", "MIO56 <<
798 "MIO60", "MIO61 <<
799 bias-disable; <<
800 drive-strength = <4>; <<
801 slew-rate = <SLEW_RATE <<
802 }; <<
803 }; <<
804 <<
805 pinctrl_gem3_default: gem3-default { <<
806 mux { <<
807 function = "ethernet3" <<
808 groups = "ethernet3_0_ <<
809 }; <<
810 <<
811 conf { <<
812 groups = "ethernet3_0_ <<
813 slew-rate = <SLEW_RATE <<
814 power-source = <IO_STA <<
815 }; <<
816 <<
817 conf-rx { <<
818 pins = "MIO70", "MIO71 <<
819 <<
820 bias-high-impedance; <<
821 low-power-disable; <<
822 }; <<
823 <<
824 conf-tx { <<
825 pins = "MIO64", "MIO65 <<
826 <<
827 bias-disable; <<
828 low-power-enable; <<
829 }; <<
830 <<
831 mux-mdio { <<
832 function = "mdio3"; <<
833 groups = "mdio3_0_grp" <<
834 }; <<
835 <<
836 conf-mdio { <<
837 groups = "mdio3_0_grp" <<
838 slew-rate = <SLEW_RATE <<
839 power-source = <IO_STA <<
840 bias-disable; <<
841 }; <<
842 }; <<
843 <<
844 pinctrl_can1_default: can1-default { <<
845 mux { <<
846 function = "can1"; <<
847 groups = "can1_6_grp"; <<
848 }; <<
849 <<
850 conf { <<
851 groups = "can1_6_grp"; <<
852 slew-rate = <SLEW_RATE <<
853 power-source = <IO_STA <<
854 }; <<
855 <<
856 conf-rx { <<
857 pins = "MIO25"; <<
858 bias-high-impedance; <<
859 }; <<
860 <<
861 conf-tx { <<
862 pins = "MIO24"; <<
863 bias-disable; <<
864 }; <<
865 }; <<
866 <<
867 pinctrl_sdhci1_default: sdhci1-default <<
868 mux { <<
869 groups = "sdio1_0_grp" <<
870 function = "sdio1"; <<
871 }; <<
872 <<
873 conf { <<
874 groups = "sdio1_0_grp" <<
875 slew-rate = <SLEW_RATE <<
876 power-source = <IO_STA <<
877 bias-disable; <<
878 }; <<
879 <<
880 mux-cd { <<
881 groups = "sdio1_cd_0_g <<
882 function = "sdio1_cd"; <<
883 }; <<
884 <<
885 conf-cd { <<
886 groups = "sdio1_cd_0_g <<
887 bias-high-impedance; <<
888 bias-pull-up; <<
889 slew-rate = <SLEW_RATE <<
890 power-source = <IO_STA <<
891 }; <<
892 <<
893 mux-wp { <<
894 groups = "sdio1_wp_0_g <<
895 function = "sdio1_wp"; <<
896 }; <<
897 <<
898 conf-wp { <<
899 groups = "sdio1_wp_0_g <<
900 bias-high-impedance; <<
901 bias-pull-up; <<
902 slew-rate = <SLEW_RATE <<
903 power-source = <IO_STA <<
904 }; <<
905 }; <<
906 <<
907 pinctrl_gpio_default: gpio-default { <<
908 mux-sw { <<
909 function = "gpio0"; <<
910 groups = "gpio0_22_grp <<
911 }; <<
912 <<
913 conf-sw { <<
914 groups = "gpio0_22_grp <<
915 slew-rate = <SLEW_RATE <<
916 power-source = <IO_STA <<
917 }; <<
918 <<
919 mux-msp { <<
920 function = "gpio0"; <<
921 groups = "gpio0_13_grp <<
922 }; <<
923 <<
924 conf-msp { <<
925 groups = "gpio0_13_grp <<
926 slew-rate = <SLEW_RATE <<
927 power-source = <IO_STA <<
928 }; <<
929 <<
930 conf-pull-up { <<
931 pins = "MIO22", "MIO23 <<
932 bias-pull-up; <<
933 }; <<
934 <<
935 conf-pull-none { <<
936 pins = "MIO13", "MIO38 <<
937 bias-disable; <<
938 }; <<
939 }; <<
940 }; <<
941 <<
942 &pcie { 663 &pcie {
943 status = "okay"; 664 status = "okay";
944 phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; <<
945 }; 665 };
946 666
947 &psgtr { 667 &psgtr {
948 status = "okay"; 668 status = "okay";
949 /* pcie, sata, usb3, dp */ 669 /* pcie, sata, usb3, dp */
950 clocks = <&si5341 0 5>, <&si5341 0 3>, 670 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
951 clock-names = "ref0", "ref1", "ref2", 671 clock-names = "ref0", "ref1", "ref2", "ref3";
952 }; 672 };
953 673
954 &qspi { <<
955 status = "okay"; <<
956 flash@0 { <<
957 compatible = "m25p80", "jedec, <<
958 #address-cells = <1>; <<
959 #size-cells = <1>; <<
960 reg = <0x0>; <<
961 spi-tx-bus-width = <4>; <<
962 spi-rx-bus-width = <4>; /* FIX <<
963 spi-max-frequency = <108000000 <<
964 }; <<
965 }; <<
966 <<
967 &rtc { 674 &rtc {
968 status = "okay"; 675 status = "okay";
969 }; 676 };
970 677
971 &sata { 678 &sata {
972 status = "okay"; 679 status = "okay";
973 /* SATA OOB timing settings */ 680 /* SATA OOB timing settings */
974 ceva,p0-cominit-params = /bits/ 8 <0x1 681 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
975 ceva,p0-comwake-params = /bits/ 8 <0x0 682 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
976 ceva,p0-burst-params = /bits/ 8 <0x13 683 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
977 ceva,p0-retry-params = /bits/ 16 <0x96 684 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
978 ceva,p1-cominit-params = /bits/ 8 <0x1 685 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
979 ceva,p1-comwake-params = /bits/ 8 <0x0 686 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
980 ceva,p1-burst-params = /bits/ 8 <0x13 687 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
981 ceva,p1-retry-params = /bits/ 16 <0x96 688 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
982 phy-names = "sata-phy"; 689 phy-names = "sata-phy";
983 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 690 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
984 }; 691 };
985 692
986 /* SD1 with level shifter */ 693 /* SD1 with level shifter */
987 &sdhci1 { 694 &sdhci1 {
988 status = "okay"; 695 status = "okay";
989 /* <<
990 * 1.0 revision has level shifter and <<
991 * removed for supporting UHS mode <<
992 */ <<
993 no-1-8-v; 696 no-1-8-v;
994 pinctrl-names = "default"; <<
995 pinctrl-0 = <&pinctrl_sdhci1_default>; <<
996 xlnx,mio-bank = <1>; 697 xlnx,mio-bank = <1>;
997 }; 698 };
998 699
999 &uart0 { 700 &uart0 {
1000 status = "okay"; 701 status = "okay";
1001 pinctrl-names = "default"; <<
1002 pinctrl-0 = <&pinctrl_uart0_default>; <<
1003 }; 702 };
1004 703
1005 &uart1 { 704 &uart1 {
1006 status = "okay"; 705 status = "okay";
1007 pinctrl-names = "default"; <<
1008 pinctrl-0 = <&pinctrl_uart1_default>; <<
1009 }; 706 };
1010 707
1011 /* ULPI SMSC USB3320 */ 708 /* ULPI SMSC USB3320 */
1012 &usb0 { 709 &usb0 {
1013 status = "okay"; 710 status = "okay";
1014 pinctrl-names = "default"; <<
1015 pinctrl-0 = <&pinctrl_usb0_default>; <<
1016 phy-names = "usb3-phy"; <<
1017 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; <<
1018 }; <<
1019 <<
1020 &dwc3_0 { <<
1021 status = "okay"; <<
1022 dr_mode = "host"; 711 dr_mode = "host";
1023 snps,usb3_lpm_capable; <<
1024 maximum-speed = "super-speed"; <<
1025 }; 712 };
1026 713
1027 &watchdog0 { 714 &watchdog0 {
1028 status = "okay"; <<
1029 }; <<
1030 <<
1031 &xilinx_ams { <<
1032 status = "okay"; <<
1033 }; <<
1034 <<
1035 &ams_ps { <<
1036 status = "okay"; <<
1037 }; <<
1038 <<
1039 &ams_pl { <<
1040 status = "okay"; 715 status = "okay";
1041 }; 716 };
1042 717
1043 &zynqmp_dpdma { 718 &zynqmp_dpdma {
1044 status = "okay"; 719 status = "okay";
1045 }; 720 };
1046 721
1047 &zynqmp_dpsub { 722 &zynqmp_dpsub {
1048 status = "okay"; 723 status = "okay";
1049 phy-names = "dp-phy0"; 724 phy-names = "dp-phy0";
1050 phys = <&psgtr 1 PHY_TYPE_DP 0 3>; 725 phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
1051 }; 726 };
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