1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * dts file for Xilinx ZynqMP ZCU102 RevA 3 * dts file for Xilinx ZynqMP ZCU102 RevA
4 * 4 *
5 * (C) Copyright 2015 - 2022, Xilinx, Inc. !! 5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro D <<
7 * 6 *
8 * Michal Simek <michal.simek@amd.com> !! 7 * Michal Simek <michal.simek@xilinx.com>
9 */ 8 */
10 9
11 /dts-v1/; 10 /dts-v1/;
12 11
13 #include "zynqmp.dtsi" 12 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi" 13 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h> 14 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h 16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h> 17 #include <dt-bindings/phy/phy.h>
19 18
20 / { 19 / {
21 model = "ZynqMP ZCU102 RevA"; 20 model = "ZynqMP ZCU102 RevA";
22 compatible = "xlnx,zynqmp-zcu102-revA" 21 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
23 22
24 aliases { 23 aliases {
25 ethernet0 = &gem3; 24 ethernet0 = &gem3;
26 i2c0 = &i2c0; 25 i2c0 = &i2c0;
27 i2c1 = &i2c1; 26 i2c1 = &i2c1;
28 mmc0 = &sdhci1; 27 mmc0 = &sdhci1;
29 nvmem0 = &eeprom; 28 nvmem0 = &eeprom;
30 rtc0 = &rtc; 29 rtc0 = &rtc;
31 serial0 = &uart0; 30 serial0 = &uart0;
32 serial1 = &uart1; 31 serial1 = &uart1;
33 serial2 = &dcc; 32 serial2 = &dcc;
34 spi0 = &qspi; 33 spi0 = &qspi;
35 usb0 = &usb0; 34 usb0 = &usb0;
36 }; 35 };
37 36
38 chosen { 37 chosen {
39 bootargs = "earlycon"; 38 bootargs = "earlycon";
40 stdout-path = "serial0:115200n 39 stdout-path = "serial0:115200n8";
41 }; 40 };
42 41
43 memory@0 { 42 memory@0 {
44 device_type = "memory"; 43 device_type = "memory";
45 reg = <0x0 0x0 0x0 0x80000000> 44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46 }; 45 };
47 46
48 gpio-keys { 47 gpio-keys {
49 compatible = "gpio-keys"; 48 compatible = "gpio-keys";
50 autorepeat; 49 autorepeat;
51 switch-19 { !! 50 sw19 {
52 label = "sw19"; 51 label = "sw19";
53 gpios = <&gpio 22 GPIO 52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN 53 linux,code = <KEY_DOWN>;
55 wakeup-source; 54 wakeup-source;
56 autorepeat; 55 autorepeat;
57 }; 56 };
58 }; 57 };
59 58
60 leds { 59 leds {
61 compatible = "gpio-leds"; 60 compatible = "gpio-leds";
62 heartbeat-led { 61 heartbeat-led {
63 label = "heartbeat"; 62 label = "heartbeat";
64 gpios = <&gpio 23 GPIO 63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger 64 linux,default-trigger = "heartbeat";
66 }; 65 };
67 }; 66 };
68 67
69 ina226-u76 { 68 ina226-u76 {
70 compatible = "iio-hwmon"; 69 compatible = "iio-hwmon";
71 io-channels = <&u76 0>, <&u76 70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
72 }; 71 };
73 ina226-u77 { 72 ina226-u77 {
74 compatible = "iio-hwmon"; 73 compatible = "iio-hwmon";
75 io-channels = <&u77 0>, <&u77 74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
76 }; 75 };
77 ina226-u78 { 76 ina226-u78 {
78 compatible = "iio-hwmon"; 77 compatible = "iio-hwmon";
79 io-channels = <&u78 0>, <&u78 78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
80 }; 79 };
81 ina226-u87 { 80 ina226-u87 {
82 compatible = "iio-hwmon"; 81 compatible = "iio-hwmon";
83 io-channels = <&u87 0>, <&u87 82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
84 }; 83 };
85 ina226-u85 { 84 ina226-u85 {
86 compatible = "iio-hwmon"; 85 compatible = "iio-hwmon";
87 io-channels = <&u85 0>, <&u85 86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
88 }; 87 };
89 ina226-u86 { 88 ina226-u86 {
90 compatible = "iio-hwmon"; 89 compatible = "iio-hwmon";
91 io-channels = <&u86 0>, <&u86 90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
92 }; 91 };
93 ina226-u93 { 92 ina226-u93 {
94 compatible = "iio-hwmon"; 93 compatible = "iio-hwmon";
95 io-channels = <&u93 0>, <&u93 94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
96 }; 95 };
97 ina226-u88 { 96 ina226-u88 {
98 compatible = "iio-hwmon"; 97 compatible = "iio-hwmon";
99 io-channels = <&u88 0>, <&u88 98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
100 }; 99 };
101 ina226-u15 { 100 ina226-u15 {
102 compatible = "iio-hwmon"; 101 compatible = "iio-hwmon";
103 io-channels = <&u15 0>, <&u15 102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
104 }; 103 };
105 ina226-u92 { 104 ina226-u92 {
106 compatible = "iio-hwmon"; 105 compatible = "iio-hwmon";
107 io-channels = <&u92 0>, <&u92 106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
108 }; 107 };
109 ina226-u79 { 108 ina226-u79 {
110 compatible = "iio-hwmon"; 109 compatible = "iio-hwmon";
111 io-channels = <&u79 0>, <&u79 110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
112 }; 111 };
113 ina226-u81 { 112 ina226-u81 {
114 compatible = "iio-hwmon"; 113 compatible = "iio-hwmon";
115 io-channels = <&u81 0>, <&u81 114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
116 }; 115 };
117 ina226-u80 { 116 ina226-u80 {
118 compatible = "iio-hwmon"; 117 compatible = "iio-hwmon";
119 io-channels = <&u80 0>, <&u80 118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
120 }; 119 };
121 ina226-u84 { 120 ina226-u84 {
122 compatible = "iio-hwmon"; 121 compatible = "iio-hwmon";
123 io-channels = <&u84 0>, <&u84 122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
124 }; 123 };
125 ina226-u16 { 124 ina226-u16 {
126 compatible = "iio-hwmon"; 125 compatible = "iio-hwmon";
127 io-channels = <&u16 0>, <&u16 126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
128 }; 127 };
129 ina226-u65 { 128 ina226-u65 {
130 compatible = "iio-hwmon"; 129 compatible = "iio-hwmon";
131 io-channels = <&u65 0>, <&u65 130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
132 }; 131 };
133 ina226-u74 { 132 ina226-u74 {
134 compatible = "iio-hwmon"; 133 compatible = "iio-hwmon";
135 io-channels = <&u74 0>, <&u74 134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
136 }; 135 };
137 ina226-u75 { 136 ina226-u75 {
138 compatible = "iio-hwmon"; 137 compatible = "iio-hwmon";
139 io-channels = <&u75 0>, <&u75 138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
140 }; 139 };
141 140
142 /* 48MHz reference crystal */ 141 /* 48MHz reference crystal */
143 ref48: ref48M { 142 ref48: ref48M {
144 compatible = "fixed-clock"; 143 compatible = "fixed-clock";
145 #clock-cells = <0>; 144 #clock-cells = <0>;
146 clock-frequency = <48000000>; 145 clock-frequency = <48000000>;
147 }; 146 };
148 147
149 refhdmi: refhdmi { 148 refhdmi: refhdmi {
150 compatible = "fixed-clock"; 149 compatible = "fixed-clock";
151 #clock-cells = <0>; 150 #clock-cells = <0>;
152 clock-frequency = <114285000>; 151 clock-frequency = <114285000>;
153 }; 152 };
154 }; 153 };
155 154
156 &can1 { 155 &can1 {
157 status = "okay"; 156 status = "okay";
158 pinctrl-names = "default"; 157 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_can1_default>; 158 pinctrl-0 = <&pinctrl_can1_default>;
160 }; 159 };
161 160
162 &dcc { 161 &dcc {
163 status = "okay"; 162 status = "okay";
164 }; 163 };
165 164
166 &fpd_dma_chan1 { 165 &fpd_dma_chan1 {
167 status = "okay"; 166 status = "okay";
168 }; 167 };
169 168
170 &fpd_dma_chan2 { 169 &fpd_dma_chan2 {
171 status = "okay"; 170 status = "okay";
172 }; 171 };
173 172
174 &fpd_dma_chan3 { 173 &fpd_dma_chan3 {
175 status = "okay"; 174 status = "okay";
176 }; 175 };
177 176
178 &fpd_dma_chan4 { 177 &fpd_dma_chan4 {
179 status = "okay"; 178 status = "okay";
180 }; 179 };
181 180
182 &fpd_dma_chan5 { 181 &fpd_dma_chan5 {
183 status = "okay"; 182 status = "okay";
184 }; 183 };
185 184
186 &fpd_dma_chan6 { 185 &fpd_dma_chan6 {
187 status = "okay"; 186 status = "okay";
188 }; 187 };
189 188
190 &fpd_dma_chan7 { 189 &fpd_dma_chan7 {
191 status = "okay"; 190 status = "okay";
192 }; 191 };
193 192
194 &fpd_dma_chan8 { 193 &fpd_dma_chan8 {
195 status = "okay"; 194 status = "okay";
196 }; 195 };
197 196
198 &gem3 { 197 &gem3 {
199 status = "okay"; 198 status = "okay";
200 phy-handle = <&phy0>; 199 phy-handle = <&phy0>;
201 phy-mode = "rgmii-id"; 200 phy-mode = "rgmii-id";
202 pinctrl-names = "default"; 201 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_gem3_default>; 202 pinctrl-0 = <&pinctrl_gem3_default>;
204 mdio: mdio { !! 203 phy0: ethernet-phy@21 {
205 #address-cells = <1>; !! 204 reg = <21>;
206 #size-cells = <0>; !! 205 ti,rx-internal-delay = <0x8>;
207 phy0: ethernet-phy@21 { !! 206 ti,tx-internal-delay = <0xa>;
208 #phy-cells = <1>; !! 207 ti,fifo-depth = <0x1>;
209 compatible = "ethernet !! 208 ti,dp83867-rxctrl-strap-quirk;
210 reg = <21>; !! 209 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
211 ti,rx-internal-delay = <<
212 ti,tx-internal-delay = <<
213 ti,fifo-depth = <0x1>; <<
214 ti,dp83867-rxctrl-stra <<
215 reset-gpios = <&tca641 <<
216 }; <<
217 }; 210 };
218 }; 211 };
219 212
220 &gpio { 213 &gpio {
221 status = "okay"; 214 status = "okay";
222 pinctrl-names = "default"; 215 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_gpio_default>; 216 pinctrl-0 = <&pinctrl_gpio_default>;
224 }; 217 };
225 218
226 &gpu { <<
227 status = "okay"; <<
228 }; <<
229 <<
230 &i2c0 { 219 &i2c0 {
231 status = "okay"; 220 status = "okay";
232 clock-frequency = <400000>; 221 clock-frequency = <400000>;
233 pinctrl-names = "default", "gpio"; 222 pinctrl-names = "default", "gpio";
234 pinctrl-0 = <&pinctrl_i2c0_default>; 223 pinctrl-0 = <&pinctrl_i2c0_default>;
235 pinctrl-1 = <&pinctrl_i2c0_gpio>; 224 pinctrl-1 = <&pinctrl_i2c0_gpio>;
236 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIG !! 225 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
237 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIG !! 226 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
238 227
239 tca6416_u97: gpio@20 { 228 tca6416_u97: gpio@20 {
240 compatible = "ti,tca6416"; 229 compatible = "ti,tca6416";
241 reg = <0x20>; 230 reg = <0x20>;
242 gpio-controller; /* IRQ not co 231 gpio-controller; /* IRQ not connected */
243 #gpio-cells = <2>; 232 #gpio-cells = <2>;
244 gpio-line-names = "PS_GTR_LAN_ 233 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
245 "PCI_CLK_DIR_S 234 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
246 "", "", "", "" 235 "", "", "", "", "", "", "", "", "";
247 gtr-sel0-hog { 236 gtr-sel0-hog {
248 gpio-hog; 237 gpio-hog;
249 gpios = <0 0>; 238 gpios = <0 0>;
250 output-low; /* PCIE = 239 output-low; /* PCIE = 0, DP = 1 */
251 line-name = "sel0"; 240 line-name = "sel0";
252 }; 241 };
253 gtr-sel1-hog { 242 gtr-sel1-hog {
254 gpio-hog; 243 gpio-hog;
255 gpios = <1 0>; 244 gpios = <1 0>;
256 output-high; /* PCIE = 245 output-high; /* PCIE = 0, DP = 1 */
257 line-name = "sel1"; 246 line-name = "sel1";
258 }; 247 };
259 gtr-sel2-hog { 248 gtr-sel2-hog {
260 gpio-hog; 249 gpio-hog;
261 gpios = <2 0>; 250 gpios = <2 0>;
262 output-high; /* PCIE = 251 output-high; /* PCIE = 0, USB0 = 1 */
263 line-name = "sel2"; 252 line-name = "sel2";
264 }; 253 };
265 gtr-sel3-hog { 254 gtr-sel3-hog {
266 gpio-hog; 255 gpio-hog;
267 gpios = <3 0>; 256 gpios = <3 0>;
268 output-high; /* PCIE = 257 output-high; /* PCIE = 0, SATA = 1 */
269 line-name = "sel3"; 258 line-name = "sel3";
270 }; 259 };
271 }; 260 };
272 261
273 tca6416_u61: gpio@21 { 262 tca6416_u61: gpio@21 {
274 compatible = "ti,tca6416"; 263 compatible = "ti,tca6416";
275 reg = <0x21>; 264 reg = <0x21>;
276 gpio-controller; /* IRQ not co 265 gpio-controller; /* IRQ not connected */
277 #gpio-cells = <2>; 266 #gpio-cells = <2>;
278 gpio-line-names = "VCCPSPLL_EN 267 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
279 "PL_PMBUS_ALER 268 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
280 "PL_DDR4_VPP_2 269 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
281 "PS_DDR4_VTERM 270 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
282 }; 271 };
283 272
284 i2c-mux@75 { /* u60 */ 273 i2c-mux@75 { /* u60 */
285 compatible = "nxp,pca9544"; 274 compatible = "nxp,pca9544";
286 #address-cells = <1>; 275 #address-cells = <1>;
287 #size-cells = <0>; 276 #size-cells = <0>;
288 reg = <0x75>; 277 reg = <0x75>;
289 i2c@0 { 278 i2c@0 {
290 #address-cells = <1>; 279 #address-cells = <1>;
291 #size-cells = <0>; 280 #size-cells = <0>;
292 reg = <0>; 281 reg = <0>;
293 /* PS_PMBUS */ 282 /* PS_PMBUS */
294 u76: ina226@40 { /* u7 283 u76: ina226@40 { /* u76 */
295 compatible = " 284 compatible = "ti,ina226";
296 #io-channel-ce 285 #io-channel-cells = <1>;
297 label = "ina22 286 label = "ina226-u76";
298 reg = <0x40>; 287 reg = <0x40>;
299 shunt-resistor 288 shunt-resistor = <5000>;
300 }; 289 };
301 u77: ina226@41 { /* u7 290 u77: ina226@41 { /* u77 */
302 compatible = " 291 compatible = "ti,ina226";
303 #io-channel-ce 292 #io-channel-cells = <1>;
304 label = "ina22 293 label = "ina226-u77";
305 reg = <0x41>; 294 reg = <0x41>;
306 shunt-resistor 295 shunt-resistor = <5000>;
307 }; 296 };
308 u78: ina226@42 { /* u7 297 u78: ina226@42 { /* u78 */
309 compatible = " 298 compatible = "ti,ina226";
310 #io-channel-ce 299 #io-channel-cells = <1>;
311 label = "ina22 300 label = "ina226-u78";
312 reg = <0x42>; 301 reg = <0x42>;
313 shunt-resistor 302 shunt-resistor = <5000>;
314 }; 303 };
315 u87: ina226@43 { /* u8 304 u87: ina226@43 { /* u87 */
316 compatible = " 305 compatible = "ti,ina226";
317 #io-channel-ce 306 #io-channel-cells = <1>;
318 label = "ina22 307 label = "ina226-u87";
319 reg = <0x43>; 308 reg = <0x43>;
320 shunt-resistor 309 shunt-resistor = <5000>;
321 }; 310 };
322 u85: ina226@44 { /* u8 311 u85: ina226@44 { /* u85 */
323 compatible = " 312 compatible = "ti,ina226";
324 #io-channel-ce 313 #io-channel-cells = <1>;
325 label = "ina22 314 label = "ina226-u85";
326 reg = <0x44>; 315 reg = <0x44>;
327 shunt-resistor 316 shunt-resistor = <5000>;
328 }; 317 };
329 u86: ina226@45 { /* u8 318 u86: ina226@45 { /* u86 */
330 compatible = " 319 compatible = "ti,ina226";
331 #io-channel-ce 320 #io-channel-cells = <1>;
332 label = "ina22 321 label = "ina226-u86";
333 reg = <0x45>; 322 reg = <0x45>;
334 shunt-resistor 323 shunt-resistor = <5000>;
335 }; 324 };
336 u93: ina226@46 { /* u9 325 u93: ina226@46 { /* u93 */
337 compatible = " 326 compatible = "ti,ina226";
338 #io-channel-ce 327 #io-channel-cells = <1>;
339 label = "ina22 328 label = "ina226-u93";
340 reg = <0x46>; 329 reg = <0x46>;
341 shunt-resistor 330 shunt-resistor = <5000>;
342 }; 331 };
343 u88: ina226@47 { /* u8 332 u88: ina226@47 { /* u88 */
344 compatible = " 333 compatible = "ti,ina226";
345 #io-channel-ce 334 #io-channel-cells = <1>;
346 label = "ina22 335 label = "ina226-u88";
347 reg = <0x47>; 336 reg = <0x47>;
348 shunt-resistor 337 shunt-resistor = <5000>;
349 }; 338 };
350 u15: ina226@4a { /* u1 339 u15: ina226@4a { /* u15 */
351 compatible = " 340 compatible = "ti,ina226";
352 #io-channel-ce 341 #io-channel-cells = <1>;
353 label = "ina22 342 label = "ina226-u15";
354 reg = <0x4a>; 343 reg = <0x4a>;
355 shunt-resistor 344 shunt-resistor = <5000>;
356 }; 345 };
357 u92: ina226@4b { /* u9 346 u92: ina226@4b { /* u92 */
358 compatible = " 347 compatible = "ti,ina226";
359 #io-channel-ce 348 #io-channel-cells = <1>;
360 label = "ina22 349 label = "ina226-u92";
361 reg = <0x4b>; 350 reg = <0x4b>;
362 shunt-resistor 351 shunt-resistor = <5000>;
363 }; 352 };
364 }; 353 };
365 i2c@1 { 354 i2c@1 {
366 #address-cells = <1>; 355 #address-cells = <1>;
367 #size-cells = <0>; 356 #size-cells = <0>;
368 reg = <1>; 357 reg = <1>;
369 /* PL_PMBUS */ 358 /* PL_PMBUS */
370 u79: ina226@40 { /* u7 359 u79: ina226@40 { /* u79 */
371 compatible = " 360 compatible = "ti,ina226";
372 #io-channel-ce 361 #io-channel-cells = <1>;
373 label = "ina22 362 label = "ina226-u79";
374 reg = <0x40>; 363 reg = <0x40>;
375 shunt-resistor 364 shunt-resistor = <2000>;
376 }; 365 };
377 u81: ina226@41 { /* u8 366 u81: ina226@41 { /* u81 */
378 compatible = " 367 compatible = "ti,ina226";
379 #io-channel-ce 368 #io-channel-cells = <1>;
380 label = "ina22 369 label = "ina226-u81";
381 reg = <0x41>; 370 reg = <0x41>;
382 shunt-resistor 371 shunt-resistor = <5000>;
383 }; 372 };
384 u80: ina226@42 { /* u8 373 u80: ina226@42 { /* u80 */
385 compatible = " 374 compatible = "ti,ina226";
386 #io-channel-ce 375 #io-channel-cells = <1>;
387 label = "ina22 376 label = "ina226-u80";
388 reg = <0x42>; 377 reg = <0x42>;
389 shunt-resistor 378 shunt-resistor = <5000>;
390 }; 379 };
391 u84: ina226@43 { /* u8 380 u84: ina226@43 { /* u84 */
392 compatible = " 381 compatible = "ti,ina226";
393 #io-channel-ce 382 #io-channel-cells = <1>;
394 label = "ina22 383 label = "ina226-u84";
395 reg = <0x43>; 384 reg = <0x43>;
396 shunt-resistor 385 shunt-resistor = <5000>;
397 }; 386 };
398 u16: ina226@44 { /* u1 387 u16: ina226@44 { /* u16 */
399 compatible = " 388 compatible = "ti,ina226";
400 #io-channel-ce 389 #io-channel-cells = <1>;
401 label = "ina22 390 label = "ina226-u16";
402 reg = <0x44>; 391 reg = <0x44>;
403 shunt-resistor 392 shunt-resistor = <5000>;
404 }; 393 };
405 u65: ina226@45 { /* u6 394 u65: ina226@45 { /* u65 */
406 compatible = " 395 compatible = "ti,ina226";
407 #io-channel-ce 396 #io-channel-cells = <1>;
408 label = "ina22 397 label = "ina226-u65";
409 reg = <0x45>; 398 reg = <0x45>;
410 shunt-resistor 399 shunt-resistor = <5000>;
411 }; 400 };
412 u74: ina226@46 { /* u7 401 u74: ina226@46 { /* u74 */
413 compatible = " 402 compatible = "ti,ina226";
414 #io-channel-ce 403 #io-channel-cells = <1>;
415 label = "ina22 404 label = "ina226-u74";
416 reg = <0x46>; 405 reg = <0x46>;
417 shunt-resistor 406 shunt-resistor = <5000>;
418 }; 407 };
419 u75: ina226@47 { /* u7 408 u75: ina226@47 { /* u75 */
420 compatible = " 409 compatible = "ti,ina226";
421 #io-channel-ce 410 #io-channel-cells = <1>;
422 label = "ina22 411 label = "ina226-u75";
423 reg = <0x47>; 412 reg = <0x47>;
424 shunt-resistor 413 shunt-resistor = <5000>;
425 }; 414 };
426 }; 415 };
427 i2c@2 { 416 i2c@2 {
428 #address-cells = <1>; 417 #address-cells = <1>;
429 #size-cells = <0>; 418 #size-cells = <0>;
430 reg = <2>; 419 reg = <2>;
431 /* MAXIM_PMBUS - 00 */ 420 /* MAXIM_PMBUS - 00 */
432 max15301@a { /* u46 */ 421 max15301@a { /* u46 */
433 compatible = " 422 compatible = "maxim,max15301";
434 reg = <0xa>; 423 reg = <0xa>;
435 }; 424 };
436 max15303@b { /* u4 */ 425 max15303@b { /* u4 */
437 compatible = " 426 compatible = "maxim,max15303";
438 reg = <0xb>; 427 reg = <0xb>;
439 }; 428 };
440 max15303@10 { /* u13 * 429 max15303@10 { /* u13 */
441 compatible = " 430 compatible = "maxim,max15303";
442 reg = <0x10>; 431 reg = <0x10>;
443 }; 432 };
444 max15301@13 { /* u47 * 433 max15301@13 { /* u47 */
445 compatible = " 434 compatible = "maxim,max15301";
446 reg = <0x13>; 435 reg = <0x13>;
447 }; 436 };
448 max15303@14 { /* u7 */ 437 max15303@14 { /* u7 */
449 compatible = " 438 compatible = "maxim,max15303";
450 reg = <0x14>; 439 reg = <0x14>;
451 }; 440 };
452 max15303@15 { /* u6 */ 441 max15303@15 { /* u6 */
453 compatible = " 442 compatible = "maxim,max15303";
454 reg = <0x15>; 443 reg = <0x15>;
455 }; 444 };
456 max15303@16 { /* u10 * 445 max15303@16 { /* u10 */
457 compatible = " 446 compatible = "maxim,max15303";
458 reg = <0x16>; 447 reg = <0x16>;
459 }; 448 };
460 max15303@17 { /* u9 */ 449 max15303@17 { /* u9 */
461 compatible = " 450 compatible = "maxim,max15303";
462 reg = <0x17>; 451 reg = <0x17>;
463 }; 452 };
464 max15301@18 { /* u63 * 453 max15301@18 { /* u63 */
465 compatible = " 454 compatible = "maxim,max15301";
466 reg = <0x18>; 455 reg = <0x18>;
467 }; 456 };
468 max15303@1a { /* u49 * 457 max15303@1a { /* u49 */
469 compatible = " 458 compatible = "maxim,max15303";
470 reg = <0x1a>; 459 reg = <0x1a>;
471 }; 460 };
472 max15303@1d { /* u18 * 461 max15303@1d { /* u18 */
473 compatible = " 462 compatible = "maxim,max15303";
474 reg = <0x1d>; 463 reg = <0x1d>;
475 }; 464 };
476 max15303@20 { /* u8 */ 465 max15303@20 { /* u8 */
477 compatible = " 466 compatible = "maxim,max15303";
478 status = "disa 467 status = "disabled"; /* unreachable */
479 reg = <0x20>; 468 reg = <0x20>;
480 }; 469 };
481 max20751@72 { /* u95 * 470 max20751@72 { /* u95 */
482 compatible = " 471 compatible = "maxim,max20751";
483 reg = <0x72>; 472 reg = <0x72>;
484 }; 473 };
485 max20751@73 { /* u96 * 474 max20751@73 { /* u96 */
486 compatible = " 475 compatible = "maxim,max20751";
487 reg = <0x73>; 476 reg = <0x73>;
488 }; 477 };
489 }; 478 };
490 /* Bus 3 is not connected */ 479 /* Bus 3 is not connected */
491 }; 480 };
492 }; 481 };
493 482
494 &i2c1 { 483 &i2c1 {
495 status = "okay"; 484 status = "okay";
496 clock-frequency = <400000>; 485 clock-frequency = <400000>;
497 pinctrl-names = "default", "gpio"; 486 pinctrl-names = "default", "gpio";
498 pinctrl-0 = <&pinctrl_i2c1_default>; 487 pinctrl-0 = <&pinctrl_i2c1_default>;
499 pinctrl-1 = <&pinctrl_i2c1_gpio>; 488 pinctrl-1 = <&pinctrl_i2c1_gpio>;
500 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIG !! 489 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
501 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIG !! 490 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
502 491
503 /* PL i2c via PCA9306 - u45 */ 492 /* PL i2c via PCA9306 - u45 */
504 i2c-mux@74 { /* u34 */ 493 i2c-mux@74 { /* u34 */
505 compatible = "nxp,pca9548"; 494 compatible = "nxp,pca9548";
506 #address-cells = <1>; 495 #address-cells = <1>;
507 #size-cells = <0>; 496 #size-cells = <0>;
508 reg = <0x74>; 497 reg = <0x74>;
509 i2c@0 { 498 i2c@0 {
510 #address-cells = <1>; 499 #address-cells = <1>;
511 #size-cells = <0>; 500 #size-cells = <0>;
512 reg = <0>; 501 reg = <0>;
513 /* 502 /*
514 * IIC_EEPROM 1kB memo 503 * IIC_EEPROM 1kB memory which uses 256B blocks
515 * where every block h 504 * where every block has different address.
516 * 0 - 256B address 505 * 0 - 256B address 0x54
517 * 256B - 512B address 506 * 256B - 512B address 0x55
518 * 512B - 768B address 507 * 512B - 768B address 0x56
519 * 768B - 1024B addres 508 * 768B - 1024B address 0x57
520 */ 509 */
521 eeprom: eeprom@54 { /* 510 eeprom: eeprom@54 { /* u23 */
522 compatible = " 511 compatible = "atmel,24c08";
523 reg = <0x54>; 512 reg = <0x54>;
524 }; 513 };
525 }; 514 };
526 i2c@1 { 515 i2c@1 {
527 #address-cells = <1>; 516 #address-cells = <1>;
528 #size-cells = <0>; 517 #size-cells = <0>;
529 reg = <1>; 518 reg = <1>;
530 si5341: clock-generato 519 si5341: clock-generator@36 { /* SI5341 - u69 */
531 compatible = " 520 compatible = "silabs,si5341";
532 reg = <0x36>; 521 reg = <0x36>;
533 #clock-cells = 522 #clock-cells = <2>;
534 #address-cells 523 #address-cells = <1>;
535 #size-cells = 524 #size-cells = <0>;
536 clocks = <&ref 525 clocks = <&ref48>;
537 clock-names = 526 clock-names = "xtal";
538 clock-output-n 527 clock-output-names = "si5341";
539 528
540 si5341_0: out@ 529 si5341_0: out@0 {
541 /* ref 530 /* refclk0 for PS-GT, used for DP */
542 reg = 531 reg = <0>;
543 always 532 always-on;
544 }; 533 };
545 si5341_2: out@ 534 si5341_2: out@2 {
546 /* ref 535 /* refclk2 for PS-GT, used for USB3 */
547 reg = 536 reg = <2>;
548 always 537 always-on;
549 }; 538 };
550 si5341_3: out@ 539 si5341_3: out@3 {
551 /* ref 540 /* refclk3 for PS-GT, used for SATA */
552 reg = 541 reg = <3>;
553 always 542 always-on;
554 }; 543 };
555 si5341_4: out@ 544 si5341_4: out@4 {
556 /* ref 545 /* refclk4 for PS-GT, used for PCIE slot */
557 reg = 546 reg = <4>;
558 always 547 always-on;
559 }; 548 };
560 si5341_5: out@ 549 si5341_5: out@5 {
561 /* ref 550 /* refclk5 for PS-GT, used for PCIE */
562 reg = 551 reg = <5>;
563 always 552 always-on;
564 }; 553 };
565 si5341_6: out@ 554 si5341_6: out@6 {
566 /* ref 555 /* refclk6 PL CLK125 */
567 reg = 556 reg = <6>;
568 always 557 always-on;
569 }; 558 };
570 si5341_7: out@ 559 si5341_7: out@7 {
571 /* ref 560 /* refclk7 PL CLK74 */
572 reg = 561 reg = <7>;
573 always 562 always-on;
574 }; 563 };
575 si5341_9: out@ 564 si5341_9: out@9 {
576 /* ref 565 /* refclk9 used for PS_REF_CLK 33.3 MHz */
577 reg = 566 reg = <9>;
578 always 567 always-on;
579 }; 568 };
580 }; 569 };
581 }; 570 };
582 i2c@2 { 571 i2c@2 {
583 #address-cells = <1>; 572 #address-cells = <1>;
584 #size-cells = <0>; 573 #size-cells = <0>;
585 reg = <2>; 574 reg = <2>;
586 si570_1: clock-generat 575 si570_1: clock-generator@5d { /* USER SI570 - u42 */
587 #clock-cells = 576 #clock-cells = <0>;
588 compatible = " 577 compatible = "silabs,si570";
589 reg = <0x5d>; 578 reg = <0x5d>;
590 temperature-st 579 temperature-stability = <50>;
591 factory-fout = 580 factory-fout = <300000000>;
592 clock-frequenc 581 clock-frequency = <300000000>;
593 clock-output-n 582 clock-output-names = "si570_user";
594 }; 583 };
595 }; 584 };
596 i2c@3 { 585 i2c@3 {
597 #address-cells = <1>; 586 #address-cells = <1>;
598 #size-cells = <0>; 587 #size-cells = <0>;
599 reg = <3>; 588 reg = <3>;
600 si570_2: clock-generat 589 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
601 #clock-cells = 590 #clock-cells = <0>;
602 compatible = " 591 compatible = "silabs,si570";
603 reg = <0x5d>; 592 reg = <0x5d>;
604 temperature-st 593 temperature-stability = <50>; /* copy from zc702 */
605 factory-fout = 594 factory-fout = <156250000>;
606 clock-frequenc !! 595 clock-frequency = <148500000>;
607 clock-output-n 596 clock-output-names = "si570_mgt";
608 }; 597 };
609 }; 598 };
610 i2c@4 { 599 i2c@4 {
611 #address-cells = <1>; 600 #address-cells = <1>;
612 #size-cells = <0>; 601 #size-cells = <0>;
613 reg = <4>; 602 reg = <4>;
614 /* SI5328 - u20 */ 603 /* SI5328 - u20 */
615 }; 604 };
616 /* 5 - 7 unconnected */ 605 /* 5 - 7 unconnected */
617 }; 606 };
618 607
619 i2c-mux@75 { 608 i2c-mux@75 {
620 compatible = "nxp,pca9548"; /* 609 compatible = "nxp,pca9548"; /* u135 */
621 #address-cells = <1>; 610 #address-cells = <1>;
622 #size-cells = <0>; 611 #size-cells = <0>;
623 reg = <0x75>; 612 reg = <0x75>;
624 613
625 i2c@0 { 614 i2c@0 {
626 #address-cells = <1>; 615 #address-cells = <1>;
627 #size-cells = <0>; 616 #size-cells = <0>;
628 reg = <0>; 617 reg = <0>;
629 /* HPC0_IIC */ 618 /* HPC0_IIC */
630 }; 619 };
631 i2c@1 { 620 i2c@1 {
632 #address-cells = <1>; 621 #address-cells = <1>;
633 #size-cells = <0>; 622 #size-cells = <0>;
634 reg = <1>; 623 reg = <1>;
635 /* HPC1_IIC */ 624 /* HPC1_IIC */
636 }; 625 };
637 i2c@2 { 626 i2c@2 {
638 #address-cells = <1>; 627 #address-cells = <1>;
639 #size-cells = <0>; 628 #size-cells = <0>;
640 reg = <2>; 629 reg = <2>;
641 /* SYSMON */ 630 /* SYSMON */
642 }; 631 };
643 i2c@3 { 632 i2c@3 {
644 #address-cells = <1>; 633 #address-cells = <1>;
645 #size-cells = <0>; 634 #size-cells = <0>;
646 reg = <3>; 635 reg = <3>;
647 /* DDR4 SODIMM */ 636 /* DDR4 SODIMM */
648 }; 637 };
649 i2c@4 { 638 i2c@4 {
650 #address-cells = <1>; 639 #address-cells = <1>;
651 #size-cells = <0>; 640 #size-cells = <0>;
652 reg = <4>; 641 reg = <4>;
653 /* SEP 3 */ 642 /* SEP 3 */
654 }; 643 };
655 i2c@5 { 644 i2c@5 {
656 #address-cells = <1>; 645 #address-cells = <1>;
657 #size-cells = <0>; 646 #size-cells = <0>;
658 reg = <5>; 647 reg = <5>;
659 /* SEP 2 */ 648 /* SEP 2 */
660 }; 649 };
661 i2c@6 { 650 i2c@6 {
662 #address-cells = <1>; 651 #address-cells = <1>;
663 #size-cells = <0>; 652 #size-cells = <0>;
664 reg = <6>; 653 reg = <6>;
665 /* SEP 1 */ 654 /* SEP 1 */
666 }; 655 };
667 i2c@7 { 656 i2c@7 {
668 #address-cells = <1>; 657 #address-cells = <1>;
669 #size-cells = <0>; 658 #size-cells = <0>;
670 reg = <7>; 659 reg = <7>;
671 /* SEP 0 */ 660 /* SEP 0 */
672 }; 661 };
673 }; 662 };
674 }; 663 };
675 664
676 &pinctrl0 { 665 &pinctrl0 {
677 status = "okay"; 666 status = "okay";
678 pinctrl_i2c0_default: i2c0-default { 667 pinctrl_i2c0_default: i2c0-default {
679 mux { 668 mux {
680 groups = "i2c0_3_grp"; 669 groups = "i2c0_3_grp";
681 function = "i2c0"; 670 function = "i2c0";
682 }; 671 };
683 672
684 conf { 673 conf {
685 groups = "i2c0_3_grp"; 674 groups = "i2c0_3_grp";
686 bias-pull-up; 675 bias-pull-up;
687 slew-rate = <SLEW_RATE 676 slew-rate = <SLEW_RATE_SLOW>;
688 power-source = <IO_STA 677 power-source = <IO_STANDARD_LVCMOS18>;
689 }; 678 };
690 }; 679 };
691 680
692 pinctrl_i2c0_gpio: i2c0-gpio-grp { !! 681 pinctrl_i2c0_gpio: i2c0-gpio {
693 mux { 682 mux {
694 groups = "gpio0_14_grp 683 groups = "gpio0_14_grp", "gpio0_15_grp";
695 function = "gpio0"; 684 function = "gpio0";
696 }; 685 };
697 686
698 conf { 687 conf {
699 groups = "gpio0_14_grp 688 groups = "gpio0_14_grp", "gpio0_15_grp";
700 slew-rate = <SLEW_RATE 689 slew-rate = <SLEW_RATE_SLOW>;
701 power-source = <IO_STA 690 power-source = <IO_STANDARD_LVCMOS18>;
702 }; 691 };
703 }; 692 };
704 693
705 pinctrl_i2c1_default: i2c1-default { 694 pinctrl_i2c1_default: i2c1-default {
706 mux { 695 mux {
707 groups = "i2c1_4_grp"; 696 groups = "i2c1_4_grp";
708 function = "i2c1"; 697 function = "i2c1";
709 }; 698 };
710 699
711 conf { 700 conf {
712 groups = "i2c1_4_grp"; 701 groups = "i2c1_4_grp";
713 bias-pull-up; 702 bias-pull-up;
714 slew-rate = <SLEW_RATE 703 slew-rate = <SLEW_RATE_SLOW>;
715 power-source = <IO_STA 704 power-source = <IO_STANDARD_LVCMOS18>;
716 }; 705 };
717 }; 706 };
718 707
719 pinctrl_i2c1_gpio: i2c1-gpio-grp { !! 708 pinctrl_i2c1_gpio: i2c1-gpio {
720 mux { 709 mux {
721 groups = "gpio0_16_grp 710 groups = "gpio0_16_grp", "gpio0_17_grp";
722 function = "gpio0"; 711 function = "gpio0";
723 }; 712 };
724 713
725 conf { 714 conf {
726 groups = "gpio0_16_grp 715 groups = "gpio0_16_grp", "gpio0_17_grp";
727 slew-rate = <SLEW_RATE 716 slew-rate = <SLEW_RATE_SLOW>;
728 power-source = <IO_STA 717 power-source = <IO_STANDARD_LVCMOS18>;
729 }; 718 };
730 }; 719 };
731 720
732 pinctrl_uart0_default: uart0-default { 721 pinctrl_uart0_default: uart0-default {
733 mux { 722 mux {
734 groups = "uart0_4_grp" 723 groups = "uart0_4_grp";
735 function = "uart0"; 724 function = "uart0";
736 }; 725 };
737 726
738 conf { 727 conf {
739 groups = "uart0_4_grp" 728 groups = "uart0_4_grp";
740 slew-rate = <SLEW_RATE 729 slew-rate = <SLEW_RATE_SLOW>;
741 power-source = <IO_STA 730 power-source = <IO_STANDARD_LVCMOS18>;
742 }; 731 };
743 732
744 conf-rx { 733 conf-rx {
745 pins = "MIO18"; 734 pins = "MIO18";
746 bias-high-impedance; 735 bias-high-impedance;
747 }; 736 };
748 737
749 conf-tx { 738 conf-tx {
750 pins = "MIO19"; 739 pins = "MIO19";
751 bias-disable; 740 bias-disable;
752 }; 741 };
753 }; 742 };
754 743
755 pinctrl_uart1_default: uart1-default { 744 pinctrl_uart1_default: uart1-default {
756 mux { 745 mux {
757 groups = "uart1_5_grp" 746 groups = "uart1_5_grp";
758 function = "uart1"; 747 function = "uart1";
759 }; 748 };
760 749
761 conf { 750 conf {
762 groups = "uart1_5_grp" 751 groups = "uart1_5_grp";
763 slew-rate = <SLEW_RATE 752 slew-rate = <SLEW_RATE_SLOW>;
764 power-source = <IO_STA 753 power-source = <IO_STANDARD_LVCMOS18>;
765 }; 754 };
766 755
767 conf-rx { 756 conf-rx {
768 pins = "MIO21"; 757 pins = "MIO21";
769 bias-high-impedance; 758 bias-high-impedance;
770 }; 759 };
771 760
772 conf-tx { 761 conf-tx {
773 pins = "MIO20"; 762 pins = "MIO20";
774 bias-disable; 763 bias-disable;
775 }; 764 };
776 }; 765 };
777 766
778 pinctrl_usb0_default: usb0-default { 767 pinctrl_usb0_default: usb0-default {
779 mux { 768 mux {
780 groups = "usb0_0_grp"; 769 groups = "usb0_0_grp";
781 function = "usb0"; 770 function = "usb0";
782 }; 771 };
783 772
784 conf { 773 conf {
785 groups = "usb0_0_grp"; 774 groups = "usb0_0_grp";
>> 775 slew-rate = <SLEW_RATE_SLOW>;
786 power-source = <IO_STA 776 power-source = <IO_STANDARD_LVCMOS18>;
787 }; 777 };
788 778
789 conf-rx { 779 conf-rx {
790 pins = "MIO52", "MIO53 780 pins = "MIO52", "MIO53", "MIO55";
791 bias-high-impedance; 781 bias-high-impedance;
792 drive-strength = <12>; <<
793 slew-rate = <SLEW_RATE <<
794 }; 782 };
795 783
796 conf-tx { 784 conf-tx {
797 pins = "MIO54", "MIO56 785 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
798 "MIO60", "MIO61 786 "MIO60", "MIO61", "MIO62", "MIO63";
799 bias-disable; 787 bias-disable;
800 drive-strength = <4>; <<
801 slew-rate = <SLEW_RATE <<
802 }; 788 };
803 }; 789 };
804 790
805 pinctrl_gem3_default: gem3-default { 791 pinctrl_gem3_default: gem3-default {
806 mux { 792 mux {
807 function = "ethernet3" 793 function = "ethernet3";
808 groups = "ethernet3_0_ 794 groups = "ethernet3_0_grp";
809 }; 795 };
810 796
811 conf { 797 conf {
812 groups = "ethernet3_0_ 798 groups = "ethernet3_0_grp";
813 slew-rate = <SLEW_RATE 799 slew-rate = <SLEW_RATE_SLOW>;
814 power-source = <IO_STA 800 power-source = <IO_STANDARD_LVCMOS18>;
815 }; 801 };
816 802
817 conf-rx { 803 conf-rx {
818 pins = "MIO70", "MIO71 804 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
819 805 "MIO75";
820 bias-high-impedance; 806 bias-high-impedance;
821 low-power-disable; 807 low-power-disable;
822 }; 808 };
823 809
824 conf-tx { 810 conf-tx {
825 pins = "MIO64", "MIO65 811 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
826 812 "MIO69";
827 bias-disable; 813 bias-disable;
828 low-power-enable; 814 low-power-enable;
829 }; 815 };
830 816
831 mux-mdio { 817 mux-mdio {
832 function = "mdio3"; 818 function = "mdio3";
833 groups = "mdio3_0_grp" 819 groups = "mdio3_0_grp";
834 }; 820 };
835 821
836 conf-mdio { 822 conf-mdio {
837 groups = "mdio3_0_grp" 823 groups = "mdio3_0_grp";
838 slew-rate = <SLEW_RATE 824 slew-rate = <SLEW_RATE_SLOW>;
839 power-source = <IO_STA 825 power-source = <IO_STANDARD_LVCMOS18>;
840 bias-disable; 826 bias-disable;
841 }; 827 };
842 }; 828 };
843 829
844 pinctrl_can1_default: can1-default { 830 pinctrl_can1_default: can1-default {
845 mux { 831 mux {
846 function = "can1"; 832 function = "can1";
847 groups = "can1_6_grp"; 833 groups = "can1_6_grp";
848 }; 834 };
849 835
850 conf { 836 conf {
851 groups = "can1_6_grp"; 837 groups = "can1_6_grp";
852 slew-rate = <SLEW_RATE 838 slew-rate = <SLEW_RATE_SLOW>;
853 power-source = <IO_STA 839 power-source = <IO_STANDARD_LVCMOS18>;
854 }; 840 };
855 841
856 conf-rx { 842 conf-rx {
857 pins = "MIO25"; 843 pins = "MIO25";
858 bias-high-impedance; 844 bias-high-impedance;
859 }; 845 };
860 846
861 conf-tx { 847 conf-tx {
862 pins = "MIO24"; 848 pins = "MIO24";
863 bias-disable; 849 bias-disable;
864 }; 850 };
865 }; 851 };
866 852
867 pinctrl_sdhci1_default: sdhci1-default 853 pinctrl_sdhci1_default: sdhci1-default {
868 mux { 854 mux {
869 groups = "sdio1_0_grp" 855 groups = "sdio1_0_grp";
870 function = "sdio1"; 856 function = "sdio1";
871 }; 857 };
872 858
873 conf { 859 conf {
874 groups = "sdio1_0_grp" 860 groups = "sdio1_0_grp";
875 slew-rate = <SLEW_RATE 861 slew-rate = <SLEW_RATE_SLOW>;
876 power-source = <IO_STA 862 power-source = <IO_STANDARD_LVCMOS18>;
877 bias-disable; 863 bias-disable;
878 }; 864 };
879 865
880 mux-cd { 866 mux-cd {
881 groups = "sdio1_cd_0_g 867 groups = "sdio1_cd_0_grp";
882 function = "sdio1_cd"; 868 function = "sdio1_cd";
883 }; 869 };
884 870
885 conf-cd { 871 conf-cd {
886 groups = "sdio1_cd_0_g 872 groups = "sdio1_cd_0_grp";
887 bias-high-impedance; 873 bias-high-impedance;
888 bias-pull-up; 874 bias-pull-up;
889 slew-rate = <SLEW_RATE 875 slew-rate = <SLEW_RATE_SLOW>;
890 power-source = <IO_STA 876 power-source = <IO_STANDARD_LVCMOS18>;
891 }; 877 };
892 878
893 mux-wp { 879 mux-wp {
894 groups = "sdio1_wp_0_g 880 groups = "sdio1_wp_0_grp";
895 function = "sdio1_wp"; 881 function = "sdio1_wp";
896 }; 882 };
897 883
898 conf-wp { 884 conf-wp {
899 groups = "sdio1_wp_0_g 885 groups = "sdio1_wp_0_grp";
900 bias-high-impedance; 886 bias-high-impedance;
901 bias-pull-up; 887 bias-pull-up;
902 slew-rate = <SLEW_RATE 888 slew-rate = <SLEW_RATE_SLOW>;
903 power-source = <IO_STA 889 power-source = <IO_STANDARD_LVCMOS18>;
904 }; 890 };
905 }; 891 };
906 892
907 pinctrl_gpio_default: gpio-default { 893 pinctrl_gpio_default: gpio-default {
908 mux-sw { 894 mux-sw {
909 function = "gpio0"; 895 function = "gpio0";
910 groups = "gpio0_22_grp 896 groups = "gpio0_22_grp", "gpio0_23_grp";
911 }; 897 };
912 898
913 conf-sw { 899 conf-sw {
914 groups = "gpio0_22_grp 900 groups = "gpio0_22_grp", "gpio0_23_grp";
915 slew-rate = <SLEW_RATE 901 slew-rate = <SLEW_RATE_SLOW>;
916 power-source = <IO_STA 902 power-source = <IO_STANDARD_LVCMOS18>;
917 }; 903 };
918 904
919 mux-msp { 905 mux-msp {
920 function = "gpio0"; 906 function = "gpio0";
921 groups = "gpio0_13_grp 907 groups = "gpio0_13_grp", "gpio0_38_grp";
922 }; 908 };
923 909
924 conf-msp { 910 conf-msp {
925 groups = "gpio0_13_grp 911 groups = "gpio0_13_grp", "gpio0_38_grp";
926 slew-rate = <SLEW_RATE 912 slew-rate = <SLEW_RATE_SLOW>;
927 power-source = <IO_STA 913 power-source = <IO_STANDARD_LVCMOS18>;
928 }; 914 };
929 915
930 conf-pull-up { 916 conf-pull-up {
931 pins = "MIO22", "MIO23 917 pins = "MIO22", "MIO23";
932 bias-pull-up; 918 bias-pull-up;
933 }; 919 };
934 920
935 conf-pull-none { 921 conf-pull-none {
936 pins = "MIO13", "MIO38 922 pins = "MIO13", "MIO38";
937 bias-disable; 923 bias-disable;
938 }; 924 };
939 }; 925 };
940 }; 926 };
941 927
942 &pcie { 928 &pcie {
943 status = "okay"; 929 status = "okay";
944 phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; <<
945 }; 930 };
946 931
947 &psgtr { 932 &psgtr {
948 status = "okay"; 933 status = "okay";
949 /* pcie, sata, usb3, dp */ 934 /* pcie, sata, usb3, dp */
950 clocks = <&si5341 0 5>, <&si5341 0 3>, 935 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
951 clock-names = "ref0", "ref1", "ref2", 936 clock-names = "ref0", "ref1", "ref2", "ref3";
952 }; 937 };
953 938
954 &qspi { 939 &qspi {
955 status = "okay"; 940 status = "okay";
956 flash@0 { 941 flash@0 {
957 compatible = "m25p80", "jedec, 942 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
958 #address-cells = <1>; 943 #address-cells = <1>;
959 #size-cells = <1>; 944 #size-cells = <1>;
960 reg = <0x0>; 945 reg = <0x0>;
961 spi-tx-bus-width = <4>; !! 946 spi-tx-bus-width = <1>;
962 spi-rx-bus-width = <4>; /* FIX 947 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
963 spi-max-frequency = <108000000 948 spi-max-frequency = <108000000>; /* Based on DC1 spec */
964 }; 949 };
965 }; 950 };
966 951
967 &rtc { 952 &rtc {
968 status = "okay"; 953 status = "okay";
969 }; 954 };
970 955
971 &sata { 956 &sata {
972 status = "okay"; 957 status = "okay";
973 /* SATA OOB timing settings */ 958 /* SATA OOB timing settings */
974 ceva,p0-cominit-params = /bits/ 8 <0x1 959 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
975 ceva,p0-comwake-params = /bits/ 8 <0x0 960 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
976 ceva,p0-burst-params = /bits/ 8 <0x13 961 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
977 ceva,p0-retry-params = /bits/ 16 <0x96 962 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
978 ceva,p1-cominit-params = /bits/ 8 <0x1 963 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
979 ceva,p1-comwake-params = /bits/ 8 <0x0 964 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
980 ceva,p1-burst-params = /bits/ 8 <0x13 965 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
981 ceva,p1-retry-params = /bits/ 16 <0x96 966 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
982 phy-names = "sata-phy"; 967 phy-names = "sata-phy";
983 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 968 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
984 }; 969 };
985 970
986 /* SD1 with level shifter */ 971 /* SD1 with level shifter */
987 &sdhci1 { 972 &sdhci1 {
988 status = "okay"; 973 status = "okay";
989 /* 974 /*
990 * 1.0 revision has level shifter and 975 * 1.0 revision has level shifter and this property should be
991 * removed for supporting UHS mode 976 * removed for supporting UHS mode
992 */ 977 */
993 no-1-8-v; 978 no-1-8-v;
994 pinctrl-names = "default"; 979 pinctrl-names = "default";
995 pinctrl-0 = <&pinctrl_sdhci1_default>; 980 pinctrl-0 = <&pinctrl_sdhci1_default>;
996 xlnx,mio-bank = <1>; 981 xlnx,mio-bank = <1>;
997 }; 982 };
998 983
999 &uart0 { 984 &uart0 {
1000 status = "okay"; 985 status = "okay";
1001 pinctrl-names = "default"; 986 pinctrl-names = "default";
1002 pinctrl-0 = <&pinctrl_uart0_default>; 987 pinctrl-0 = <&pinctrl_uart0_default>;
1003 }; 988 };
1004 989
1005 &uart1 { 990 &uart1 {
1006 status = "okay"; 991 status = "okay";
1007 pinctrl-names = "default"; 992 pinctrl-names = "default";
1008 pinctrl-0 = <&pinctrl_uart1_default>; 993 pinctrl-0 = <&pinctrl_uart1_default>;
1009 }; 994 };
1010 995
1011 /* ULPI SMSC USB3320 */ 996 /* ULPI SMSC USB3320 */
1012 &usb0 { 997 &usb0 {
1013 status = "okay"; 998 status = "okay";
1014 pinctrl-names = "default"; 999 pinctrl-names = "default";
1015 pinctrl-0 = <&pinctrl_usb0_default>; 1000 pinctrl-0 = <&pinctrl_usb0_default>;
1016 phy-names = "usb3-phy"; 1001 phy-names = "usb3-phy";
1017 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 1002 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1018 }; 1003 };
1019 1004
1020 &dwc3_0 { 1005 &dwc3_0 {
1021 status = "okay"; 1006 status = "okay";
1022 dr_mode = "host"; 1007 dr_mode = "host";
1023 snps,usb3_lpm_capable; 1008 snps,usb3_lpm_capable;
1024 maximum-speed = "super-speed"; 1009 maximum-speed = "super-speed";
1025 }; 1010 };
1026 1011
1027 &watchdog0 { 1012 &watchdog0 {
1028 status = "okay"; <<
1029 }; <<
1030 <<
1031 &xilinx_ams { <<
1032 status = "okay"; <<
1033 }; <<
1034 <<
1035 &ams_ps { <<
1036 status = "okay"; <<
1037 }; <<
1038 <<
1039 &ams_pl { <<
1040 status = "okay"; 1013 status = "okay";
1041 }; 1014 };
1042 1015
1043 &zynqmp_dpdma { 1016 &zynqmp_dpdma {
1044 status = "okay"; 1017 status = "okay";
1045 }; 1018 };
1046 1019
1047 &zynqmp_dpsub { 1020 &zynqmp_dpsub {
1048 status = "okay"; 1021 status = "okay";
1049 phy-names = "dp-phy0"; 1022 phy-names = "dp-phy0";
1050 phys = <&psgtr 1 PHY_TYPE_DP 0 3>; 1023 phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
1051 }; 1024 };
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