1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Copyright (c) 2014 Samsung Electronics Co.,
4 * Author: Chanwoo Choi <cw00.choi@samsung.com
5 */
6
7 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
8 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H
9
10 /* CMU_TOP */
11 #define CLK_FOUT_ISP_PLL 1
12 #define CLK_FOUT_AUD_PLL 2
13
14 #define CLK_MOUT_AUD_PLL 10
15 #define CLK_MOUT_ISP_PLL 11
16 #define CLK_MOUT_AUD_PLL_USER_T 12
17 #define CLK_MOUT_MPHY_PLL_USER 13
18 #define CLK_MOUT_MFC_PLL_USER 14
19 #define CLK_MOUT_BUS_PLL_USER 15
20 #define CLK_MOUT_ACLK_HEVC_400 16
21 #define CLK_MOUT_ACLK_CAM1_333 17
22 #define CLK_MOUT_ACLK_CAM1_552_B 18
23 #define CLK_MOUT_ACLK_CAM1_552_A 19
24 #define CLK_MOUT_ACLK_ISP_DIS_400 20
25 #define CLK_MOUT_ACLK_ISP_400 21
26 #define CLK_MOUT_ACLK_BUS0_400 22
27 #define CLK_MOUT_ACLK_MSCL_400_B 23
28 #define CLK_MOUT_ACLK_MSCL_400_A 24
29 #define CLK_MOUT_ACLK_GSCL_333 25
30 #define CLK_MOUT_ACLK_G2D_400_B 26
31 #define CLK_MOUT_ACLK_G2D_400_A 27
32 #define CLK_MOUT_SCLK_JPEG_C 28
33 #define CLK_MOUT_SCLK_JPEG_B 29
34 #define CLK_MOUT_SCLK_JPEG_A 30
35 #define CLK_MOUT_SCLK_MMC2_B 31
36 #define CLK_MOUT_SCLK_MMC2_A 32
37 #define CLK_MOUT_SCLK_MMC1_B 33
38 #define CLK_MOUT_SCLK_MMC1_A 34
39 #define CLK_MOUT_SCLK_MMC0_D 35
40 #define CLK_MOUT_SCLK_MMC0_C 36
41 #define CLK_MOUT_SCLK_MMC0_B 37
42 #define CLK_MOUT_SCLK_MMC0_A 38
43 #define CLK_MOUT_SCLK_SPI4 39
44 #define CLK_MOUT_SCLK_SPI3 40
45 #define CLK_MOUT_SCLK_UART2 41
46 #define CLK_MOUT_SCLK_UART1 42
47 #define CLK_MOUT_SCLK_UART0 43
48 #define CLK_MOUT_SCLK_SPI2 44
49 #define CLK_MOUT_SCLK_SPI1 45
50 #define CLK_MOUT_SCLK_SPI0 46
51 #define CLK_MOUT_ACLK_MFC_400_C 47
52 #define CLK_MOUT_ACLK_MFC_400_B 48
53 #define CLK_MOUT_ACLK_MFC_400_A 49
54 #define CLK_MOUT_SCLK_ISP_SENSOR2 50
55 #define CLK_MOUT_SCLK_ISP_SENSOR1 51
56 #define CLK_MOUT_SCLK_ISP_SENSOR0 52
57 #define CLK_MOUT_SCLK_ISP_UART 53
58 #define CLK_MOUT_SCLK_ISP_SPI1 54
59 #define CLK_MOUT_SCLK_ISP_SPI0 55
60 #define CLK_MOUT_SCLK_PCIE_100 56
61 #define CLK_MOUT_SCLK_UFSUNIPRO 57
62 #define CLK_MOUT_SCLK_USBHOST30 58
63 #define CLK_MOUT_SCLK_USBDRD30 59
64 #define CLK_MOUT_SCLK_SLIMBUS 60
65 #define CLK_MOUT_SCLK_SPDIF 61
66 #define CLK_MOUT_SCLK_AUDIO1 62
67 #define CLK_MOUT_SCLK_AUDIO0 63
68 #define CLK_MOUT_SCLK_HDMI_SPDIF 64
69
70 #define CLK_DIV_ACLK_FSYS_200 100
71 #define CLK_DIV_ACLK_IMEM_SSSX_266 101
72 #define CLK_DIV_ACLK_IMEM_200 102
73 #define CLK_DIV_ACLK_IMEM_266 103
74 #define CLK_DIV_ACLK_PERIC_66_B 104
75 #define CLK_DIV_ACLK_PERIC_66_A 105
76 #define CLK_DIV_ACLK_PERIS_66_B 106
77 #define CLK_DIV_ACLK_PERIS_66_A 107
78 #define CLK_DIV_SCLK_MMC1_B 108
79 #define CLK_DIV_SCLK_MMC1_A 109
80 #define CLK_DIV_SCLK_MMC0_B 110
81 #define CLK_DIV_SCLK_MMC0_A 111
82 #define CLK_DIV_SCLK_MMC2_B 112
83 #define CLK_DIV_SCLK_MMC2_A 113
84 #define CLK_DIV_SCLK_SPI1_B 114
85 #define CLK_DIV_SCLK_SPI1_A 115
86 #define CLK_DIV_SCLK_SPI0_B 116
87 #define CLK_DIV_SCLK_SPI0_A 117
88 #define CLK_DIV_SCLK_SPI2_B 118
89 #define CLK_DIV_SCLK_SPI2_A 119
90 #define CLK_DIV_SCLK_UART2 120
91 #define CLK_DIV_SCLK_UART1 121
92 #define CLK_DIV_SCLK_UART0 122
93 #define CLK_DIV_SCLK_SPI4_B 123
94 #define CLK_DIV_SCLK_SPI4_A 124
95 #define CLK_DIV_SCLK_SPI3_B 125
96 #define CLK_DIV_SCLK_SPI3_A 126
97 #define CLK_DIV_SCLK_I2S1 127
98 #define CLK_DIV_SCLK_PCM1 128
99 #define CLK_DIV_SCLK_AUDIO1 129
100 #define CLK_DIV_SCLK_AUDIO0 130
101 #define CLK_DIV_ACLK_GSCL_111 131
102 #define CLK_DIV_ACLK_GSCL_333 132
103 #define CLK_DIV_ACLK_HEVC_400 133
104 #define CLK_DIV_ACLK_MFC_400 134
105 #define CLK_DIV_ACLK_G2D_266 135
106 #define CLK_DIV_ACLK_G2D_400 136
107 #define CLK_DIV_ACLK_G3D_400 137
108 #define CLK_DIV_ACLK_BUS0_400 138
109 #define CLK_DIV_ACLK_BUS1_400 139
110 #define CLK_DIV_SCLK_PCIE_100 140
111 #define CLK_DIV_SCLK_USBHOST30 141
112 #define CLK_DIV_SCLK_UFSUNIPRO 142
113 #define CLK_DIV_SCLK_USBDRD30 143
114 #define CLK_DIV_SCLK_JPEG 144
115 #define CLK_DIV_ACLK_MSCL_400 145
116 #define CLK_DIV_ACLK_ISP_DIS_400 146
117 #define CLK_DIV_ACLK_ISP_400 147
118 #define CLK_DIV_ACLK_CAM0_333 148
119 #define CLK_DIV_ACLK_CAM0_400 149
120 #define CLK_DIV_ACLK_CAM0_552 150
121 #define CLK_DIV_ACLK_CAM1_333 151
122 #define CLK_DIV_ACLK_CAM1_400 152
123 #define CLK_DIV_ACLK_CAM1_552 153
124 #define CLK_DIV_SCLK_ISP_UART 154
125 #define CLK_DIV_SCLK_ISP_SPI1_B 155
126 #define CLK_DIV_SCLK_ISP_SPI1_A 156
127 #define CLK_DIV_SCLK_ISP_SPI0_B 157
128 #define CLK_DIV_SCLK_ISP_SPI0_A 158
129 #define CLK_DIV_SCLK_ISP_SENSOR2_B 159
130 #define CLK_DIV_SCLK_ISP_SENSOR2_A 160
131 #define CLK_DIV_SCLK_ISP_SENSOR1_B 161
132 #define CLK_DIV_SCLK_ISP_SENSOR1_A 162
133 #define CLK_DIV_SCLK_ISP_SENSOR0_B 163
134 #define CLK_DIV_SCLK_ISP_SENSOR0_A 164
135
136 #define CLK_ACLK_PERIC_66 200
137 #define CLK_ACLK_PERIS_66 201
138 #define CLK_ACLK_FSYS_200 202
139 #define CLK_SCLK_MMC2_FSYS 203
140 #define CLK_SCLK_MMC1_FSYS 204
141 #define CLK_SCLK_MMC0_FSYS 205
142 #define CLK_SCLK_SPI4_PERIC 206
143 #define CLK_SCLK_SPI3_PERIC 207
144 #define CLK_SCLK_UART2_PERIC 208
145 #define CLK_SCLK_UART1_PERIC 209
146 #define CLK_SCLK_UART0_PERIC 210
147 #define CLK_SCLK_SPI2_PERIC 211
148 #define CLK_SCLK_SPI1_PERIC 212
149 #define CLK_SCLK_SPI0_PERIC 213
150 #define CLK_SCLK_SPDIF_PERIC 214
151 #define CLK_SCLK_I2S1_PERIC 215
152 #define CLK_SCLK_PCM1_PERIC 216
153 #define CLK_SCLK_SLIMBUS 217
154 #define CLK_SCLK_AUDIO1 218
155 #define CLK_SCLK_AUDIO0 219
156 #define CLK_ACLK_G2D_266 220
157 #define CLK_ACLK_G2D_400 221
158 #define CLK_ACLK_G3D_400 222
159 #define CLK_ACLK_IMEM_SSSX_266 223
160 #define CLK_ACLK_BUS0_400 224
161 #define CLK_ACLK_BUS1_400 225
162 #define CLK_ACLK_IMEM_200 226
163 #define CLK_ACLK_IMEM_266 227
164 #define CLK_SCLK_PCIE_100_FSYS 228
165 #define CLK_SCLK_UFSUNIPRO_FSYS 229
166 #define CLK_SCLK_USBHOST30_FSYS 230
167 #define CLK_SCLK_USBDRD30_FSYS 231
168 #define CLK_ACLK_GSCL_111 232
169 #define CLK_ACLK_GSCL_333 233
170 #define CLK_SCLK_JPEG_MSCL 234
171 #define CLK_ACLK_MSCL_400 235
172 #define CLK_ACLK_MFC_400 236
173 #define CLK_ACLK_HEVC_400 237
174 #define CLK_ACLK_ISP_DIS_400 238
175 #define CLK_ACLK_ISP_400 239
176 #define CLK_ACLK_CAM0_333 240
177 #define CLK_ACLK_CAM0_400 241
178 #define CLK_ACLK_CAM0_552 242
179 #define CLK_ACLK_CAM1_333 243
180 #define CLK_ACLK_CAM1_400 244
181 #define CLK_ACLK_CAM1_552 245
182 #define CLK_SCLK_ISP_SENSOR2 246
183 #define CLK_SCLK_ISP_SENSOR1 247
184 #define CLK_SCLK_ISP_SENSOR0 248
185 #define CLK_SCLK_ISP_MCTADC_CAM1 249
186 #define CLK_SCLK_ISP_UART_CAM1 250
187 #define CLK_SCLK_ISP_SPI1_CAM1 251
188 #define CLK_SCLK_ISP_SPI0_CAM1 252
189 #define CLK_SCLK_HDMI_SPDIF_DISP 253
190
191 /* CMU_CPIF */
192 #define CLK_FOUT_MPHY_PLL 1
193
194 #define CLK_MOUT_MPHY_PLL 2
195
196 #define CLK_DIV_SCLK_MPHY 10
197
198 #define CLK_SCLK_MPHY_PLL 11
199 #define CLK_SCLK_UFS_MPHY 11
200
201 /* CMU_MIF */
202 #define CLK_FOUT_MEM0_PLL 1
203 #define CLK_FOUT_MEM1_PLL 2
204 #define CLK_FOUT_BUS_PLL 3
205 #define CLK_FOUT_MFC_PLL 4
206 #define CLK_DOUT_MFC_PLL 5
207 #define CLK_DOUT_BUS_PLL 6
208 #define CLK_DOUT_MEM1_PLL 7
209 #define CLK_DOUT_MEM0_PLL 8
210
211 #define CLK_MOUT_MFC_PLL_DIV2 10
212 #define CLK_MOUT_BUS_PLL_DIV2 11
213 #define CLK_MOUT_MEM1_PLL_DIV2 12
214 #define CLK_MOUT_MEM0_PLL_DIV2 13
215 #define CLK_MOUT_MFC_PLL 14
216 #define CLK_MOUT_BUS_PLL 15
217 #define CLK_MOUT_MEM1_PLL 16
218 #define CLK_MOUT_MEM0_PLL 17
219 #define CLK_MOUT_CLK2X_PHY_C 18
220 #define CLK_MOUT_CLK2X_PHY_B 19
221 #define CLK_MOUT_CLK2X_PHY_A 20
222 #define CLK_MOUT_CLKM_PHY_C 21
223 #define CLK_MOUT_CLKM_PHY_B 22
224 #define CLK_MOUT_CLKM_PHY_A 23
225 #define CLK_MOUT_ACLK_MIFNM_200 24
226 #define CLK_MOUT_ACLK_MIFNM_400 25
227 #define CLK_MOUT_ACLK_DISP_333_B 26
228 #define CLK_MOUT_ACLK_DISP_333_A 27
229 #define CLK_MOUT_SCLK_DECON_VCLK_C 28
230 #define CLK_MOUT_SCLK_DECON_VCLK_B 29
231 #define CLK_MOUT_SCLK_DECON_VCLK_A 30
232 #define CLK_MOUT_SCLK_DECON_ECLK_C 31
233 #define CLK_MOUT_SCLK_DECON_ECLK_B 32
234 #define CLK_MOUT_SCLK_DECON_ECLK_A 33
235 #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34
236 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
237 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
238 #define CLK_MOUT_SCLK_DSD_C 37
239 #define CLK_MOUT_SCLK_DSD_B 38
240 #define CLK_MOUT_SCLK_DSD_A 39
241 #define CLK_MOUT_SCLK_DSIM0_C 40
242 #define CLK_MOUT_SCLK_DSIM0_B 41
243 #define CLK_MOUT_SCLK_DSIM0_A 42
244 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46
245 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47
246 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48
247 #define CLK_MOUT_SCLK_DSIM1_C 49
248 #define CLK_MOUT_SCLK_DSIM1_B 50
249 #define CLK_MOUT_SCLK_DSIM1_A 51
250
251 #define CLK_DIV_SCLK_HPM_MIF 55
252 #define CLK_DIV_ACLK_DREX1 56
253 #define CLK_DIV_ACLK_DREX0 57
254 #define CLK_DIV_CLK2XPHY 58
255 #define CLK_DIV_ACLK_MIF_266 59
256 #define CLK_DIV_ACLK_MIFND_133 60
257 #define CLK_DIV_ACLK_MIF_133 61
258 #define CLK_DIV_ACLK_MIFNM_200 62
259 #define CLK_DIV_ACLK_MIF_200 63
260 #define CLK_DIV_ACLK_MIF_400 64
261 #define CLK_DIV_ACLK_BUS2_400 65
262 #define CLK_DIV_ACLK_DISP_333 66
263 #define CLK_DIV_ACLK_CPIF_200 67
264 #define CLK_DIV_SCLK_DSIM1 68
265 #define CLK_DIV_SCLK_DECON_TV_VCLK 69
266 #define CLK_DIV_SCLK_DSIM0 70
267 #define CLK_DIV_SCLK_DSD 71
268 #define CLK_DIV_SCLK_DECON_TV_ECLK 72
269 #define CLK_DIV_SCLK_DECON_VCLK 73
270 #define CLK_DIV_SCLK_DECON_ECLK 74
271 #define CLK_DIV_MIF_PRE 75
272
273 #define CLK_CLK2X_PHY1 80
274 #define CLK_CLK2X_PHY0 81
275 #define CLK_CLKM_PHY1 82
276 #define CLK_CLKM_PHY0 83
277 #define CLK_RCLK_DREX1 84
278 #define CLK_RCLK_DREX0 85
279 #define CLK_ACLK_DREX1_TZ 86
280 #define CLK_ACLK_DREX0_TZ 87
281 #define CLK_ACLK_DREX1_PEREV 88
282 #define CLK_ACLK_DREX0_PEREV 89
283 #define CLK_ACLK_DREX1_MEMIF 90
284 #define CLK_ACLK_DREX0_MEMIF 91
285 #define CLK_ACLK_DREX1_SCH 92
286 #define CLK_ACLK_DREX0_SCH 93
287 #define CLK_ACLK_DREX1_BUSIF 94
288 #define CLK_ACLK_DREX0_BUSIF 95
289 #define CLK_ACLK_DREX1_BUSIF_RD 96
290 #define CLK_ACLK_DREX0_BUSIF_RD 97
291 #define CLK_ACLK_DREX1 98
292 #define CLK_ACLK_DREX0 99
293 #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100
294 #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101
295 #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102
296 #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103
297 #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104
298 #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105
299 #define CLK_ACLK_ASYNCAXIS_CP1 106
300 #define CLK_ACLK_ASYNCAXIM_CP1 107
301 #define CLK_ACLK_ASYNCAXIS_CP0 108
302 #define CLK_ACLK_ASYNCAXIM_CP0 109
303 #define CLK_ACLK_ASYNCAXIS_DREX1_3 110
304 #define CLK_ACLK_ASYNCAXIM_DREX1_3 111
305 #define CLK_ACLK_ASYNCAXIS_DREX1_1 112
306 #define CLK_ACLK_ASYNCAXIM_DREX1_1 113
307 #define CLK_ACLK_ASYNCAXIS_DREX1_0 114
308 #define CLK_ACLK_ASYNCAXIM_DREX1_0 115
309 #define CLK_ACLK_ASYNCAXIS_DREX0_3 116
310 #define CLK_ACLK_ASYNCAXIM_DREX0_3 117
311 #define CLK_ACLK_ASYNCAXIS_DREX0_1 118
312 #define CLK_ACLK_ASYNCAXIM_DREX0_1 119
313 #define CLK_ACLK_ASYNCAXIS_DREX0_0 120
314 #define CLK_ACLK_ASYNCAXIM_DREX0_0 121
315 #define CLK_ACLK_AHB2APB_MIF2P 122
316 #define CLK_ACLK_AHB2APB_MIF1P 123
317 #define CLK_ACLK_AHB2APB_MIF0P 124
318 #define CLK_ACLK_IXIU_CCI 125
319 #define CLK_ACLK_XIU_MIFSFRX 126
320 #define CLK_ACLK_MIFNP_133 127
321 #define CLK_ACLK_MIFNM_200 128
322 #define CLK_ACLK_MIFND_133 129
323 #define CLK_ACLK_MIFND_400 130
324 #define CLK_ACLK_CCI 131
325 #define CLK_ACLK_MIFND_266 132
326 #define CLK_ACLK_PPMU_DREX1S3 133
327 #define CLK_ACLK_PPMU_DREX1S1 134
328 #define CLK_ACLK_PPMU_DREX1S0 135
329 #define CLK_ACLK_PPMU_DREX0S3 136
330 #define CLK_ACLK_PPMU_DREX0S1 137
331 #define CLK_ACLK_PPMU_DREX0S0 138
332 #define CLK_ACLK_BTS_APOLLO 139
333 #define CLK_ACLK_BTS_ATLAS 140
334 #define CLK_ACLK_ACE_SEL_APOLL 141
335 #define CLK_ACLK_ACE_SEL_ATLAS 142
336 #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143
337 #define CLK_ACLK_AXIUS_ATLAS_CCI 144
338 #define CLK_ACLK_AXISYNCDNS_CCI 145
339 #define CLK_ACLK_AXISYNCDN_CCI 146
340 #define CLK_ACLK_AXISYNCDN_NOC_D 147
341 #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148
342 #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149
343 #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150
344 #define CLK_ACLK_BUS2_400 151
345 #define CLK_ACLK_DISP_333 152
346 #define CLK_ACLK_CPIF_200 153
347 #define CLK_PCLK_PPMU_DREX1S3 154
348 #define CLK_PCLK_PPMU_DREX1S1 155
349 #define CLK_PCLK_PPMU_DREX1S0 156
350 #define CLK_PCLK_PPMU_DREX0S3 157
351 #define CLK_PCLK_PPMU_DREX0S1 158
352 #define CLK_PCLK_PPMU_DREX0S0 159
353 #define CLK_PCLK_BTS_APOLLO 160
354 #define CLK_PCLK_BTS_ATLAS 161
355 #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162
356 #define CLK_PCLK_ASYNCAXI_CP1 163
357 #define CLK_PCLK_ASYNCAXI_CP0 164
358 #define CLK_PCLK_ASYNCAXI_DREX1_3 165
359 #define CLK_PCLK_ASYNCAXI_DREX1_1 166
360 #define CLK_PCLK_ASYNCAXI_DREX1_0 167
361 #define CLK_PCLK_ASYNCAXI_DREX0_3 168
362 #define CLK_PCLK_ASYNCAXI_DREX0_1 169
363 #define CLK_PCLK_ASYNCAXI_DREX0_0 170
364 #define CLK_PCLK_MIFSRVND_133 171
365 #define CLK_PCLK_PMU_MIF 172
366 #define CLK_PCLK_SYSREG_MIF 173
367 #define CLK_PCLK_GPIO_ALIVE 174
368 #define CLK_PCLK_ABB 175
369 #define CLK_PCLK_PMU_APBIF 176
370 #define CLK_PCLK_DDR_PHY1 177
371 #define CLK_PCLK_DREX1 178
372 #define CLK_PCLK_DDR_PHY0 179
373 #define CLK_PCLK_DREX0 180
374 #define CLK_PCLK_DREX0_TZ 181
375 #define CLK_PCLK_DREX1_TZ 182
376 #define CLK_PCLK_MONOTONIC_CNT 183
377 #define CLK_PCLK_RTC 184
378 #define CLK_SCLK_DSIM1_DISP 185
379 #define CLK_SCLK_DECON_TV_VCLK_DISP 186
380 #define CLK_SCLK_FREQ_DET_BUS_PLL 187
381 #define CLK_SCLK_FREQ_DET_MFC_PLL 188
382 #define CLK_SCLK_FREQ_DET_MEM0_PLL 189
383 #define CLK_SCLK_FREQ_DET_MEM1_PLL 190
384 #define CLK_SCLK_DSIM0_DISP 191
385 #define CLK_SCLK_DSD_DISP 192
386 #define CLK_SCLK_DECON_TV_ECLK_DISP 193
387 #define CLK_SCLK_DECON_VCLK_DISP 194
388 #define CLK_SCLK_DECON_ECLK_DISP 195
389 #define CLK_SCLK_HPM_MIF 196
390 #define CLK_SCLK_MFC_PLL 197
391 #define CLK_SCLK_BUS_PLL 198
392 #define CLK_SCLK_BUS_PLL_APOLLO 199
393 #define CLK_SCLK_BUS_PLL_ATLAS 200
394
395 /* CMU_PERIC */
396 #define CLK_PCLK_SPI2 1
397 #define CLK_PCLK_SPI1 2
398 #define CLK_PCLK_SPI0 3
399 #define CLK_PCLK_UART2 4
400 #define CLK_PCLK_UART1 5
401 #define CLK_PCLK_UART0 6
402 #define CLK_PCLK_HSI2C3 7
403 #define CLK_PCLK_HSI2C2 8
404 #define CLK_PCLK_HSI2C1 9
405 #define CLK_PCLK_HSI2C0 10
406 #define CLK_PCLK_I2C7 11
407 #define CLK_PCLK_I2C6 12
408 #define CLK_PCLK_I2C5 13
409 #define CLK_PCLK_I2C4 14
410 #define CLK_PCLK_I2C3 15
411 #define CLK_PCLK_I2C2 16
412 #define CLK_PCLK_I2C1 17
413 #define CLK_PCLK_I2C0 18
414 #define CLK_PCLK_SPI4 19
415 #define CLK_PCLK_SPI3 20
416 #define CLK_PCLK_HSI2C11 21
417 #define CLK_PCLK_HSI2C10 22
418 #define CLK_PCLK_HSI2C9 23
419 #define CLK_PCLK_HSI2C8 24
420 #define CLK_PCLK_HSI2C7 25
421 #define CLK_PCLK_HSI2C6 26
422 #define CLK_PCLK_HSI2C5 27
423 #define CLK_PCLK_HSI2C4 28
424 #define CLK_SCLK_SPI4 29
425 #define CLK_SCLK_SPI3 30
426 #define CLK_SCLK_SPI2 31
427 #define CLK_SCLK_SPI1 32
428 #define CLK_SCLK_SPI0 33
429 #define CLK_SCLK_UART2 34
430 #define CLK_SCLK_UART1 35
431 #define CLK_SCLK_UART0 36
432 #define CLK_ACLK_AHB2APB_PERIC2P 37
433 #define CLK_ACLK_AHB2APB_PERIC1P 38
434 #define CLK_ACLK_AHB2APB_PERIC0P 39
435 #define CLK_ACLK_PERICNP_66 40
436 #define CLK_PCLK_SCI 41
437 #define CLK_PCLK_GPIO_FINGER 42
438 #define CLK_PCLK_GPIO_ESE 43
439 #define CLK_PCLK_PWM 44
440 #define CLK_PCLK_SPDIF 45
441 #define CLK_PCLK_PCM1 46
442 #define CLK_PCLK_I2S1 47
443 #define CLK_PCLK_ADCIF 48
444 #define CLK_PCLK_GPIO_TOUCH 49
445 #define CLK_PCLK_GPIO_NFC 50
446 #define CLK_PCLK_GPIO_PERIC 51
447 #define CLK_PCLK_PMU_PERIC 52
448 #define CLK_PCLK_SYSREG_PERIC 53
449 #define CLK_SCLK_IOCLK_SPI4 54
450 #define CLK_SCLK_IOCLK_SPI3 55
451 #define CLK_SCLK_SCI 56
452 #define CLK_SCLK_SC_IN 57
453 #define CLK_SCLK_PWM 58
454 #define CLK_SCLK_IOCLK_SPI2 59
455 #define CLK_SCLK_IOCLK_SPI1 60
456 #define CLK_SCLK_IOCLK_SPI0 61
457 #define CLK_SCLK_IOCLK_I2S1_BCLK 62
458 #define CLK_SCLK_SPDIF 63
459 #define CLK_SCLK_PCM1 64
460 #define CLK_SCLK_I2S1 65
461
462 #define CLK_DIV_SCLK_SCI 70
463 #define CLK_DIV_SCLK_SC_IN 71
464
465 /* CMU_PERIS */
466 #define CLK_PCLK_HPM_APBIF 1
467 #define CLK_PCLK_TMU1_APBIF 2
468 #define CLK_PCLK_TMU0_APBIF 3
469 #define CLK_PCLK_PMU_PERIS 4
470 #define CLK_PCLK_SYSREG_PERIS 5
471 #define CLK_PCLK_CMU_TOP_APBIF 6
472 #define CLK_PCLK_WDT_APOLLO 7
473 #define CLK_PCLK_WDT_ATLAS 8
474 #define CLK_PCLK_MCT 9
475 #define CLK_PCLK_HDMI_CEC 10
476 #define CLK_ACLK_AHB2APB_PERIS1P 11
477 #define CLK_ACLK_AHB2APB_PERIS0P 12
478 #define CLK_ACLK_PERISNP_66 13
479 #define CLK_PCLK_TZPC12 14
480 #define CLK_PCLK_TZPC11 15
481 #define CLK_PCLK_TZPC10 16
482 #define CLK_PCLK_TZPC9 17
483 #define CLK_PCLK_TZPC8 18
484 #define CLK_PCLK_TZPC7 19
485 #define CLK_PCLK_TZPC6 20
486 #define CLK_PCLK_TZPC5 21
487 #define CLK_PCLK_TZPC4 22
488 #define CLK_PCLK_TZPC3 23
489 #define CLK_PCLK_TZPC2 24
490 #define CLK_PCLK_TZPC1 25
491 #define CLK_PCLK_TZPC0 26
492 #define CLK_PCLK_SECKEY_APBIF 27
493 #define CLK_PCLK_CHIPID_APBIF 28
494 #define CLK_PCLK_TOPRTC 29
495 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30
496 #define CLK_PCLK_ANTIRBK_CNT_APBIF 31
497 #define CLK_PCLK_OTP_CON_APBIF 32
498 #define CLK_SCLK_ASV_TB 33
499 #define CLK_SCLK_TMU1 34
500 #define CLK_SCLK_TMU0 35
501 #define CLK_SCLK_SECKEY 36
502 #define CLK_SCLK_CHIPID 37
503 #define CLK_SCLK_TOPRTC 38
504 #define CLK_SCLK_CUSTOM_EFUSE 39
505 #define CLK_SCLK_ANTIRBK_CNT 40
506 #define CLK_SCLK_OTP_CON 41
507
508 /* CMU_FSYS */
509 #define CLK_MOUT_ACLK_FSYS_200_USER 1
510 #define CLK_MOUT_SCLK_MMC2_USER 2
511 #define CLK_MOUT_SCLK_MMC1_USER 3
512 #define CLK_MOUT_SCLK_MMC0_USER 4
513 #define CLK_MOUT_SCLK_UFS_MPHY_USER 5
514 #define CLK_MOUT_SCLK_PCIE_100_USER 6
515 #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7
516 #define CLK_MOUT_SCLK_USBHOST30_USER 8
517 #define CLK_MOUT_SCLK_USBDRD30_USER 9
518 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE
519 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYC
520 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_US
521 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOH
522 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK
523 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREE
524 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_P
525 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLO
526 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER
527 #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER
528 #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER
529 #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER
530 #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER
531 #define CLK_MOUT_SCLK_MPHY
532
533 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PH
534 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_P
535 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_
536 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK
537 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY
538 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY
539 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PH
540 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY
541 #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY
542 #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY
543 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY
544 #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY
545 #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY
546
547 #define CLK_ACLK_PCIE 50
548 #define CLK_ACLK_PDMA1 51
549 #define CLK_ACLK_TSI 52
550 #define CLK_ACLK_MMC2 53
551 #define CLK_ACLK_MMC1 54
552 #define CLK_ACLK_MMC0 55
553 #define CLK_ACLK_UFS 56
554 #define CLK_ACLK_USBHOST20 57
555 #define CLK_ACLK_USBHOST30 58
556 #define CLK_ACLK_USBDRD30 59
557 #define CLK_ACLK_PDMA0 60
558 #define CLK_SCLK_MMC2 61
559 #define CLK_SCLK_MMC1 62
560 #define CLK_SCLK_MMC0 63
561 #define CLK_PDMA1 64
562 #define CLK_PDMA0 65
563 #define CLK_ACLK_XIU_FSYSPX 66
564 #define CLK_ACLK_AHB_USBLINKH1 67
565 #define CLK_ACLK_SMMU_PDMA1 68
566 #define CLK_ACLK_BTS_PCIE 69
567 #define CLK_ACLK_AXIUS_PDMA1 70
568 #define CLK_ACLK_SMMU_PDMA0 71
569 #define CLK_ACLK_BTS_UFS 72
570 #define CLK_ACLK_BTS_USBHOST30 73
571 #define CLK_ACLK_BTS_USBDRD30 74
572 #define CLK_ACLK_AXIUS_PDMA0 75
573 #define CLK_ACLK_AXIUS_USBHS 76
574 #define CLK_ACLK_AXIUS_FSYSSX 77
575 #define CLK_ACLK_AHB2APB_FSYSP 78
576 #define CLK_ACLK_AHB2AXI_USBHS 79
577 #define CLK_ACLK_AHB_USBLINKH0 80
578 #define CLK_ACLK_AHB_USBHS 81
579 #define CLK_ACLK_AHB_FSYSH 82
580 #define CLK_ACLK_XIU_FSYSX 83
581 #define CLK_ACLK_XIU_FSYSSX 84
582 #define CLK_ACLK_FSYSNP_200 85
583 #define CLK_ACLK_FSYSND_200 86
584 #define CLK_PCLK_PCIE_CTRL 87
585 #define CLK_PCLK_SMMU_PDMA1 88
586 #define CLK_PCLK_PCIE_PHY 89
587 #define CLK_PCLK_BTS_PCIE 90
588 #define CLK_PCLK_SMMU_PDMA0 91
589 #define CLK_PCLK_BTS_UFS 92
590 #define CLK_PCLK_BTS_USBHOST30 93
591 #define CLK_PCLK_BTS_USBDRD30 94
592 #define CLK_PCLK_GPIO_FSYS 95
593 #define CLK_PCLK_PMU_FSYS 96
594 #define CLK_PCLK_SYSREG_FSYS 97
595 #define CLK_SCLK_PCIE_100 98
596 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK
597 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK
598 #define CLK_PHYCLK_UFS_RX1_SYMBOL
599 #define CLK_PHYCLK_UFS_RX0_SYMBOL
600 #define CLK_PHYCLK_UFS_TX1_SYMBOL
601 #define CLK_PHYCLK_UFS_TX0_SYMBOL
602 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1
603 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI
604 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK
605 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK
606 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK
607 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK
608 #define CLK_SCLK_MPHY 111
609 #define CLK_SCLK_UFSUNIPRO 112
610 #define CLK_SCLK_USBHOST30 113
611 #define CLK_SCLK_USBDRD30 114
612 #define CLK_PCIE 115
613
614 /* CMU_G2D */
615 #define CLK_MUX_ACLK_G2D_266_USER 1
616 #define CLK_MUX_ACLK_G2D_400_USER 2
617
618 #define CLK_DIV_PCLK_G2D 3
619
620 #define CLK_ACLK_SMMU_MDMA1 4
621 #define CLK_ACLK_BTS_MDMA1 5
622 #define CLK_ACLK_BTS_G2D 6
623 #define CLK_ACLK_ALB_G2D 7
624 #define CLK_ACLK_AXIUS_G2DX 8
625 #define CLK_ACLK_ASYNCAXI_SYSX 9
626 #define CLK_ACLK_AHB2APB_G2D1P 10
627 #define CLK_ACLK_AHB2APB_G2D0P 11
628 #define CLK_ACLK_XIU_G2DX 12
629 #define CLK_ACLK_G2DNP_133 13
630 #define CLK_ACLK_G2DND_400 14
631 #define CLK_ACLK_MDMA1 15
632 #define CLK_ACLK_G2D 16
633 #define CLK_ACLK_SMMU_G2D 17
634 #define CLK_PCLK_SMMU_MDMA1 18
635 #define CLK_PCLK_BTS_MDMA1 19
636 #define CLK_PCLK_BTS_G2D 20
637 #define CLK_PCLK_ALB_G2D 21
638 #define CLK_PCLK_ASYNCAXI_SYSX 22
639 #define CLK_PCLK_PMU_G2D 23
640 #define CLK_PCLK_SYSREG_G2D 24
641 #define CLK_PCLK_G2D 25
642 #define CLK_PCLK_SMMU_G2D 26
643
644 /* CMU_DISP */
645 #define CLK_FOUT_DISP_PLL
646
647 #define CLK_MOUT_DISP_PLL
648 #define CLK_MOUT_SCLK_DSIM1_USER
649 #define CLK_MOUT_SCLK_DSIM0_USER
650 #define CLK_MOUT_SCLK_DSD_USER
651 #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER
652 #define CLK_MOUT_SCLK_DECON_VCLK_USER
653 #define CLK_MOUT_SCLK_DECON_ECLK_USER
654 #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER
655 #define CLK_MOUT_ACLK_DISP_333_USER
656 #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_U
657 #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_US
658 #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_U
659 #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_US
660 #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER
661 #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USE
662 #define CLK_MOUT_SCLK_DSIM0
663 #define CLK_MOUT_SCLK_DECON_TV_ECLK
664 #define CLK_MOUT_SCLK_DECON_VCLK
665 #define CLK_MOUT_SCLK_DECON_ECLK
666 #define CLK_MOUT_SCLK_DSIM1_B_DISP
667 #define CLK_MOUT_SCLK_DSIM1_A_DISP
668 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP
669 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP
670 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP
671
672 #define CLK_DIV_SCLK_DSIM1_DISP
673 #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP
674 #define CLK_DIV_SCLK_DSIM0_DISP
675 #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP
676 #define CLK_DIV_SCLK_DECON_VCLK_DISP
677 #define CLK_DIV_SCLK_DECON_ECLK_DISP
678 #define CLK_DIV_PCLK_DISP
679
680 #define CLK_ACLK_DECON_TV
681 #define CLK_ACLK_DECON
682 #define CLK_ACLK_SMMU_TV1X
683 #define CLK_ACLK_SMMU_TV0X
684 #define CLK_ACLK_SMMU_DECON1X
685 #define CLK_ACLK_SMMU_DECON0X
686 #define CLK_ACLK_BTS_DECON_TV_M3
687 #define CLK_ACLK_BTS_DECON_TV_M2
688 #define CLK_ACLK_BTS_DECON_TV_M1
689 #define CLK_ACLK_BTS_DECON_TV_M0
690 #define CLK_ACLK_BTS_DECON_NM4
691 #define CLK_ACLK_BTS_DECON_NM3
692 #define CLK_ACLK_BTS_DECON_NM2
693 #define CLK_ACLK_BTS_DECON_NM1
694 #define CLK_ACLK_BTS_DECON_NM0
695 #define CLK_ACLK_AHB2APB_DISPSFR2P
696 #define CLK_ACLK_AHB2APB_DISPSFR1P
697 #define CLK_ACLK_AHB2APB_DISPSFR0P
698 #define CLK_ACLK_AHB_DISPH
699 #define CLK_ACLK_XIU_TV1X
700 #define CLK_ACLK_XIU_TV0X
701 #define CLK_ACLK_XIU_DECON1X
702 #define CLK_ACLK_XIU_DECON0X
703 #define CLK_ACLK_XIU_DISP1X
704 #define CLK_ACLK_XIU_DISPNP_100
705 #define CLK_ACLK_DISP1ND_333
706 #define CLK_ACLK_DISP0ND_333
707 #define CLK_PCLK_SMMU_TV1X
708 #define CLK_PCLK_SMMU_TV0X
709 #define CLK_PCLK_SMMU_DECON1X
710 #define CLK_PCLK_SMMU_DECON0X
711 #define CLK_PCLK_BTS_DECON_TV_M3
712 #define CLK_PCLK_BTS_DECON_TV_M2
713 #define CLK_PCLK_BTS_DECON_TV_M1
714 #define CLK_PCLK_BTS_DECON_TV_M0
715 #define CLK_PCLK_BTS_DECONM4
716 #define CLK_PCLK_BTS_DECONM3
717 #define CLK_PCLK_BTS_DECONM2
718 #define CLK_PCLK_BTS_DECONM1
719 #define CLK_PCLK_BTS_DECONM0
720 #define CLK_PCLK_MIC1
721 #define CLK_PCLK_PMU_DISP
722 #define CLK_PCLK_SYSREG_DISP
723 #define CLK_PCLK_HDMIPHY
724 #define CLK_PCLK_HDMI
725 #define CLK_PCLK_MIC0
726 #define CLK_PCLK_DSIM1
727 #define CLK_PCLK_DSIM0
728 #define CLK_PCLK_DECON_TV
729 #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8
730 #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0
731 #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1
732 #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1
733 #define CLK_SCLK_DSIM1
734 #define CLK_SCLK_DECON_TV_VCLK
735 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8
736 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0
737 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO
738 #define CLK_PHYCLK_HDMI_PIXEL
739 #define CLK_SCLK_RGB_VCLK_TO_SMIES
740 #define CLK_SCLK_FREQ_DET_DISP_PLL
741 #define CLK_SCLK_RGB_VCLK_TO_DSIM0
742 #define CLK_SCLK_RGB_VCLK_TO_MIC0
743 #define CLK_SCLK_DSD
744 #define CLK_SCLK_HDMI_SPDIF
745 #define CLK_SCLK_DSIM0
746 #define CLK_SCLK_DECON_TV_ECLK
747 #define CLK_SCLK_DECON_VCLK
748 #define CLK_SCLK_DECON_ECLK
749 #define CLK_SCLK_RGB_VCLK
750 #define CLK_SCLK_RGB_TV_VCLK
751
752 #define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY
753 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY
754
755 #define CLK_PCLK_DECON
756
757 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY
758 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY
759
760 /* CMU_AUD */
761 #define CLK_MOUT_AUD_PLL_USER
762 #define CLK_MOUT_SCLK_AUD_PCM
763 #define CLK_MOUT_SCLK_AUD_I2S
764
765 #define CLK_DIV_ATCLK_AUD
766 #define CLK_DIV_PCLK_DBG_AUD
767 #define CLK_DIV_ACLK_AUD
768 #define CLK_DIV_AUD_CA5
769 #define CLK_DIV_SCLK_AUD_SLIMBUS
770 #define CLK_DIV_SCLK_AUD_UART
771 #define CLK_DIV_SCLK_AUD_PCM
772 #define CLK_DIV_SCLK_AUD_I2S
773
774 #define CLK_ACLK_INTR_CTRL
775 #define CLK_ACLK_AXIDS2_LPASSP
776 #define CLK_ACLK_AXIDS1_LPASSP
777 #define CLK_ACLK_AXI2APB1_LPASSP
778 #define CLK_ACLK_AXI2APH_LPASSP
779 #define CLK_ACLK_SMMU_LPASSX
780 #define CLK_ACLK_AXIDS0_LPASSP
781 #define CLK_ACLK_AXI2APB0_LPASSP
782 #define CLK_ACLK_XIU_LPASSX
783 #define CLK_ACLK_AUDNP_133
784 #define CLK_ACLK_AUDND_133
785 #define CLK_ACLK_SRAMC
786 #define CLK_ACLK_DMAC
787 #define CLK_PCLK_WDT1
788 #define CLK_PCLK_WDT0
789 #define CLK_PCLK_SFR1
790 #define CLK_PCLK_SMMU_LPASSX
791 #define CLK_PCLK_GPIO_AUD
792 #define CLK_PCLK_PMU_AUD
793 #define CLK_PCLK_SYSREG_AUD
794 #define CLK_PCLK_AUD_SLIMBUS
795 #define CLK_PCLK_AUD_UART
796 #define CLK_PCLK_AUD_PCM
797 #define CLK_PCLK_AUD_I2S
798 #define CLK_PCLK_TIMER
799 #define CLK_PCLK_SFR0_CTRL
800 #define CLK_ATCLK_AUD
801 #define CLK_PCLK_DBG_AUD
802 #define CLK_SCLK_AUD_CA5
803 #define CLK_SCLK_JTAG_TCK
804 #define CLK_SCLK_SLIMBUS_CLKIN
805 #define CLK_SCLK_AUD_SLIMBUS
806 #define CLK_SCLK_AUD_UART
807 #define CLK_SCLK_AUD_PCM
808 #define CLK_SCLK_I2S_BCLK
809 #define CLK_SCLK_AUD_I2S
810
811 /* CMU_BUS{0|1|2} */
812 #define CLK_DIV_PCLK_BUS_133
813
814 #define CLK_ACLK_AHB2APB_BUSP
815 #define CLK_ACLK_BUSNP_133
816 #define CLK_ACLK_BUSND_400
817 #define CLK_PCLK_BUSSRVND_133
818 #define CLK_PCLK_PMU_BUS
819 #define CLK_PCLK_SYSREG_BUS
820
821 #define CLK_MOUT_ACLK_BUS2_400_USER
822 #define CLK_ACLK_BUS2BEND_400
823 #define CLK_ACLK_BUS2RTND_400
824
825 /* CMU_G3D */
826 #define CLK_FOUT_G3D_PLL
827
828 #define CLK_MOUT_ACLK_G3D_400
829 #define CLK_MOUT_G3D_PLL
830
831 #define CLK_DIV_SCLK_HPM_G3D
832 #define CLK_DIV_PCLK_G3D
833 #define CLK_DIV_ACLK_G3D
834 #define CLK_ACLK_BTS_G3D1
835 #define CLK_ACLK_BTS_G3D0
836 #define CLK_ACLK_ASYNCAPBS_G3D
837 #define CLK_ACLK_ASYNCAPBM_G3D
838 #define CLK_ACLK_AHB2APB_G3DP
839 #define CLK_ACLK_G3DNP_150
840 #define CLK_ACLK_G3DND_600
841 #define CLK_ACLK_G3D
842 #define CLK_PCLK_BTS_G3D1
843 #define CLK_PCLK_BTS_G3D0
844 #define CLK_PCLK_PMU_G3D
845 #define CLK_PCLK_SYSREG_G3D
846 #define CLK_SCLK_HPM_G3D
847
848 /* CMU_GSCL */
849 #define CLK_MOUT_ACLK_GSCL_111_USER
850 #define CLK_MOUT_ACLK_GSCL_333_USER
851
852 #define CLK_ACLK_BTS_GSCL2
853 #define CLK_ACLK_BTS_GSCL1
854 #define CLK_ACLK_BTS_GSCL0
855 #define CLK_ACLK_AHB2APB_GSCLP
856 #define CLK_ACLK_XIU_GSCLX
857 #define CLK_ACLK_GSCLNP_111
858 #define CLK_ACLK_GSCLRTND_333
859 #define CLK_ACLK_GSCLBEND_333
860 #define CLK_ACLK_GSD
861 #define CLK_ACLK_GSCL2
862 #define CLK_ACLK_GSCL1
863 #define CLK_ACLK_GSCL0
864 #define CLK_ACLK_SMMU_GSCL0
865 #define CLK_ACLK_SMMU_GSCL1
866 #define CLK_ACLK_SMMU_GSCL2
867 #define CLK_PCLK_BTS_GSCL2
868 #define CLK_PCLK_BTS_GSCL1
869 #define CLK_PCLK_BTS_GSCL0
870 #define CLK_PCLK_PMU_GSCL
871 #define CLK_PCLK_SYSREG_GSCL
872 #define CLK_PCLK_GSCL2
873 #define CLK_PCLK_GSCL1
874 #define CLK_PCLK_GSCL0
875 #define CLK_PCLK_SMMU_GSCL0
876 #define CLK_PCLK_SMMU_GSCL1
877 #define CLK_PCLK_SMMU_GSCL2
878
879 /* CMU_APOLLO */
880 #define CLK_FOUT_APOLLO_PLL
881
882 #define CLK_MOUT_APOLLO_PLL
883 #define CLK_MOUT_BUS_PLL_APOLLO_USER
884 #define CLK_MOUT_APOLLO
885
886 #define CLK_DIV_CNTCLK_APOLLO
887 #define CLK_DIV_PCLK_DBG_APOLLO
888 #define CLK_DIV_ATCLK_APOLLO
889 #define CLK_DIV_PCLK_APOLLO
890 #define CLK_DIV_ACLK_APOLLO
891 #define CLK_DIV_APOLLO2
892 #define CLK_DIV_APOLLO1
893 #define CLK_DIV_SCLK_HPM_APOLLO
894 #define CLK_DIV_APOLLO_PLL
895
896 #define CLK_ACLK_ATBDS_APOLLO_3
897 #define CLK_ACLK_ATBDS_APOLLO_2
898 #define CLK_ACLK_ATBDS_APOLLO_1
899 #define CLK_ACLK_ATBDS_APOLLO_0
900 #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS
901 #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS
902 #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS
903 #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS
904 #define CLK_ACLK_ASYNCACES_APOLLO_CCI
905 #define CLK_ACLK_AHB2APB_APOLLOP
906 #define CLK_ACLK_APOLLONP_200
907 #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO
908 #define CLK_PCLK_PMU_APOLLO
909 #define CLK_PCLK_SYSREG_APOLLO
910 #define CLK_CNTCLK_APOLLO
911 #define CLK_SCLK_HPM_APOLLO
912 #define CLK_SCLK_APOLLO
913
914 /* CMU_ATLAS */
915 #define CLK_FOUT_ATLAS_PLL
916
917 #define CLK_MOUT_ATLAS_PLL
918 #define CLK_MOUT_BUS_PLL_ATLAS_USER
919 #define CLK_MOUT_ATLAS
920
921 #define CLK_DIV_CNTCLK_ATLAS
922 #define CLK_DIV_PCLK_DBG_ATLAS
923 #define CLK_DIV_ATCLK_ATLASO
924 #define CLK_DIV_PCLK_ATLAS
925 #define CLK_DIV_ACLK_ATLAS
926 #define CLK_DIV_ATLAS2
927 #define CLK_DIV_ATLAS1
928 #define CLK_DIV_SCLK_HPM_ATLAS
929 #define CLK_DIV_ATLAS_PLL
930
931 #define CLK_ACLK_ATB_AUD_CSSYS
932 #define CLK_ACLK_ATB_APOLLO3_CSSYS
933 #define CLK_ACLK_ATB_APOLLO2_CSSYS
934 #define CLK_ACLK_ATB_APOLLO1_CSSYS
935 #define CLK_ACLK_ATB_APOLLO0_CSSYS
936 #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS
937 #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX
938 #define CLK_ACLK_ASYNCACES_ATLAS_CCI
939 #define CLK_ACLK_AHB2APB_ATLASP
940 #define CLK_ACLK_ATLASNP_200
941 #define CLK_PCLK_ASYNCAPB_AUD_CSSYS
942 #define CLK_PCLK_ASYNCAPB_ISP_CSSYS
943 #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS
944 #define CLK_PCLK_PMU_ATLAS
945 #define CLK_PCLK_SYSREG_ATLAS
946 #define CLK_PCLK_SECJTAG
947 #define CLK_CNTCLK_ATLAS
948 #define CLK_SCLK_FREQ_DET_ATLAS_PLL
949 #define CLK_SCLK_HPM_ATLAS
950 #define CLK_TRACECLK
951 #define CLK_CTMCLK
952 #define CLK_HCLK_CSSYS
953 #define CLK_PCLK_DBG_CSSYS
954 #define CLK_PCLK_DBG
955 #define CLK_ATCLK
956 #define CLK_SCLK_ATLAS
957
958 /* CMU_MSCL */
959 #define CLK_MOUT_SCLK_JPEG_USER
960 #define CLK_MOUT_ACLK_MSCL_400_USER
961 #define CLK_MOUT_SCLK_JPEG
962
963 #define CLK_DIV_PCLK_MSCL
964
965 #define CLK_ACLK_BTS_JPEG
966 #define CLK_ACLK_BTS_M2MSCALER1
967 #define CLK_ACLK_BTS_M2MSCALER0
968 #define CLK_ACLK_AHB2APB_MSCL0P
969 #define CLK_ACLK_XIU_MSCLX
970 #define CLK_ACLK_MSCLNP_100
971 #define CLK_ACLK_MSCLND_400
972 #define CLK_ACLK_JPEG
973 #define CLK_ACLK_M2MSCALER1
974 #define CLK_ACLK_M2MSCALER0
975 #define CLK_ACLK_SMMU_M2MSCALER0
976 #define CLK_ACLK_SMMU_M2MSCALER1
977 #define CLK_ACLK_SMMU_JPEG
978 #define CLK_PCLK_BTS_JPEG
979 #define CLK_PCLK_BTS_M2MSCALER1
980 #define CLK_PCLK_BTS_M2MSCALER0
981 #define CLK_PCLK_PMU_MSCL
982 #define CLK_PCLK_SYSREG_MSCL
983 #define CLK_PCLK_JPEG
984 #define CLK_PCLK_M2MSCALER1
985 #define CLK_PCLK_M2MSCALER0
986 #define CLK_PCLK_SMMU_M2MSCALER0
987 #define CLK_PCLK_SMMU_M2MSCALER1
988 #define CLK_PCLK_SMMU_JPEG
989 #define CLK_SCLK_JPEG
990
991 /* CMU_MFC */
992 #define CLK_MOUT_ACLK_MFC_400_USER
993
994 #define CLK_DIV_PCLK_MFC
995
996 #define CLK_ACLK_BTS_MFC_1
997 #define CLK_ACLK_BTS_MFC_0
998 #define CLK_ACLK_AHB2APB_MFCP
999 #define CLK_ACLK_XIU_MFCX
1000 #define CLK_ACLK_MFCNP_100
1001 #define CLK_ACLK_MFCND_400
1002 #define CLK_ACLK_MFC
1003 #define CLK_ACLK_SMMU_MFC_1
1004 #define CLK_ACLK_SMMU_MFC_0
1005 #define CLK_PCLK_BTS_MFC_1
1006 #define CLK_PCLK_BTS_MFC_0
1007 #define CLK_PCLK_PMU_MFC
1008 #define CLK_PCLK_SYSREG_MFC
1009 #define CLK_PCLK_MFC
1010 #define CLK_PCLK_SMMU_MFC_1
1011 #define CLK_PCLK_SMMU_MFC_0
1012
1013 /* CMU_HEVC */
1014 #define CLK_MOUT_ACLK_HEVC_400_USER
1015
1016 #define CLK_DIV_PCLK_HEVC
1017
1018 #define CLK_ACLK_BTS_HEVC_1
1019 #define CLK_ACLK_BTS_HEVC_0
1020 #define CLK_ACLK_AHB2APB_HEVCP
1021 #define CLK_ACLK_XIU_HEVCX
1022 #define CLK_ACLK_HEVCNP_100
1023 #define CLK_ACLK_HEVCND_400
1024 #define CLK_ACLK_HEVC
1025 #define CLK_ACLK_SMMU_HEVC_1
1026 #define CLK_ACLK_SMMU_HEVC_0
1027 #define CLK_PCLK_BTS_HEVC_1
1028 #define CLK_PCLK_BTS_HEVC_0
1029 #define CLK_PCLK_PMU_HEVC
1030 #define CLK_PCLK_SYSREG_HEVC
1031 #define CLK_PCLK_HEVC
1032 #define CLK_PCLK_SMMU_HEVC_1
1033 #define CLK_PCLK_SMMU_HEVC_0
1034
1035 /* CMU_ISP */
1036 #define CLK_MOUT_ACLK_ISP_DIS_400_USER
1037 #define CLK_MOUT_ACLK_ISP_400_USER
1038
1039 #define CLK_DIV_PCLK_ISP_DIS
1040 #define CLK_DIV_PCLK_ISP
1041 #define CLK_DIV_ACLK_ISP_D_200
1042 #define CLK_DIV_ACLK_ISP_C_200
1043
1044 #define CLK_ACLK_ISP_D_GLUE
1045 #define CLK_ACLK_SCALERP
1046 #define CLK_ACLK_3DNR
1047 #define CLK_ACLK_DIS
1048 #define CLK_ACLK_SCALERC
1049 #define CLK_ACLK_DRC
1050 #define CLK_ACLK_ISP
1051 #define CLK_ACLK_AXIUS_SCALERP
1052 #define CLK_ACLK_AXIUS_SCALERC
1053 #define CLK_ACLK_AXIUS_DRC
1054 #define CLK_ACLK_ASYNCAHBM_ISP2P
1055 #define CLK_ACLK_ASYNCAHBM_ISP1P
1056 #define CLK_ACLK_ASYNCAXIS_DIS1
1057 #define CLK_ACLK_ASYNCAXIS_DIS0
1058 #define CLK_ACLK_ASYNCAXIM_DIS1
1059 #define CLK_ACLK_ASYNCAXIM_DIS0
1060 #define CLK_ACLK_ASYNCAXIM_ISP2P
1061 #define CLK_ACLK_ASYNCAXIM_ISP1P
1062 #define CLK_ACLK_AHB2APB_ISP2P
1063 #define CLK_ACLK_AHB2APB_ISP1P
1064 #define CLK_ACLK_AXI2APB_ISP2P
1065 #define CLK_ACLK_AXI2APB_ISP1P
1066 #define CLK_ACLK_XIU_ISPEX1
1067 #define CLK_ACLK_XIU_ISPEX0
1068 #define CLK_ACLK_ISPND_400
1069 #define CLK_ACLK_SMMU_SCALERP
1070 #define CLK_ACLK_SMMU_3DNR
1071 #define CLK_ACLK_SMMU_DIS1
1072 #define CLK_ACLK_SMMU_DIS0
1073 #define CLK_ACLK_SMMU_SCALERC
1074 #define CLK_ACLK_SMMU_DRC
1075 #define CLK_ACLK_SMMU_ISP
1076 #define CLK_ACLK_BTS_SCALERP
1077 #define CLK_ACLK_BTS_3DR
1078 #define CLK_ACLK_BTS_DIS1
1079 #define CLK_ACLK_BTS_DIS0
1080 #define CLK_ACLK_BTS_SCALERC
1081 #define CLK_ACLK_BTS_DRC
1082 #define CLK_ACLK_BTS_ISP
1083 #define CLK_PCLK_SMMU_SCALERP
1084 #define CLK_PCLK_SMMU_3DNR
1085 #define CLK_PCLK_SMMU_DIS1
1086 #define CLK_PCLK_SMMU_DIS0
1087 #define CLK_PCLK_SMMU_SCALERC
1088 #define CLK_PCLK_SMMU_DRC
1089 #define CLK_PCLK_SMMU_ISP
1090 #define CLK_PCLK_BTS_SCALERP
1091 #define CLK_PCLK_BTS_3DNR
1092 #define CLK_PCLK_BTS_DIS1
1093 #define CLK_PCLK_BTS_DIS0
1094 #define CLK_PCLK_BTS_SCALERC
1095 #define CLK_PCLK_BTS_DRC
1096 #define CLK_PCLK_BTS_ISP
1097 #define CLK_PCLK_ASYNCAXI_DIS1
1098 #define CLK_PCLK_ASYNCAXI_DIS0
1099 #define CLK_PCLK_PMU_ISP
1100 #define CLK_PCLK_SYSREG_ISP
1101 #define CLK_PCLK_CMU_ISP_LOCAL
1102 #define CLK_PCLK_SCALERP
1103 #define CLK_PCLK_3DNR
1104 #define CLK_PCLK_DIS_CORE
1105 #define CLK_PCLK_DIS
1106 #define CLK_PCLK_SCALERC
1107 #define CLK_PCLK_DRC
1108 #define CLK_PCLK_ISP
1109 #define CLK_SCLK_PIXELASYNCS_DIS
1110 #define CLK_SCLK_PIXELASYNCM_DIS
1111 #define CLK_SCLK_PIXELASYNCS_SCALERP
1112 #define CLK_SCLK_PIXELASYNCM_ISPD
1113 #define CLK_SCLK_PIXELASYNCS_ISPC
1114 #define CLK_SCLK_PIXELASYNCM_ISPC
1115
1116 /* CMU_CAM0 */
1117 #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY
1118 #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY
1119
1120 #define CLK_MOUT_ACLK_CAM0_333_USER
1121 #define CLK_MOUT_ACLK_CAM0_400_USER
1122 #define CLK_MOUT_ACLK_CAM0_552_USER
1123 #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER
1124 #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER
1125 #define CLK_MOUT_ACLK_LITE_D_B
1126 #define CLK_MOUT_ACLK_LITE_D_A
1127 #define CLK_MOUT_ACLK_LITE_B_B
1128 #define CLK_MOUT_ACLK_LITE_B_A
1129 #define CLK_MOUT_ACLK_LITE_A_B
1130 #define CLK_MOUT_ACLK_LITE_A_A
1131 #define CLK_MOUT_ACLK_CAM0_400
1132 #define CLK_MOUT_ACLK_CSIS1_B
1133 #define CLK_MOUT_ACLK_CSIS1_A
1134 #define CLK_MOUT_ACLK_CSIS0_B
1135 #define CLK_MOUT_ACLK_CSIS0_A
1136 #define CLK_MOUT_ACLK_3AA1_B
1137 #define CLK_MOUT_ACLK_3AA1_A
1138 #define CLK_MOUT_ACLK_3AA0_B
1139 #define CLK_MOUT_ACLK_3AA0_A
1140 #define CLK_MOUT_SCLK_LITE_FREECNT_C
1141 #define CLK_MOUT_SCLK_LITE_FREECNT_B
1142 #define CLK_MOUT_SCLK_LITE_FREECNT_A
1143 #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B
1144 #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A
1145 #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_
1146 #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_
1147
1148 #define CLK_DIV_PCLK_CAM0_50
1149 #define CLK_DIV_ACLK_CAM0_200
1150 #define CLK_DIV_ACLK_CAM0_BUS_400
1151 #define CLK_DIV_PCLK_LITE_D
1152 #define CLK_DIV_ACLK_LITE_D
1153 #define CLK_DIV_PCLK_LITE_B
1154 #define CLK_DIV_ACLK_LITE_B
1155 #define CLK_DIV_PCLK_LITE_A
1156 #define CLK_DIV_ACLK_LITE_A
1157 #define CLK_DIV_ACLK_CSIS1
1158 #define CLK_DIV_ACLK_CSIS0
1159 #define CLK_DIV_PCLK_3AA1
1160 #define CLK_DIV_ACLK_3AA1
1161 #define CLK_DIV_PCLK_3AA0
1162 #define CLK_DIV_ACLK_3AA0
1163 #define CLK_DIV_SCLK_PIXELASYNC_LITE_C
1164 #define CLK_DIV_PCLK_PIXELASYNC_LITE_C
1165 #define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT
1166
1167 #define CLK_ACLK_CSIS1
1168 #define CLK_ACLK_CSIS0
1169 #define CLK_ACLK_3AA1
1170 #define CLK_ACLK_3AA0
1171 #define CLK_ACLK_LITE_D
1172 #define CLK_ACLK_LITE_B
1173 #define CLK_ACLK_LITE_A
1174 #define CLK_ACLK_AHBSYNCDN
1175 #define CLK_ACLK_AXIUS_LITE_D
1176 #define CLK_ACLK_AXIUS_LITE_B
1177 #define CLK_ACLK_AXIUS_LITE_A
1178 #define CLK_ACLK_ASYNCAPBM_3AA1
1179 #define CLK_ACLK_ASYNCAPBS_3AA1
1180 #define CLK_ACLK_ASYNCAPBM_3AA0
1181 #define CLK_ACLK_ASYNCAPBS_3AA0
1182 #define CLK_ACLK_ASYNCAPBM_LITE_D
1183 #define CLK_ACLK_ASYNCAPBS_LITE_D
1184 #define CLK_ACLK_ASYNCAPBM_LITE_B
1185 #define CLK_ACLK_ASYNCAPBS_LITE_B
1186 #define CLK_ACLK_ASYNCAPBM_LITE_A
1187 #define CLK_ACLK_ASYNCAPBS_LITE_A
1188 #define CLK_ACLK_ASYNCAXIM_ISP0P
1189 #define CLK_ACLK_ASYNCAXIM_3AA1
1190 #define CLK_ACLK_ASYNCAXIS_3AA1
1191 #define CLK_ACLK_ASYNCAXIM_3AA0
1192 #define CLK_ACLK_ASYNCAXIS_3AA0
1193 #define CLK_ACLK_ASYNCAXIM_LITE_D
1194 #define CLK_ACLK_ASYNCAXIS_LITE_D
1195 #define CLK_ACLK_ASYNCAXIM_LITE_B
1196 #define CLK_ACLK_ASYNCAXIS_LITE_B
1197 #define CLK_ACLK_ASYNCAXIM_LITE_A
1198 #define CLK_ACLK_ASYNCAXIS_LITE_A
1199 #define CLK_ACLK_AHB2APB_ISPSFRP
1200 #define CLK_ACLK_AXI2APB_ISP0P
1201 #define CLK_ACLK_AXI2AHB_ISP0P
1202 #define CLK_ACLK_XIU_IS0X
1203 #define CLK_ACLK_XIU_ISP0EX
1204 #define CLK_ACLK_CAM0NP_276
1205 #define CLK_ACLK_CAM0ND_400
1206 #define CLK_ACLK_SMMU_3AA1
1207 #define CLK_ACLK_SMMU_3AA0
1208 #define CLK_ACLK_SMMU_LITE_D
1209 #define CLK_ACLK_SMMU_LITE_B
1210 #define CLK_ACLK_SMMU_LITE_A
1211 #define CLK_ACLK_BTS_3AA1
1212 #define CLK_ACLK_BTS_3AA0
1213 #define CLK_ACLK_BTS_LITE_D
1214 #define CLK_ACLK_BTS_LITE_B
1215 #define CLK_ACLK_BTS_LITE_A
1216 #define CLK_PCLK_SMMU_3AA1
1217 #define CLK_PCLK_SMMU_3AA0
1218 #define CLK_PCLK_SMMU_LITE_D
1219 #define CLK_PCLK_SMMU_LITE_B
1220 #define CLK_PCLK_SMMU_LITE_A
1221 #define CLK_PCLK_BTS_3AA1
1222 #define CLK_PCLK_BTS_3AA0
1223 #define CLK_PCLK_BTS_LITE_D
1224 #define CLK_PCLK_BTS_LITE_B
1225 #define CLK_PCLK_BTS_LITE_A
1226 #define CLK_PCLK_ASYNCAXI_CAM1
1227 #define CLK_PCLK_ASYNCAXI_3AA1
1228 #define CLK_PCLK_ASYNCAXI_3AA0
1229 #define CLK_PCLK_ASYNCAXI_LITE_D
1230 #define CLK_PCLK_ASYNCAXI_LITE_B
1231 #define CLK_PCLK_ASYNCAXI_LITE_A
1232 #define CLK_PCLK_PMU_CAM0
1233 #define CLK_PCLK_SYSREG_CAM0
1234 #define CLK_PCLK_CMU_CAM0_LOCAL
1235 #define CLK_PCLK_CSIS1
1236 #define CLK_PCLK_CSIS0
1237 #define CLK_PCLK_3AA1
1238 #define CLK_PCLK_3AA0
1239 #define CLK_PCLK_LITE_D
1240 #define CLK_PCLK_LITE_B
1241 #define CLK_PCLK_LITE_A
1242 #define CLK_PHYCLK_RXBYTECLKHS0_S4
1243 #define CLK_PHYCLK_RXBYTECLKHS0_S2A
1244 #define CLK_SCLK_LITE_FREECNT
1245 #define CLK_SCLK_PIXELASYNCM_3AA1
1246 #define CLK_SCLK_PIXELASYNCM_3AA0
1247 #define CLK_SCLK_PIXELASYNCS_3AA0
1248 #define CLK_SCLK_PIXELASYNCM_LITE_C
1249 #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT
1250 #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT
1251
1252 /* CMU_CAM1 */
1253 #define CLK_PHYCLK_RXBYTEECLKHS0_S2B
1254
1255 #define CLK_MOUT_SCLK_ISP_UART_USER
1256 #define CLK_MOUT_SCLK_ISP_SPI1_USER
1257 #define CLK_MOUT_SCLK_ISP_SPI0_USER
1258 #define CLK_MOUT_ACLK_CAM1_333_USER
1259 #define CLK_MOUT_ACLK_CAM1_400_USER
1260 #define CLK_MOUT_ACLK_CAM1_552_USER
1261 #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER
1262 #define CLK_MOUT_ACLK_CSIS2_B
1263 #define CLK_MOUT_ACLK_CSIS2_A
1264 #define CLK_MOUT_ACLK_FD_B
1265 #define CLK_MOUT_ACLK_FD_A
1266 #define CLK_MOUT_ACLK_LITE_C_B
1267 #define CLK_MOUT_ACLK_LITE_C_A
1268
1269 #define CLK_DIV_SCLK_ISP_MPWM
1270 #define CLK_DIV_PCLK_CAM1_83
1271 #define CLK_DIV_PCLK_CAM1_166
1272 #define CLK_DIV_PCLK_DBG_CAM1
1273 #define CLK_DIV_ATCLK_CAM1
1274 #define CLK_DIV_ACLK_CSIS2
1275 #define CLK_DIV_PCLK_FD
1276 #define CLK_DIV_ACLK_FD
1277 #define CLK_DIV_PCLK_LITE_C
1278 #define CLK_DIV_ACLK_LITE_C
1279
1280 #define CLK_ACLK_ISP_GIC
1281 #define CLK_ACLK_FD
1282 #define CLK_ACLK_LITE_C
1283 #define CLK_ACLK_CSIS2
1284 #define CLK_ACLK_ASYNCAPBM_FD
1285 #define CLK_ACLK_ASYNCAPBS_FD
1286 #define CLK_ACLK_ASYNCAPBM_LITE_C
1287 #define CLK_ACLK_ASYNCAPBS_LITE_C
1288 #define CLK_ACLK_ASYNCAHBS_SFRISP2H2
1289 #define CLK_ACLK_ASYNCAHBS_SFRISP2H1
1290 #define CLK_ACLK_ASYNCAXIM_CA5
1291 #define CLK_ACLK_ASYNCAXIS_CA5
1292 #define CLK_ACLK_ASYNCAXIS_ISPX2
1293 #define CLK_ACLK_ASYNCAXIS_ISPX1
1294 #define CLK_ACLK_ASYNCAXIS_ISPX0
1295 #define CLK_ACLK_ASYNCAXIM_ISPEX
1296 #define CLK_ACLK_ASYNCAXIM_ISP3P
1297 #define CLK_ACLK_ASYNCAXIS_ISP3P
1298 #define CLK_ACLK_ASYNCAXIM_FD
1299 #define CLK_ACLK_ASYNCAXIS_FD
1300 #define CLK_ACLK_ASYNCAXIM_LITE_C
1301 #define CLK_ACLK_ASYNCAXIS_LITE_C
1302 #define CLK_ACLK_AHB2APB_ISP5P
1303 #define CLK_ACLK_AHB2APB_ISP3P
1304 #define CLK_ACLK_AXI2APB_ISP3P
1305 #define CLK_ACLK_AHB_SFRISP2H
1306 #define CLK_ACLK_AXI_ISP_HX_R
1307 #define CLK_ACLK_AXI_ISP_CX_R
1308 #define CLK_ACLK_AXI_ISP_HX
1309 #define CLK_ACLK_AXI_ISP_CX
1310 #define CLK_ACLK_XIU_ISPX
1311 #define CLK_ACLK_XIU_ISPEX
1312 #define CLK_ACLK_CAM1NP_333
1313 #define CLK_ACLK_CAM1ND_400
1314 #define CLK_ACLK_SMMU_ISPCPU
1315 #define CLK_ACLK_SMMU_FD
1316 #define CLK_ACLK_SMMU_LITE_C
1317 #define CLK_ACLK_BTS_ISP3P
1318 #define CLK_ACLK_BTS_FD
1319 #define CLK_ACLK_BTS_LITE_C
1320 #define CLK_ACLK_AHBDN_SFRISP2H
1321 #define CLK_ACLK_AHBDN_ISP5P
1322 #define CLK_ACLK_AXIUS_ISP3P
1323 #define CLK_ACLK_AXIUS_FD
1324 #define CLK_ACLK_AXIUS_LITE_C
1325 #define CLK_PCLK_SMMU_ISPCPU
1326 #define CLK_PCLK_SMMU_FD
1327 #define CLK_PCLK_SMMU_LITE_C
1328 #define CLK_PCLK_BTS_ISP3P
1329 #define CLK_PCLK_BTS_FD
1330 #define CLK_PCLK_BTS_LITE_C
1331 #define CLK_PCLK_ASYNCAXIM_CA5
1332 #define CLK_PCLK_ASYNCAXIM_ISPEX
1333 #define CLK_PCLK_ASYNCAXIM_ISP3P
1334 #define CLK_PCLK_ASYNCAXIM_FD
1335 #define CLK_PCLK_ASYNCAXIM_LITE_C
1336 #define CLK_PCLK_PMU_CAM1
1337 #define CLK_PCLK_SYSREG_CAM1
1338 #define CLK_PCLK_CMU_CAM1_LOCAL
1339 #define CLK_PCLK_ISP_MCTADC
1340 #define CLK_PCLK_ISP_WDT
1341 #define CLK_PCLK_ISP_PWM
1342 #define CLK_PCLK_ISP_UART
1343 #define CLK_PCLK_ISP_MCUCTL
1344 #define CLK_PCLK_ISP_SPI1
1345 #define CLK_PCLK_ISP_SPI0
1346 #define CLK_PCLK_ISP_I2C2
1347 #define CLK_PCLK_ISP_I2C1
1348 #define CLK_PCLK_ISP_I2C0
1349 #define CLK_PCLK_ISP_MPWM
1350 #define CLK_PCLK_FD
1351 #define CLK_PCLK_LITE_C
1352 #define CLK_PCLK_CSIS2
1353 #define CLK_SCLK_ISP_I2C2
1354 #define CLK_SCLK_ISP_I2C1
1355 #define CLK_SCLK_ISP_I2C0
1356 #define CLK_SCLK_ISP_PWM
1357 #define CLK_PHYCLK_RXBYTECLKHS0_S2B
1358 #define CLK_SCLK_LITE_C_FREECNT
1359 #define CLK_SCLK_PIXELASYNCM_FD
1360 #define CLK_SCLK_ISP_MCTADC
1361 #define CLK_SCLK_ISP_UART
1362 #define CLK_SCLK_ISP_SPI1
1363 #define CLK_SCLK_ISP_SPI0
1364 #define CLK_SCLK_ISP_MPWM
1365 #define CLK_PCLK_DBG_ISP
1366 #define CLK_ATCLK_ISP
1367 #define CLK_SCLK_ISP_CA5
1368
1369 /* CMU_IMEM */
1370 #define CLK_ACLK_SLIMSSS 2
1371 #define CLK_PCLK_SLIMSSS 35
1372
1373 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
1374
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