1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ 1 2 /* 3 * Meson-G12A clock tree IDs 4 * 5 * Copyright (c) 2018 Amlogic, Inc. All rights 6 */ 7 8 #ifndef __G12A_CLKC_H 9 #define __G12A_CLKC_H 10 11 #define CLKID_SYS_PLL 12 #define CLKID_FIXED_PLL 13 #define CLKID_FCLK_DIV2 14 #define CLKID_FCLK_DIV3 15 #define CLKID_FCLK_DIV4 16 #define CLKID_FCLK_DIV5 17 #define CLKID_FCLK_DIV7 18 #define CLKID_GP0_PLL 19 #define CLKID_MPEG_SEL 20 #define CLKID_MPEG_DIV 21 #define CLKID_CLK81 22 #define CLKID_MPLL0 23 #define CLKID_MPLL1 24 #define CLKID_MPLL2 25 #define CLKID_MPLL3 26 #define CLKID_DDR 27 #define CLKID_DOS 28 #define CLKID_AUDIO_LOCKER 29 #define CLKID_MIPI_DSI_HOST 30 #define CLKID_ETH_PHY 31 #define CLKID_ISA 32 #define CLKID_PL301 33 #define CLKID_PERIPHS 34 #define CLKID_SPICC0 35 #define CLKID_I2C 36 #define CLKID_SANA 37 #define CLKID_SD 38 #define CLKID_RNG0 39 #define CLKID_UART0 40 #define CLKID_SPICC1 41 #define CLKID_HIU_IFACE 42 #define CLKID_MIPI_DSI_PHY 43 #define CLKID_ASSIST_MISC 44 #define CLKID_SD_EMMC_A 45 #define CLKID_SD_EMMC_B 46 #define CLKID_SD_EMMC_C 47 #define CLKID_AUDIO_CODEC 48 #define CLKID_AUDIO 49 #define CLKID_ETH 50 #define CLKID_DEMUX 51 #define CLKID_AUDIO_IFIFO 52 #define CLKID_ADC 53 #define CLKID_UART1 54 #define CLKID_G2D 55 #define CLKID_RESET 56 #define CLKID_PCIE_COMB 57 #define CLKID_PARSER 58 #define CLKID_USB 59 #define CLKID_PCIE_PHY 60 #define CLKID_AHB_ARB0 61 #define CLKID_AHB_DATA_BUS 62 #define CLKID_AHB_CTRL_BUS 63 #define CLKID_HTX_HDCP22 64 #define CLKID_HTX_PCLK 65 #define CLKID_BT656 66 #define CLKID_USB1_DDR_BRIDGE 67 #define CLKID_MMC_PCLK 68 #define CLKID_UART2 69 #define CLKID_VPU_INTR 70 #define CLKID_GIC 71 #define CLKID_SD_EMMC_A_CLK0 72 #define CLKID_SD_EMMC_B_CLK0 73 #define CLKID_SD_EMMC_C_CLK0 74 #define CLKID_SD_EMMC_A_CLK0_SEL 75 #define CLKID_SD_EMMC_A_CLK0_DIV 76 #define CLKID_SD_EMMC_B_CLK0_SEL 77 #define CLKID_SD_EMMC_B_CLK0_DIV 78 #define CLKID_SD_EMMC_C_CLK0_SEL 79 #define CLKID_SD_EMMC_C_CLK0_DIV 80 #define CLKID_MPLL0_DIV 81 #define CLKID_MPLL1_DIV 82 #define CLKID_MPLL2_DIV 83 #define CLKID_MPLL3_DIV 84 #define CLKID_MPLL_PREDIV 85 #define CLKID_HIFI_PLL 86 #define CLKID_FCLK_DIV2_DIV 87 #define CLKID_FCLK_DIV3_DIV 88 #define CLKID_FCLK_DIV4_DIV 89 #define CLKID_FCLK_DIV5_DIV 90 #define CLKID_FCLK_DIV7_DIV 91 #define CLKID_VCLK2_VENCI0 92 #define CLKID_VCLK2_VENCI1 93 #define CLKID_VCLK2_VENCP0 94 #define CLKID_VCLK2_VENCP1 95 #define CLKID_VCLK2_VENCT0 96 #define CLKID_VCLK2_VENCT1 97 #define CLKID_VCLK2_OTHER 98 #define CLKID_VCLK2_ENCI 99 #define CLKID_VCLK2_ENCP 100 #define CLKID_DAC_CLK 101 #define CLKID_AOCLK 102 #define CLKID_IEC958 103 #define CLKID_ENC480P 104 #define CLKID_RNG1 105 #define CLKID_VCLK2_ENCT 106 #define CLKID_VCLK2_ENCL 107 #define CLKID_VCLK2_VENCLMMC 108 #define CLKID_VCLK2_VENCL 109 #define CLKID_VCLK2_OTHER1 110 #define CLKID_FCLK_DIV2P5 111 #define CLKID_FCLK_DIV2P5_DIV 112 #define CLKID_FIXED_PLL_DCO 113 #define CLKID_SYS_PLL_DCO 114 #define CLKID_GP0_PLL_DCO 115 #define CLKID_HIFI_PLL_DCO 116 #define CLKID_DMA 117 #define CLKID_EFUSE 118 #define CLKID_ROM_BOOT 119 #define CLKID_RESET_SEC 120 #define CLKID_SEC_AHB_APB3 121 #define CLKID_VPU_0_SEL 122 #define CLKID_VPU_0_DIV 123 #define CLKID_VPU_0 124 #define CLKID_VPU_1_SEL 125 #define CLKID_VPU_1_DIV 126 #define CLKID_VPU_1 127 #define CLKID_VPU 128 #define CLKID_VAPB_0_SEL 129 #define CLKID_VAPB_0_DIV 130 #define CLKID_VAPB_0 131 #define CLKID_VAPB_1_SEL 132 #define CLKID_VAPB_1_DIV 133 #define CLKID_VAPB_1 134 #define CLKID_VAPB_SEL 135 #define CLKID_VAPB 136 #define CLKID_HDMI_PLL_DCO 137 #define CLKID_HDMI_PLL_OD 138 #define CLKID_HDMI_PLL_OD2 139 #define CLKID_HDMI_PLL 140 #define CLKID_VID_PLL 141 #define CLKID_VID_PLL_SEL 142 #define CLKID_VID_PLL_DIV 143 #define CLKID_VCLK_SEL 144 #define CLKID_VCLK2_SEL 145 #define CLKID_VCLK_INPUT 146 #define CLKID_VCLK2_INPUT 147 #define CLKID_VCLK_DIV 148 #define CLKID_VCLK2_DIV 149 #define CLKID_VCLK 150 #define CLKID_VCLK2 151 #define CLKID_VCLK_DIV2_EN 152 #define CLKID_VCLK_DIV4_EN 153 #define CLKID_VCLK_DIV6_EN 154 #define CLKID_VCLK_DIV12_EN 155 #define CLKID_VCLK2_DIV2_EN 156 #define CLKID_VCLK2_DIV4_EN 157 #define CLKID_VCLK2_DIV6_EN 158 #define CLKID_VCLK2_DIV12_EN 159 #define CLKID_VCLK_DIV1 160 #define CLKID_VCLK_DIV2 161 #define CLKID_VCLK_DIV4 162 #define CLKID_VCLK_DIV6 163 #define CLKID_VCLK_DIV12 164 #define CLKID_VCLK2_DIV1 165 #define CLKID_VCLK2_DIV2 166 #define CLKID_VCLK2_DIV4 167 #define CLKID_VCLK2_DIV6 168 #define CLKID_VCLK2_DIV12 169 #define CLKID_CTS_ENCI_SEL 170 #define CLKID_CTS_ENCP_SEL 171 #define CLKID_CTS_VDAC_SEL 172 #define CLKID_HDMI_TX_SEL 173 #define CLKID_CTS_ENCI 174 #define CLKID_CTS_ENCP 175 #define CLKID_CTS_VDAC 176 #define CLKID_HDMI_TX 177 #define CLKID_HDMI_SEL 178 #define CLKID_HDMI_DIV 179 #define CLKID_HDMI 180 #define CLKID_MALI_0_SEL 181 #define CLKID_MALI_0_DIV 182 #define CLKID_MALI_0 183 #define CLKID_MALI_1_SEL 184 #define CLKID_MALI_1_DIV 185 #define CLKID_MALI_1 186 #define CLKID_MALI 187 #define CLKID_MPLL_50M_DIV 188 #define CLKID_MPLL_50M 189 #define CLKID_SYS_PLL_DIV16_EN 190 #define CLKID_SYS_PLL_DIV16 191 #define CLKID_CPU_CLK_DYN0_SEL 192 #define CLKID_CPU_CLK_DYN0_DIV 193 #define CLKID_CPU_CLK_DYN0 194 #define CLKID_CPU_CLK_DYN1_SEL 195 #define CLKID_CPU_CLK_DYN1_DIV 196 #define CLKID_CPU_CLK_DYN1 197 #define CLKID_CPU_CLK_DYN 198 #define CLKID_CPU_CLK 199 #define CLKID_CPU_CLK_DIV16_EN 200 #define CLKID_CPU_CLK_DIV16 201 #define CLKID_CPU_CLK_APB_DIV 202 #define CLKID_CPU_CLK_APB 203 #define CLKID_CPU_CLK_ATB_DIV 204 #define CLKID_CPU_CLK_ATB 205 #define CLKID_CPU_CLK_AXI_DIV 206 #define CLKID_CPU_CLK_AXI 207 #define CLKID_CPU_CLK_TRACE_DIV 208 #define CLKID_CPU_CLK_TRACE 209 #define CLKID_PCIE_PLL_DCO 210 #define CLKID_PCIE_PLL_DCO_DIV2 211 #define CLKID_PCIE_PLL_OD 212 #define CLKID_PCIE_PLL 213 #define CLKID_VDEC_1_SEL 214 #define CLKID_VDEC_1_DIV 215 #define CLKID_VDEC_1 216 #define CLKID_VDEC_HEVC_SEL 217 #define CLKID_VDEC_HEVC_DIV 218 #define CLKID_VDEC_HEVC 219 #define CLKID_VDEC_HEVCF_SEL 220 #define CLKID_VDEC_HEVCF_DIV 221 #define CLKID_VDEC_HEVCF 222 #define CLKID_TS_DIV 223 #define CLKID_TS 224 #define CLKID_SYS1_PLL_DCO 225 #define CLKID_SYS1_PLL 226 #define CLKID_SYS1_PLL_DIV16_EN 227 #define CLKID_SYS1_PLL_DIV16 228 #define CLKID_CPUB_CLK_DYN0_SEL 229 #define CLKID_CPUB_CLK_DYN0_DIV 230 #define CLKID_CPUB_CLK_DYN0 231 #define CLKID_CPUB_CLK_DYN1_SEL 232 #define CLKID_CPUB_CLK_DYN1_DIV 233 #define CLKID_CPUB_CLK_DYN1 234 #define CLKID_CPUB_CLK_DYN 235 #define CLKID_CPUB_CLK 236 #define CLKID_CPUB_CLK_DIV16_EN 237 #define CLKID_CPUB_CLK_DIV16 238 #define CLKID_CPUB_CLK_DIV2 239 #define CLKID_CPUB_CLK_DIV3 240 #define CLKID_CPUB_CLK_DIV4 241 #define CLKID_CPUB_CLK_DIV5 242 #define CLKID_CPUB_CLK_DIV6 243 #define CLKID_CPUB_CLK_DIV7 244 #define CLKID_CPUB_CLK_DIV8 245 #define CLKID_CPUB_CLK_APB_SEL 246 #define CLKID_CPUB_CLK_APB 247 #define CLKID_CPUB_CLK_ATB_SEL 248 #define CLKID_CPUB_CLK_ATB 249 #define CLKID_CPUB_CLK_AXI_SEL 250 #define CLKID_CPUB_CLK_AXI 251 #define CLKID_CPUB_CLK_TRACE_SEL 252 #define CLKID_CPUB_CLK_TRACE 253 #define CLKID_GP1_PLL_DCO 254 #define CLKID_GP1_PLL 255 #define CLKID_DSU_CLK_DYN0_SEL 256 #define CLKID_DSU_CLK_DYN0_DIV 257 #define CLKID_DSU_CLK_DYN0 258 #define CLKID_DSU_CLK_DYN1_SEL 259 #define CLKID_DSU_CLK_DYN1_DIV 260 #define CLKID_DSU_CLK_DYN1 261 #define CLKID_DSU_CLK_DYN 262 #define CLKID_DSU_CLK_FINAL 263 #define CLKID_DSU_CLK 264 #define CLKID_CPU1_CLK 265 #define CLKID_CPU2_CLK 266 #define CLKID_CPU3_CLK 267 #define CLKID_SPICC0_SCLK_SEL 268 #define CLKID_SPICC0_SCLK_DIV 269 #define CLKID_SPICC0_SCLK 270 #define CLKID_SPICC1_SCLK_SEL 271 #define CLKID_SPICC1_SCLK_DIV 272 #define CLKID_SPICC1_SCLK 273 #define CLKID_NNA_AXI_CLK_SEL 274 #define CLKID_NNA_AXI_CLK_DIV 275 #define CLKID_NNA_AXI_CLK 276 #define CLKID_NNA_CORE_CLK_SEL 277 #define CLKID_NNA_CORE_CLK_DIV 278 #define CLKID_NNA_CORE_CLK 279 #define CLKID_MIPI_DSI_PXCLK_DIV 280 #define CLKID_MIPI_DSI_PXCLK_SEL 281 #define CLKID_MIPI_DSI_PXCLK 282 #define CLKID_CTS_ENCL 283 #define CLKID_CTS_ENCL_SEL 284 #define CLKID_MIPI_ISP_DIV 285 #define CLKID_MIPI_ISP_SEL 286 #define CLKID_MIPI_ISP 287 #define CLKID_MIPI_ISP_GATE 288 #define CLKID_MIPI_ISP_CSI_PHY0 289 #define CLKID_MIPI_ISP_CSI_PHY1 290 291 #endif /* __G12A_CLKC_H */ 292
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