1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ 1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ 2 /* 2 /* 3 * Meson-G12A clock tree IDs 3 * Meson-G12A clock tree IDs 4 * 4 * 5 * Copyright (c) 2018 Amlogic, Inc. All rights 5 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 6 */ 6 */ 7 7 8 #ifndef __G12A_CLKC_H 8 #ifndef __G12A_CLKC_H 9 #define __G12A_CLKC_H 9 #define __G12A_CLKC_H 10 10 11 #define CLKID_SYS_PLL 11 #define CLKID_SYS_PLL 0 12 #define CLKID_FIXED_PLL 12 #define CLKID_FIXED_PLL 1 13 #define CLKID_FCLK_DIV2 13 #define CLKID_FCLK_DIV2 2 14 #define CLKID_FCLK_DIV3 14 #define CLKID_FCLK_DIV3 3 15 #define CLKID_FCLK_DIV4 15 #define CLKID_FCLK_DIV4 4 16 #define CLKID_FCLK_DIV5 16 #define CLKID_FCLK_DIV5 5 17 #define CLKID_FCLK_DIV7 17 #define CLKID_FCLK_DIV7 6 18 #define CLKID_GP0_PLL 18 #define CLKID_GP0_PLL 7 19 #define CLKID_MPEG_SEL << 20 #define CLKID_MPEG_DIV << 21 #define CLKID_CLK81 19 #define CLKID_CLK81 10 22 #define CLKID_MPLL0 20 #define CLKID_MPLL0 11 23 #define CLKID_MPLL1 21 #define CLKID_MPLL1 12 24 #define CLKID_MPLL2 22 #define CLKID_MPLL2 13 25 #define CLKID_MPLL3 23 #define CLKID_MPLL3 14 26 #define CLKID_DDR 24 #define CLKID_DDR 15 27 #define CLKID_DOS 25 #define CLKID_DOS 16 28 #define CLKID_AUDIO_LOCKER 26 #define CLKID_AUDIO_LOCKER 17 29 #define CLKID_MIPI_DSI_HOST 27 #define CLKID_MIPI_DSI_HOST 18 30 #define CLKID_ETH_PHY 28 #define CLKID_ETH_PHY 19 31 #define CLKID_ISA 29 #define CLKID_ISA 20 32 #define CLKID_PL301 30 #define CLKID_PL301 21 33 #define CLKID_PERIPHS 31 #define CLKID_PERIPHS 22 34 #define CLKID_SPICC0 32 #define CLKID_SPICC0 23 35 #define CLKID_I2C 33 #define CLKID_I2C 24 36 #define CLKID_SANA 34 #define CLKID_SANA 25 37 #define CLKID_SD 35 #define CLKID_SD 26 38 #define CLKID_RNG0 36 #define CLKID_RNG0 27 39 #define CLKID_UART0 37 #define CLKID_UART0 28 40 #define CLKID_SPICC1 38 #define CLKID_SPICC1 29 41 #define CLKID_HIU_IFACE 39 #define CLKID_HIU_IFACE 30 42 #define CLKID_MIPI_DSI_PHY 40 #define CLKID_MIPI_DSI_PHY 31 43 #define CLKID_ASSIST_MISC 41 #define CLKID_ASSIST_MISC 32 44 #define CLKID_SD_EMMC_A 42 #define CLKID_SD_EMMC_A 33 45 #define CLKID_SD_EMMC_B 43 #define CLKID_SD_EMMC_B 34 46 #define CLKID_SD_EMMC_C 44 #define CLKID_SD_EMMC_C 35 47 #define CLKID_AUDIO_CODEC 45 #define CLKID_AUDIO_CODEC 36 48 #define CLKID_AUDIO 46 #define CLKID_AUDIO 37 49 #define CLKID_ETH 47 #define CLKID_ETH 38 50 #define CLKID_DEMUX 48 #define CLKID_DEMUX 39 51 #define CLKID_AUDIO_IFIFO 49 #define CLKID_AUDIO_IFIFO 40 52 #define CLKID_ADC 50 #define CLKID_ADC 41 53 #define CLKID_UART1 51 #define CLKID_UART1 42 54 #define CLKID_G2D 52 #define CLKID_G2D 43 55 #define CLKID_RESET 53 #define CLKID_RESET 44 56 #define CLKID_PCIE_COMB 54 #define CLKID_PCIE_COMB 45 57 #define CLKID_PARSER 55 #define CLKID_PARSER 46 58 #define CLKID_USB 56 #define CLKID_USB 47 59 #define CLKID_PCIE_PHY 57 #define CLKID_PCIE_PHY 48 60 #define CLKID_AHB_ARB0 58 #define CLKID_AHB_ARB0 49 61 #define CLKID_AHB_DATA_BUS 59 #define CLKID_AHB_DATA_BUS 50 62 #define CLKID_AHB_CTRL_BUS 60 #define CLKID_AHB_CTRL_BUS 51 63 #define CLKID_HTX_HDCP22 61 #define CLKID_HTX_HDCP22 52 64 #define CLKID_HTX_PCLK 62 #define CLKID_HTX_PCLK 53 65 #define CLKID_BT656 63 #define CLKID_BT656 54 66 #define CLKID_USB1_DDR_BRIDGE 64 #define CLKID_USB1_DDR_BRIDGE 55 67 #define CLKID_MMC_PCLK 65 #define CLKID_MMC_PCLK 56 68 #define CLKID_UART2 66 #define CLKID_UART2 57 69 #define CLKID_VPU_INTR 67 #define CLKID_VPU_INTR 58 70 #define CLKID_GIC 68 #define CLKID_GIC 59 71 #define CLKID_SD_EMMC_A_CLK0 69 #define CLKID_SD_EMMC_A_CLK0 60 72 #define CLKID_SD_EMMC_B_CLK0 70 #define CLKID_SD_EMMC_B_CLK0 61 73 #define CLKID_SD_EMMC_C_CLK0 71 #define CLKID_SD_EMMC_C_CLK0 62 74 #define CLKID_SD_EMMC_A_CLK0_SEL << 75 #define CLKID_SD_EMMC_A_CLK0_DIV << 76 #define CLKID_SD_EMMC_B_CLK0_SEL << 77 #define CLKID_SD_EMMC_B_CLK0_DIV << 78 #define CLKID_SD_EMMC_C_CLK0_SEL << 79 #define CLKID_SD_EMMC_C_CLK0_DIV << 80 #define CLKID_MPLL0_DIV << 81 #define CLKID_MPLL1_DIV << 82 #define CLKID_MPLL2_DIV << 83 #define CLKID_MPLL3_DIV << 84 #define CLKID_MPLL_PREDIV << 85 #define CLKID_HIFI_PLL 72 #define CLKID_HIFI_PLL 74 86 #define CLKID_FCLK_DIV2_DIV << 87 #define CLKID_FCLK_DIV3_DIV << 88 #define CLKID_FCLK_DIV4_DIV << 89 #define CLKID_FCLK_DIV5_DIV << 90 #define CLKID_FCLK_DIV7_DIV << 91 #define CLKID_VCLK2_VENCI0 73 #define CLKID_VCLK2_VENCI0 80 92 #define CLKID_VCLK2_VENCI1 74 #define CLKID_VCLK2_VENCI1 81 93 #define CLKID_VCLK2_VENCP0 75 #define CLKID_VCLK2_VENCP0 82 94 #define CLKID_VCLK2_VENCP1 76 #define CLKID_VCLK2_VENCP1 83 95 #define CLKID_VCLK2_VENCT0 77 #define CLKID_VCLK2_VENCT0 84 96 #define CLKID_VCLK2_VENCT1 78 #define CLKID_VCLK2_VENCT1 85 97 #define CLKID_VCLK2_OTHER 79 #define CLKID_VCLK2_OTHER 86 98 #define CLKID_VCLK2_ENCI 80 #define CLKID_VCLK2_ENCI 87 99 #define CLKID_VCLK2_ENCP 81 #define CLKID_VCLK2_ENCP 88 100 #define CLKID_DAC_CLK 82 #define CLKID_DAC_CLK 89 101 #define CLKID_AOCLK 83 #define CLKID_AOCLK 90 102 #define CLKID_IEC958 84 #define CLKID_IEC958 91 103 #define CLKID_ENC480P 85 #define CLKID_ENC480P 92 104 #define CLKID_RNG1 86 #define CLKID_RNG1 93 105 #define CLKID_VCLK2_ENCT 87 #define CLKID_VCLK2_ENCT 94 106 #define CLKID_VCLK2_ENCL 88 #define CLKID_VCLK2_ENCL 95 107 #define CLKID_VCLK2_VENCLMMC 89 #define CLKID_VCLK2_VENCLMMC 96 108 #define CLKID_VCLK2_VENCL 90 #define CLKID_VCLK2_VENCL 97 109 #define CLKID_VCLK2_OTHER1 91 #define CLKID_VCLK2_OTHER1 98 110 #define CLKID_FCLK_DIV2P5 92 #define CLKID_FCLK_DIV2P5 99 111 #define CLKID_FCLK_DIV2P5_DIV << 112 #define CLKID_FIXED_PLL_DCO << 113 #define CLKID_SYS_PLL_DCO << 114 #define CLKID_GP0_PLL_DCO << 115 #define CLKID_HIFI_PLL_DCO << 116 #define CLKID_DMA 93 #define CLKID_DMA 105 117 #define CLKID_EFUSE 94 #define CLKID_EFUSE 106 118 #define CLKID_ROM_BOOT 95 #define CLKID_ROM_BOOT 107 119 #define CLKID_RESET_SEC 96 #define CLKID_RESET_SEC 108 120 #define CLKID_SEC_AHB_APB3 97 #define CLKID_SEC_AHB_APB3 109 121 #define CLKID_VPU_0_SEL 98 #define CLKID_VPU_0_SEL 110 122 #define CLKID_VPU_0_DIV << 123 #define CLKID_VPU_0 99 #define CLKID_VPU_0 112 124 #define CLKID_VPU_1_SEL 100 #define CLKID_VPU_1_SEL 113 125 #define CLKID_VPU_1_DIV << 126 #define CLKID_VPU_1 101 #define CLKID_VPU_1 115 127 #define CLKID_VPU 102 #define CLKID_VPU 116 128 #define CLKID_VAPB_0_SEL 103 #define CLKID_VAPB_0_SEL 117 129 #define CLKID_VAPB_0_DIV << 130 #define CLKID_VAPB_0 104 #define CLKID_VAPB_0 119 131 #define CLKID_VAPB_1_SEL 105 #define CLKID_VAPB_1_SEL 120 132 #define CLKID_VAPB_1_DIV << 133 #define CLKID_VAPB_1 106 #define CLKID_VAPB_1 122 134 #define CLKID_VAPB_SEL 107 #define CLKID_VAPB_SEL 123 135 #define CLKID_VAPB 108 #define CLKID_VAPB 124 136 #define CLKID_HDMI_PLL_DCO << 137 #define CLKID_HDMI_PLL_OD << 138 #define CLKID_HDMI_PLL_OD2 << 139 #define CLKID_HDMI_PLL 109 #define CLKID_HDMI_PLL 128 140 #define CLKID_VID_PLL 110 #define CLKID_VID_PLL 129 141 #define CLKID_VID_PLL_SEL << 142 #define CLKID_VID_PLL_DIV << 143 #define CLKID_VCLK_SEL << 144 #define CLKID_VCLK2_SEL << 145 #define CLKID_VCLK_INPUT << 146 #define CLKID_VCLK2_INPUT << 147 #define CLKID_VCLK_DIV << 148 #define CLKID_VCLK2_DIV << 149 #define CLKID_VCLK 111 #define CLKID_VCLK 138 150 #define CLKID_VCLK2 112 #define CLKID_VCLK2 139 151 #define CLKID_VCLK_DIV2_EN << 152 #define CLKID_VCLK_DIV4_EN << 153 #define CLKID_VCLK_DIV6_EN << 154 #define CLKID_VCLK_DIV12_EN << 155 #define CLKID_VCLK2_DIV2_EN << 156 #define CLKID_VCLK2_DIV4_EN << 157 #define CLKID_VCLK2_DIV6_EN << 158 #define CLKID_VCLK2_DIV12_EN << 159 #define CLKID_VCLK_DIV1 113 #define CLKID_VCLK_DIV1 148 160 #define CLKID_VCLK_DIV2 114 #define CLKID_VCLK_DIV2 149 161 #define CLKID_VCLK_DIV4 115 #define CLKID_VCLK_DIV4 150 162 #define CLKID_VCLK_DIV6 116 #define CLKID_VCLK_DIV6 151 163 #define CLKID_VCLK_DIV12 117 #define CLKID_VCLK_DIV12 152 164 #define CLKID_VCLK2_DIV1 118 #define CLKID_VCLK2_DIV1 153 165 #define CLKID_VCLK2_DIV2 119 #define CLKID_VCLK2_DIV2 154 166 #define CLKID_VCLK2_DIV4 120 #define CLKID_VCLK2_DIV4 155 167 #define CLKID_VCLK2_DIV6 121 #define CLKID_VCLK2_DIV6 156 168 #define CLKID_VCLK2_DIV12 122 #define CLKID_VCLK2_DIV12 157 169 #define CLKID_CTS_ENCI_SEL << 170 #define CLKID_CTS_ENCP_SEL << 171 #define CLKID_CTS_VDAC_SEL << 172 #define CLKID_HDMI_TX_SEL << 173 #define CLKID_CTS_ENCI 123 #define CLKID_CTS_ENCI 162 174 #define CLKID_CTS_ENCP 124 #define CLKID_CTS_ENCP 163 175 #define CLKID_CTS_VDAC 125 #define CLKID_CTS_VDAC 164 176 #define CLKID_HDMI_TX 126 #define CLKID_HDMI_TX 165 177 #define CLKID_HDMI_SEL << 178 #define CLKID_HDMI_DIV << 179 #define CLKID_HDMI 127 #define CLKID_HDMI 168 180 #define CLKID_MALI_0_SEL 128 #define CLKID_MALI_0_SEL 169 181 #define CLKID_MALI_0_DIV << 182 #define CLKID_MALI_0 129 #define CLKID_MALI_0 171 183 #define CLKID_MALI_1_SEL 130 #define CLKID_MALI_1_SEL 172 184 #define CLKID_MALI_1_DIV << 185 #define CLKID_MALI_1 131 #define CLKID_MALI_1 174 186 #define CLKID_MALI 132 #define CLKID_MALI 175 187 #define CLKID_MPLL_50M_DIV << 188 #define CLKID_MPLL_50M 133 #define CLKID_MPLL_50M 177 189 #define CLKID_SYS_PLL_DIV16_EN << 190 #define CLKID_SYS_PLL_DIV16 << 191 #define CLKID_CPU_CLK_DYN0_SEL << 192 #define CLKID_CPU_CLK_DYN0_DIV << 193 #define CLKID_CPU_CLK_DYN0 << 194 #define CLKID_CPU_CLK_DYN1_SEL << 195 #define CLKID_CPU_CLK_DYN1_DIV << 196 #define CLKID_CPU_CLK_DYN1 << 197 #define CLKID_CPU_CLK_DYN << 198 #define CLKID_CPU_CLK 134 #define CLKID_CPU_CLK 187 199 #define CLKID_CPU_CLK_DIV16_EN << 200 #define CLKID_CPU_CLK_DIV16 << 201 #define CLKID_CPU_CLK_APB_DIV << 202 #define CLKID_CPU_CLK_APB << 203 #define CLKID_CPU_CLK_ATB_DIV << 204 #define CLKID_CPU_CLK_ATB << 205 #define CLKID_CPU_CLK_AXI_DIV << 206 #define CLKID_CPU_CLK_AXI << 207 #define CLKID_CPU_CLK_TRACE_DIV << 208 #define CLKID_CPU_CLK_TRACE << 209 #define CLKID_PCIE_PLL_DCO << 210 #define CLKID_PCIE_PLL_DCO_DIV2 << 211 #define CLKID_PCIE_PLL_OD << 212 #define CLKID_PCIE_PLL 135 #define CLKID_PCIE_PLL 201 213 #define CLKID_VDEC_1_SEL << 214 #define CLKID_VDEC_1_DIV << 215 #define CLKID_VDEC_1 136 #define CLKID_VDEC_1 204 216 #define CLKID_VDEC_HEVC_SEL << 217 #define CLKID_VDEC_HEVC_DIV << 218 #define CLKID_VDEC_HEVC 137 #define CLKID_VDEC_HEVC 207 219 #define CLKID_VDEC_HEVCF_SEL << 220 #define CLKID_VDEC_HEVCF_DIV << 221 #define CLKID_VDEC_HEVCF 138 #define CLKID_VDEC_HEVCF 210 222 #define CLKID_TS_DIV << 223 #define CLKID_TS 139 #define CLKID_TS 212 224 #define CLKID_SYS1_PLL_DCO << 225 #define CLKID_SYS1_PLL << 226 #define CLKID_SYS1_PLL_DIV16_EN << 227 #define CLKID_SYS1_PLL_DIV16 << 228 #define CLKID_CPUB_CLK_DYN0_SEL << 229 #define CLKID_CPUB_CLK_DYN0_DIV << 230 #define CLKID_CPUB_CLK_DYN0 << 231 #define CLKID_CPUB_CLK_DYN1_SEL << 232 #define CLKID_CPUB_CLK_DYN1_DIV << 233 #define CLKID_CPUB_CLK_DYN1 << 234 #define CLKID_CPUB_CLK_DYN << 235 #define CLKID_CPUB_CLK 140 #define CLKID_CPUB_CLK 224 236 #define CLKID_CPUB_CLK_DIV16_EN << 237 #define CLKID_CPUB_CLK_DIV16 << 238 #define CLKID_CPUB_CLK_DIV2 << 239 #define CLKID_CPUB_CLK_DIV3 << 240 #define CLKID_CPUB_CLK_DIV4 << 241 #define CLKID_CPUB_CLK_DIV5 << 242 #define CLKID_CPUB_CLK_DIV6 << 243 #define CLKID_CPUB_CLK_DIV7 << 244 #define CLKID_CPUB_CLK_DIV8 << 245 #define CLKID_CPUB_CLK_APB_SEL << 246 #define CLKID_CPUB_CLK_APB << 247 #define CLKID_CPUB_CLK_ATB_SEL << 248 #define CLKID_CPUB_CLK_ATB << 249 #define CLKID_CPUB_CLK_AXI_SEL << 250 #define CLKID_CPUB_CLK_AXI << 251 #define CLKID_CPUB_CLK_TRACE_SEL << 252 #define CLKID_CPUB_CLK_TRACE << 253 #define CLKID_GP1_PLL_DCO << 254 #define CLKID_GP1_PLL 141 #define CLKID_GP1_PLL 243 255 #define CLKID_DSU_CLK_DYN0_SEL << 256 #define CLKID_DSU_CLK_DYN0_DIV << 257 #define CLKID_DSU_CLK_DYN0 << 258 #define CLKID_DSU_CLK_DYN1_SEL << 259 #define CLKID_DSU_CLK_DYN1_DIV << 260 #define CLKID_DSU_CLK_DYN1 << 261 #define CLKID_DSU_CLK_DYN << 262 #define CLKID_DSU_CLK_FINAL << 263 #define CLKID_DSU_CLK 142 #define CLKID_DSU_CLK 252 264 #define CLKID_CPU1_CLK 143 #define CLKID_CPU1_CLK 253 265 #define CLKID_CPU2_CLK 144 #define CLKID_CPU2_CLK 254 266 #define CLKID_CPU3_CLK 145 #define CLKID_CPU3_CLK 255 267 #define CLKID_SPICC0_SCLK_SEL << 268 #define CLKID_SPICC0_SCLK_DIV << 269 #define CLKID_SPICC0_SCLK 146 #define CLKID_SPICC0_SCLK 258 270 #define CLKID_SPICC1_SCLK_SEL << 271 #define CLKID_SPICC1_SCLK_DIV << 272 #define CLKID_SPICC1_SCLK 147 #define CLKID_SPICC1_SCLK 261 273 #define CLKID_NNA_AXI_CLK_SEL << 274 #define CLKID_NNA_AXI_CLK_DIV << 275 #define CLKID_NNA_AXI_CLK 148 #define CLKID_NNA_AXI_CLK 264 276 #define CLKID_NNA_CORE_CLK_SEL << 277 #define CLKID_NNA_CORE_CLK_DIV << 278 #define CLKID_NNA_CORE_CLK 149 #define CLKID_NNA_CORE_CLK 267 279 #define CLKID_MIPI_DSI_PXCLK_DIV << 280 #define CLKID_MIPI_DSI_PXCLK_SEL 150 #define CLKID_MIPI_DSI_PXCLK_SEL 269 281 #define CLKID_MIPI_DSI_PXCLK 151 #define CLKID_MIPI_DSI_PXCLK 270 282 #define CLKID_CTS_ENCL << 283 #define CLKID_CTS_ENCL_SEL << 284 #define CLKID_MIPI_ISP_DIV << 285 #define CLKID_MIPI_ISP_SEL << 286 #define CLKID_MIPI_ISP << 287 #define CLKID_MIPI_ISP_GATE << 288 #define CLKID_MIPI_ISP_CSI_PHY0 << 289 #define CLKID_MIPI_ISP_CSI_PHY1 << 290 152 291 #endif /* __G12A_CLKC_H */ 153 #endif /* __G12A_CLKC_H */ 292 154
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