1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) 2012-2013 Hisilicon Limited. 2 * Copyright (c) 2012-2013 Hisilicon Limited.
4 * Copyright (c) 2012-2013 Linaro Limited. 3 * Copyright (c) 2012-2013 Linaro Limited.
5 * 4 *
6 * Author: Haojian Zhuang <haojian.zhuang@lina 5 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
7 * Xin Li <li.xin@linaro.org> 6 * Xin Li <li.xin@linaro.org>
>> 7 *
>> 8 * This program is free software; you can redistribute it and/or modify
>> 9 * it under the terms of the GNU General Public License as published by
>> 10 * the Free Software Foundation; either version 2 of the License, or
>> 11 * (at your option) any later version.
>> 12 *
>> 13 * This program is distributed in the hope that it will be useful,
>> 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 16 * GNU General Public License for more details.
>> 17 *
>> 18 * You should have received a copy of the GNU General Public License along
>> 19 * with this program; if not, write to the Free Software Foundation, Inc.,
>> 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>> 21 *
8 */ 22 */
9 23
10 #ifndef __DTS_HI3620_CLOCK_H 24 #ifndef __DTS_HI3620_CLOCK_H
11 #define __DTS_HI3620_CLOCK_H 25 #define __DTS_HI3620_CLOCK_H
12 26
13 #define HI3620_NONE_CLOCK 0 27 #define HI3620_NONE_CLOCK 0
14 28
15 /* fixed rate & fixed factor clocks */ 29 /* fixed rate & fixed factor clocks */
16 #define HI3620_OSC32K 1 30 #define HI3620_OSC32K 1
17 #define HI3620_OSC26M 2 31 #define HI3620_OSC26M 2
18 #define HI3620_PCLK 3 32 #define HI3620_PCLK 3
19 #define HI3620_PLL_ARM0 4 33 #define HI3620_PLL_ARM0 4
20 #define HI3620_PLL_ARM1 5 34 #define HI3620_PLL_ARM1 5
21 #define HI3620_PLL_PERI 6 35 #define HI3620_PLL_PERI 6
22 #define HI3620_PLL_USB 7 36 #define HI3620_PLL_USB 7
23 #define HI3620_PLL_HDMI 8 37 #define HI3620_PLL_HDMI 8
24 #define HI3620_PLL_GPU 9 38 #define HI3620_PLL_GPU 9
25 #define HI3620_RCLK_TCXO 10 39 #define HI3620_RCLK_TCXO 10
26 #define HI3620_RCLK_CFGAXI 11 40 #define HI3620_RCLK_CFGAXI 11
27 #define HI3620_RCLK_PICO 12 41 #define HI3620_RCLK_PICO 12
28 42
29 /* mux clocks */ 43 /* mux clocks */
30 #define HI3620_TIMER0_MUX 32 44 #define HI3620_TIMER0_MUX 32
31 #define HI3620_TIMER1_MUX 33 45 #define HI3620_TIMER1_MUX 33
32 #define HI3620_TIMER2_MUX 34 46 #define HI3620_TIMER2_MUX 34
33 #define HI3620_TIMER3_MUX 35 47 #define HI3620_TIMER3_MUX 35
34 #define HI3620_TIMER4_MUX 36 48 #define HI3620_TIMER4_MUX 36
35 #define HI3620_TIMER5_MUX 37 49 #define HI3620_TIMER5_MUX 37
36 #define HI3620_TIMER6_MUX 38 50 #define HI3620_TIMER6_MUX 38
37 #define HI3620_TIMER7_MUX 39 51 #define HI3620_TIMER7_MUX 39
38 #define HI3620_TIMER8_MUX 40 52 #define HI3620_TIMER8_MUX 40
39 #define HI3620_TIMER9_MUX 41 53 #define HI3620_TIMER9_MUX 41
40 #define HI3620_UART0_MUX 42 54 #define HI3620_UART0_MUX 42
41 #define HI3620_UART1_MUX 43 55 #define HI3620_UART1_MUX 43
42 #define HI3620_UART2_MUX 44 56 #define HI3620_UART2_MUX 44
43 #define HI3620_UART3_MUX 45 57 #define HI3620_UART3_MUX 45
44 #define HI3620_UART4_MUX 46 58 #define HI3620_UART4_MUX 46
45 #define HI3620_SPI0_MUX 47 59 #define HI3620_SPI0_MUX 47
46 #define HI3620_SPI1_MUX 48 60 #define HI3620_SPI1_MUX 48
47 #define HI3620_SPI2_MUX 49 61 #define HI3620_SPI2_MUX 49
48 #define HI3620_SAXI_MUX 50 62 #define HI3620_SAXI_MUX 50
49 #define HI3620_PWM0_MUX 51 63 #define HI3620_PWM0_MUX 51
50 #define HI3620_PWM1_MUX 52 64 #define HI3620_PWM1_MUX 52
51 #define HI3620_SD_MUX 53 65 #define HI3620_SD_MUX 53
52 #define HI3620_MMC1_MUX 54 66 #define HI3620_MMC1_MUX 54
53 #define HI3620_MMC1_MUX2 55 67 #define HI3620_MMC1_MUX2 55
54 #define HI3620_G2D_MUX 56 68 #define HI3620_G2D_MUX 56
55 #define HI3620_VENC_MUX 57 69 #define HI3620_VENC_MUX 57
56 #define HI3620_VDEC_MUX 58 70 #define HI3620_VDEC_MUX 58
57 #define HI3620_VPP_MUX 59 71 #define HI3620_VPP_MUX 59
58 #define HI3620_EDC0_MUX 60 72 #define HI3620_EDC0_MUX 60
59 #define HI3620_LDI0_MUX 61 73 #define HI3620_LDI0_MUX 61
60 #define HI3620_EDC1_MUX 62 74 #define HI3620_EDC1_MUX 62
61 #define HI3620_LDI1_MUX 63 75 #define HI3620_LDI1_MUX 63
62 #define HI3620_RCLK_HSIC 64 76 #define HI3620_RCLK_HSIC 64
63 #define HI3620_MMC2_MUX 65 77 #define HI3620_MMC2_MUX 65
64 #define HI3620_MMC3_MUX 66 78 #define HI3620_MMC3_MUX 66
65 79
66 /* divider clocks */ 80 /* divider clocks */
67 #define HI3620_SHAREAXI_DIV 128 81 #define HI3620_SHAREAXI_DIV 128
68 #define HI3620_CFGAXI_DIV 129 82 #define HI3620_CFGAXI_DIV 129
69 #define HI3620_SD_DIV 130 83 #define HI3620_SD_DIV 130
70 #define HI3620_MMC1_DIV 131 84 #define HI3620_MMC1_DIV 131
71 #define HI3620_HSIC_DIV 132 85 #define HI3620_HSIC_DIV 132
72 #define HI3620_MMC2_DIV 133 86 #define HI3620_MMC2_DIV 133
73 #define HI3620_MMC3_DIV 134 87 #define HI3620_MMC3_DIV 134
74 88
75 /* gate clocks */ 89 /* gate clocks */
76 #define HI3620_TIMERCLK01 160 90 #define HI3620_TIMERCLK01 160
77 #define HI3620_TIMER_RCLK01 161 91 #define HI3620_TIMER_RCLK01 161
78 #define HI3620_TIMERCLK23 162 92 #define HI3620_TIMERCLK23 162
79 #define HI3620_TIMER_RCLK23 163 93 #define HI3620_TIMER_RCLK23 163
80 #define HI3620_TIMERCLK45 164 94 #define HI3620_TIMERCLK45 164
81 #define HI3620_TIMERCLK67 165 95 #define HI3620_TIMERCLK67 165
82 #define HI3620_TIMERCLK89 166 96 #define HI3620_TIMERCLK89 166
83 #define HI3620_RTCCLK 167 97 #define HI3620_RTCCLK 167
84 #define HI3620_KPC_CLK 168 98 #define HI3620_KPC_CLK 168
85 #define HI3620_GPIOCLK0 169 99 #define HI3620_GPIOCLK0 169
86 #define HI3620_GPIOCLK1 170 100 #define HI3620_GPIOCLK1 170
87 #define HI3620_GPIOCLK2 171 101 #define HI3620_GPIOCLK2 171
88 #define HI3620_GPIOCLK3 172 102 #define HI3620_GPIOCLK3 172
89 #define HI3620_GPIOCLK4 173 103 #define HI3620_GPIOCLK4 173
90 #define HI3620_GPIOCLK5 174 104 #define HI3620_GPIOCLK5 174
91 #define HI3620_GPIOCLK6 175 105 #define HI3620_GPIOCLK6 175
92 #define HI3620_GPIOCLK7 176 106 #define HI3620_GPIOCLK7 176
93 #define HI3620_GPIOCLK8 177 107 #define HI3620_GPIOCLK8 177
94 #define HI3620_GPIOCLK9 178 108 #define HI3620_GPIOCLK9 178
95 #define HI3620_GPIOCLK10 179 109 #define HI3620_GPIOCLK10 179
96 #define HI3620_GPIOCLK11 180 110 #define HI3620_GPIOCLK11 180
97 #define HI3620_GPIOCLK12 181 111 #define HI3620_GPIOCLK12 181
98 #define HI3620_GPIOCLK13 182 112 #define HI3620_GPIOCLK13 182
99 #define HI3620_GPIOCLK14 183 113 #define HI3620_GPIOCLK14 183
100 #define HI3620_GPIOCLK15 184 114 #define HI3620_GPIOCLK15 184
101 #define HI3620_GPIOCLK16 185 115 #define HI3620_GPIOCLK16 185
102 #define HI3620_GPIOCLK17 186 116 #define HI3620_GPIOCLK17 186
103 #define HI3620_GPIOCLK18 187 117 #define HI3620_GPIOCLK18 187
104 #define HI3620_GPIOCLK19 188 118 #define HI3620_GPIOCLK19 188
105 #define HI3620_GPIOCLK20 189 119 #define HI3620_GPIOCLK20 189
106 #define HI3620_GPIOCLK21 190 120 #define HI3620_GPIOCLK21 190
107 #define HI3620_DPHY0_CLK 191 121 #define HI3620_DPHY0_CLK 191
108 #define HI3620_DPHY1_CLK 192 122 #define HI3620_DPHY1_CLK 192
109 #define HI3620_DPHY2_CLK 193 123 #define HI3620_DPHY2_CLK 193
110 #define HI3620_USBPHY_CLK 194 124 #define HI3620_USBPHY_CLK 194
111 #define HI3620_ACP_CLK 195 125 #define HI3620_ACP_CLK 195
112 #define HI3620_PWMCLK0 196 126 #define HI3620_PWMCLK0 196
113 #define HI3620_PWMCLK1 197 127 #define HI3620_PWMCLK1 197
114 #define HI3620_UARTCLK0 198 128 #define HI3620_UARTCLK0 198
115 #define HI3620_UARTCLK1 199 129 #define HI3620_UARTCLK1 199
116 #define HI3620_UARTCLK2 200 130 #define HI3620_UARTCLK2 200
117 #define HI3620_UARTCLK3 201 131 #define HI3620_UARTCLK3 201
118 #define HI3620_UARTCLK4 202 132 #define HI3620_UARTCLK4 202
119 #define HI3620_SPICLK0 203 133 #define HI3620_SPICLK0 203
120 #define HI3620_SPICLK1 204 134 #define HI3620_SPICLK1 204
121 #define HI3620_SPICLK2 205 135 #define HI3620_SPICLK2 205
122 #define HI3620_I2CCLK0 206 136 #define HI3620_I2CCLK0 206
123 #define HI3620_I2CCLK1 207 137 #define HI3620_I2CCLK1 207
124 #define HI3620_I2CCLK2 208 138 #define HI3620_I2CCLK2 208
125 #define HI3620_I2CCLK3 209 139 #define HI3620_I2CCLK3 209
126 #define HI3620_SCI_CLK 210 140 #define HI3620_SCI_CLK 210
127 #define HI3620_DDRC_PER_CLK 211 141 #define HI3620_DDRC_PER_CLK 211
128 #define HI3620_DMAC_CLK 212 142 #define HI3620_DMAC_CLK 212
129 #define HI3620_USB2DVC_CLK 213 143 #define HI3620_USB2DVC_CLK 213
130 #define HI3620_SD_CLK 214 144 #define HI3620_SD_CLK 214
131 #define HI3620_MMC_CLK1 215 145 #define HI3620_MMC_CLK1 215
132 #define HI3620_MMC_CLK2 216 146 #define HI3620_MMC_CLK2 216
133 #define HI3620_MMC_CLK3 217 147 #define HI3620_MMC_CLK3 217
134 #define HI3620_MCU_CLK 218 148 #define HI3620_MCU_CLK 218
135 149
136 #define HI3620_SD_CIUCLK 0 150 #define HI3620_SD_CIUCLK 0
137 #define HI3620_MMC_CIUCLK1 1 151 #define HI3620_MMC_CIUCLK1 1
138 #define HI3620_MMC_CIUCLK2 2 152 #define HI3620_MMC_CIUCLK2 2
139 #define HI3620_MMC_CIUCLK3 3 153 #define HI3620_MMC_CIUCLK3 3
140 154
141 #define HI3620_NR_CLKS 219 155 #define HI3620_NR_CLKS 219
142 156
143 #endif /* __DTS_HI3620_CLOCK_H */ 157 #endif /* __DTS_HI3620_CLOCK_H */
144 158
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