1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) 2016 HiSilicon Technologies C 2 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License as published by
>> 6 * the Free Software Foundation; either version 2 of the License, or
>> 7 * (at your option) any later version.
>> 8 *
>> 9 * This program is distributed in the hope that it will be useful,
>> 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 12 * GNU General Public License for more details.
>> 13 *
>> 14 * You should have received a copy of the GNU General Public License
>> 15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
4 */ 16 */
5 17
6 #ifndef __DTS_HISTB_CLOCK_H 18 #ifndef __DTS_HISTB_CLOCK_H
7 #define __DTS_HISTB_CLOCK_H 19 #define __DTS_HISTB_CLOCK_H
8 20
9 /* clocks provided by core CRG */ 21 /* clocks provided by core CRG */
10 #define HISTB_OSC_CLK 0 22 #define HISTB_OSC_CLK 0
11 #define HISTB_APB_CLK 1 23 #define HISTB_APB_CLK 1
12 #define HISTB_AHB_CLK 2 24 #define HISTB_AHB_CLK 2
13 #define HISTB_UART1_CLK 3 !! 25 #define HISTB_UART1_CLK 3
14 #define HISTB_UART2_CLK 4 !! 26 #define HISTB_UART2_CLK 4
15 #define HISTB_UART3_CLK 5 !! 27 #define HISTB_UART3_CLK 5
16 #define HISTB_I2C0_CLK 6 !! 28 #define HISTB_I2C0_CLK 6
17 #define HISTB_I2C1_CLK 7 !! 29 #define HISTB_I2C1_CLK 7
18 #define HISTB_I2C2_CLK 8 !! 30 #define HISTB_I2C2_CLK 8
19 #define HISTB_I2C3_CLK 9 !! 31 #define HISTB_I2C3_CLK 9
20 #define HISTB_I2C4_CLK 10 !! 32 #define HISTB_I2C4_CLK 10
21 #define HISTB_I2C5_CLK 11 !! 33 #define HISTB_I2C5_CLK 11
22 #define HISTB_SPI0_CLK 12 !! 34 #define HISTB_SPI0_CLK 12
23 #define HISTB_SPI1_CLK 13 !! 35 #define HISTB_SPI1_CLK 13
24 #define HISTB_SPI2_CLK 14 !! 36 #define HISTB_SPI2_CLK 14
25 #define HISTB_SCI_CLK 15 37 #define HISTB_SCI_CLK 15
26 #define HISTB_FMC_CLK 16 38 #define HISTB_FMC_CLK 16
27 #define HISTB_MMC_BIU_CLK 17 39 #define HISTB_MMC_BIU_CLK 17
28 #define HISTB_MMC_CIU_CLK 18 40 #define HISTB_MMC_CIU_CLK 18
29 #define HISTB_MMC_DRV_CLK 19 41 #define HISTB_MMC_DRV_CLK 19
30 #define HISTB_MMC_SAMPLE_CLK 20 42 #define HISTB_MMC_SAMPLE_CLK 20
31 #define HISTB_SDIO0_BIU_CLK 21 43 #define HISTB_SDIO0_BIU_CLK 21
32 #define HISTB_SDIO0_CIU_CLK 22 44 #define HISTB_SDIO0_CIU_CLK 22
33 #define HISTB_SDIO0_DRV_CLK 23 45 #define HISTB_SDIO0_DRV_CLK 23
34 #define HISTB_SDIO0_SAMPLE_CLK 24 !! 46 #define HISTB_SDIO0_SAMPLE_CLK 24
35 #define HISTB_PCIE_AUX_CLK 25 47 #define HISTB_PCIE_AUX_CLK 25
36 #define HISTB_PCIE_PIPE_CLK 26 48 #define HISTB_PCIE_PIPE_CLK 26
37 #define HISTB_PCIE_SYS_CLK 27 49 #define HISTB_PCIE_SYS_CLK 27
38 #define HISTB_PCIE_BUS_CLK 28 50 #define HISTB_PCIE_BUS_CLK 28
39 #define HISTB_ETH0_MAC_CLK 29 51 #define HISTB_ETH0_MAC_CLK 29
40 #define HISTB_ETH0_MACIF_CLK 30 52 #define HISTB_ETH0_MACIF_CLK 30
41 #define HISTB_ETH1_MAC_CLK 31 53 #define HISTB_ETH1_MAC_CLK 31
42 #define HISTB_ETH1_MACIF_CLK 32 54 #define HISTB_ETH1_MACIF_CLK 32
43 #define HISTB_COMBPHY1_CLK 33 55 #define HISTB_COMBPHY1_CLK 33
44 #define HISTB_USB2_BUS_CLK 34 !! 56 #define HISTB_USB2_BUS_CLK 34
45 #define HISTB_USB2_PHY_CLK 35 !! 57 #define HISTB_USB2_PHY_CLK 35
46 #define HISTB_USB2_UTMI_CLK 36 !! 58 #define HISTB_USB2_UTMI_CLK 36
47 #define HISTB_USB2_12M_CLK 37 !! 59 #define HISTB_USB2_12M_CLK 37
48 #define HISTB_USB2_48M_CLK 38 !! 60 #define HISTB_USB2_48M_CLK 38
49 #define HISTB_USB2_OTG_UTMI_CLK 39 !! 61 #define HISTB_USB2_OTG_UTMI_CLK 39
50 #define HISTB_USB2_PHY1_REF_CLK 40 !! 62 #define HISTB_USB2_PHY1_REF_CLK 40
51 #define HISTB_USB2_PHY2_REF_CLK 41 !! 63 #define HISTB_USB2_PHY2_REF_CLK 41
52 #define HISTB_COMBPHY0_CLK 42 <<
53 #define HISTB_USB3_BUS_CLK 43 <<
54 #define HISTB_USB3_UTMI_CLK 44 <<
55 #define HISTB_USB3_PIPE_CLK 45 <<
56 #define HISTB_USB3_SUSPEND_CLK 46 <<
57 #define HISTB_USB3_BUS_CLK1 47 <<
58 #define HISTB_USB3_UTMI_CLK1 48 <<
59 #define HISTB_USB3_PIPE_CLK1 49 <<
60 #define HISTB_USB3_SUSPEND_CLK1 50 <<
61 64
62 /* clocks provided by mcu CRG */ 65 /* clocks provided by mcu CRG */
63 #define HISTB_MCE_CLK 1 !! 66 #define HISTB_MCE_CLK 1
64 #define HISTB_IR_CLK 2 !! 67 #define HISTB_IR_CLK 2
65 #define HISTB_TIMER01_CLK 3 !! 68 #define HISTB_TIMER01_CLK 3
66 #define HISTB_LEDC_CLK 4 !! 69 #define HISTB_LEDC_CLK 4
67 #define HISTB_UART0_CLK 5 !! 70 #define HISTB_UART0_CLK 5
68 #define HISTB_LSADC_CLK 6 !! 71 #define HISTB_LSADC_CLK 6
69 72
70 #endif /* __DTS_HISTB_CLOCK_H */ 73 #endif /* __DTS_HISTB_CLOCK_H */
71 74
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