1 /* SPDX-License-Identifier: GPL-2.0-only OR MI 1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 /* 2 /* 3 * Copyright 2024 NXP 3 * Copyright 2024 NXP 4 */ 4 */ 5 5 6 #ifndef __DT_BINDINGS_CLOCK_IMX95_H 6 #ifndef __DT_BINDINGS_CLOCK_IMX95_H 7 #define __DT_BINDINGS_CLOCK_IMX95_H 7 #define __DT_BINDINGS_CLOCK_IMX95_H 8 8 9 #define IMX95_CLK_VPUBLK_WAVE 9 #define IMX95_CLK_VPUBLK_WAVE 0 10 #define IMX95_CLK_VPUBLK_JPEG_ENC 10 #define IMX95_CLK_VPUBLK_JPEG_ENC 1 11 #define IMX95_CLK_VPUBLK_JPEG_DEC 11 #define IMX95_CLK_VPUBLK_JPEG_DEC 2 12 12 13 #define IMX95_CLK_CAMBLK_CSI2_FOR0 13 #define IMX95_CLK_CAMBLK_CSI2_FOR0 0 14 #define IMX95_CLK_CAMBLK_CSI2_FOR1 14 #define IMX95_CLK_CAMBLK_CSI2_FOR1 1 15 #define IMX95_CLK_CAMBLK_ISP_AXI 15 #define IMX95_CLK_CAMBLK_ISP_AXI 2 16 #define IMX95_CLK_CAMBLK_ISP_PIXEL 16 #define IMX95_CLK_CAMBLK_ISP_PIXEL 3 17 #define IMX95_CLK_CAMBLK_ISP 17 #define IMX95_CLK_CAMBLK_ISP 4 18 18 19 #define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 19 #define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0 20 #define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 20 #define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1 21 #define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 21 #define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2 22 #define IMX95_CLK_DISPMIX_PIX_DI0_GATE 22 #define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3 23 #define IMX95_CLK_DISPMIX_PIX_DI1_GATE 23 #define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4 24 24 25 #define IMX95_CLK_DISPMIX_ENG0_SEL 25 #define IMX95_CLK_DISPMIX_ENG0_SEL 0 26 #define IMX95_CLK_DISPMIX_ENG1_SEL 26 #define IMX95_CLK_DISPMIX_ENG1_SEL 1 27 27 28 #define IMX95_CLK_NETCMIX_ENETC0_RMII 28 #define IMX95_CLK_NETCMIX_ENETC0_RMII 0 29 #define IMX95_CLK_NETCMIX_ENETC1_RMII 29 #define IMX95_CLK_NETCMIX_ENETC1_RMII 1 30 30 31 #endif /* __DT_BINDINGS_CLOCK_IMX95_H */ 31 #endif /* __DT_BINDINGS_CLOCK_IMX95_H */ 32 32
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