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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/dt-bindings/clock/omap5.h

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Diff markup

Differences between /scripts/dtc/include-prefixes/dt-bindings/clock/omap5.h (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/dt-bindings/clock/omap5.h (Version linux-4.17.19)


  1 /* SPDX-License-Identifier: GPL-2.0-only */    << 
  2 /*                                                  1 /*
  3  * Copyright 2017 Texas Instruments, Inc.           2  * Copyright 2017 Texas Instruments, Inc.
                                                   >>   3  *
                                                   >>   4  * This software is licensed under the terms of the GNU General Public
                                                   >>   5  * License version 2, as published by the Free Software Foundation, and
                                                   >>   6  * may be copied, distributed, and modified under those terms.
                                                   >>   7  *
                                                   >>   8  * This program is distributed in the hope that it will be useful,
                                                   >>   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
                                                   >>  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
                                                   >>  11  * GNU General Public License for more details.
  4  */                                                12  */
  5 #ifndef __DT_BINDINGS_CLK_OMAP5_H                  13 #ifndef __DT_BINDINGS_CLK_OMAP5_H
  6 #define __DT_BINDINGS_CLK_OMAP5_H                  14 #define __DT_BINDINGS_CLK_OMAP5_H
  7                                                    15 
  8 #define OMAP5_CLKCTRL_OFFSET    0x20               16 #define OMAP5_CLKCTRL_OFFSET    0x20
  9 #define OMAP5_CLKCTRL_INDEX(offset)     ((offs     17 #define OMAP5_CLKCTRL_INDEX(offset)     ((offset) - OMAP5_CLKCTRL_OFFSET)
 10                                                    18 
 11 /* mpu clocks */                                   19 /* mpu clocks */
 12 #define OMAP5_MPU_CLKCTRL       OMAP5_CLKCTRL_     20 #define OMAP5_MPU_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x20)
 13                                                    21 
 14 /* dsp clocks */                                   22 /* dsp clocks */
 15 #define OMAP5_MMU_DSP_CLKCTRL   OMAP5_CLKCTRL_     23 #define OMAP5_MMU_DSP_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x20)
 16                                                    24 
 17 /* abe clocks */                                   25 /* abe clocks */
 18 #define OMAP5_L4_ABE_CLKCTRL    OMAP5_CLKCTRL_     26 #define OMAP5_L4_ABE_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x20)
 19 #define OMAP5_AESS_CLKCTRL      OMAP5_CLKCTRL_ << 
 20 #define OMAP5_MCPDM_CLKCTRL     OMAP5_CLKCTRL_     27 #define OMAP5_MCPDM_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x30)
 21 #define OMAP5_DMIC_CLKCTRL      OMAP5_CLKCTRL_     28 #define OMAP5_DMIC_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x38)
 22 #define OMAP5_MCBSP1_CLKCTRL    OMAP5_CLKCTRL_     29 #define OMAP5_MCBSP1_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x48)
 23 #define OMAP5_MCBSP2_CLKCTRL    OMAP5_CLKCTRL_     30 #define OMAP5_MCBSP2_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x50)
 24 #define OMAP5_MCBSP3_CLKCTRL    OMAP5_CLKCTRL_     31 #define OMAP5_MCBSP3_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x58)
 25 #define OMAP5_TIMER5_CLKCTRL    OMAP5_CLKCTRL_     32 #define OMAP5_TIMER5_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x68)
 26 #define OMAP5_TIMER6_CLKCTRL    OMAP5_CLKCTRL_     33 #define OMAP5_TIMER6_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x70)
 27 #define OMAP5_TIMER7_CLKCTRL    OMAP5_CLKCTRL_     34 #define OMAP5_TIMER7_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x78)
 28 #define OMAP5_TIMER8_CLKCTRL    OMAP5_CLKCTRL_     35 #define OMAP5_TIMER8_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x80)
 29                                                    36 
 30 /* l3main1 clocks */                               37 /* l3main1 clocks */
 31 #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_     38 #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
 32                                                    39 
 33 /* l3main2 clocks */                               40 /* l3main2 clocks */
 34 #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_     41 #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
 35 #define OMAP5_L3_MAIN_2_GPMC_CLKCTRL    OMAP5_ << 
 36 #define OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL       << 
 37                                                    42 
 38 /* ipu clocks */                                   43 /* ipu clocks */
 39 #define OMAP5_MMU_IPU_CLKCTRL   OMAP5_CLKCTRL_     44 #define OMAP5_MMU_IPU_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x20)
 40                                                    45 
 41 /* dma clocks */                                   46 /* dma clocks */
 42 #define OMAP5_DMA_SYSTEM_CLKCTRL        OMAP5_     47 #define OMAP5_DMA_SYSTEM_CLKCTRL        OMAP5_CLKCTRL_INDEX(0x20)
 43                                                    48 
 44 /* emif clocks */                                  49 /* emif clocks */
 45 #define OMAP5_DMM_CLKCTRL       OMAP5_CLKCTRL_     50 #define OMAP5_DMM_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x20)
 46 #define OMAP5_EMIF1_CLKCTRL     OMAP5_CLKCTRL_     51 #define OMAP5_EMIF1_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x30)
 47 #define OMAP5_EMIF2_CLKCTRL     OMAP5_CLKCTRL_     52 #define OMAP5_EMIF2_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x38)
 48                                                    53 
 49 /* l4cfg clocks */                                 54 /* l4cfg clocks */
 50 #define OMAP5_L4_CFG_CLKCTRL    OMAP5_CLKCTRL_     55 #define OMAP5_L4_CFG_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x20)
 51 #define OMAP5_SPINLOCK_CLKCTRL  OMAP5_CLKCTRL_     56 #define OMAP5_SPINLOCK_CLKCTRL  OMAP5_CLKCTRL_INDEX(0x28)
 52 #define OMAP5_MAILBOX_CLKCTRL   OMAP5_CLKCTRL_     57 #define OMAP5_MAILBOX_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x30)
 53                                                    58 
 54 /* l3instr clocks */                               59 /* l3instr clocks */
 55 #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_     60 #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
 56 #define OMAP5_L3_INSTR_CLKCTRL  OMAP5_CLKCTRL_     61 #define OMAP5_L3_INSTR_CLKCTRL  OMAP5_CLKCTRL_INDEX(0x28)
 57                                                    62 
 58 /* l4per clocks */                                 63 /* l4per clocks */
 59 #define OMAP5_TIMER10_CLKCTRL   OMAP5_CLKCTRL_     64 #define OMAP5_TIMER10_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x28)
 60 #define OMAP5_TIMER11_CLKCTRL   OMAP5_CLKCTRL_     65 #define OMAP5_TIMER11_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x30)
 61 #define OMAP5_TIMER2_CLKCTRL    OMAP5_CLKCTRL_     66 #define OMAP5_TIMER2_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x38)
 62 #define OMAP5_TIMER3_CLKCTRL    OMAP5_CLKCTRL_     67 #define OMAP5_TIMER3_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x40)
 63 #define OMAP5_TIMER4_CLKCTRL    OMAP5_CLKCTRL_     68 #define OMAP5_TIMER4_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x48)
 64 #define OMAP5_TIMER9_CLKCTRL    OMAP5_CLKCTRL_     69 #define OMAP5_TIMER9_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x50)
 65 #define OMAP5_GPIO2_CLKCTRL     OMAP5_CLKCTRL_     70 #define OMAP5_GPIO2_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x60)
 66 #define OMAP5_GPIO3_CLKCTRL     OMAP5_CLKCTRL_     71 #define OMAP5_GPIO3_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x68)
 67 #define OMAP5_GPIO4_CLKCTRL     OMAP5_CLKCTRL_     72 #define OMAP5_GPIO4_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x70)
 68 #define OMAP5_GPIO5_CLKCTRL     OMAP5_CLKCTRL_     73 #define OMAP5_GPIO5_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x78)
 69 #define OMAP5_GPIO6_CLKCTRL     OMAP5_CLKCTRL_     74 #define OMAP5_GPIO6_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x80)
 70 #define OMAP5_I2C1_CLKCTRL      OMAP5_CLKCTRL_     75 #define OMAP5_I2C1_CLKCTRL      OMAP5_CLKCTRL_INDEX(0xa0)
 71 #define OMAP5_I2C2_CLKCTRL      OMAP5_CLKCTRL_     76 #define OMAP5_I2C2_CLKCTRL      OMAP5_CLKCTRL_INDEX(0xa8)
 72 #define OMAP5_I2C3_CLKCTRL      OMAP5_CLKCTRL_     77 #define OMAP5_I2C3_CLKCTRL      OMAP5_CLKCTRL_INDEX(0xb0)
 73 #define OMAP5_I2C4_CLKCTRL      OMAP5_CLKCTRL_     78 #define OMAP5_I2C4_CLKCTRL      OMAP5_CLKCTRL_INDEX(0xb8)
 74 #define OMAP5_L4_PER_CLKCTRL    OMAP5_CLKCTRL_     79 #define OMAP5_L4_PER_CLKCTRL    OMAP5_CLKCTRL_INDEX(0xc0)
 75 #define OMAP5_MCSPI1_CLKCTRL    OMAP5_CLKCTRL_     80 #define OMAP5_MCSPI1_CLKCTRL    OMAP5_CLKCTRL_INDEX(0xf0)
 76 #define OMAP5_MCSPI2_CLKCTRL    OMAP5_CLKCTRL_     81 #define OMAP5_MCSPI2_CLKCTRL    OMAP5_CLKCTRL_INDEX(0xf8)
 77 #define OMAP5_MCSPI3_CLKCTRL    OMAP5_CLKCTRL_     82 #define OMAP5_MCSPI3_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x100)
 78 #define OMAP5_MCSPI4_CLKCTRL    OMAP5_CLKCTRL_     83 #define OMAP5_MCSPI4_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x108)
 79 #define OMAP5_GPIO7_CLKCTRL     OMAP5_CLKCTRL_     84 #define OMAP5_GPIO7_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x110)
 80 #define OMAP5_GPIO8_CLKCTRL     OMAP5_CLKCTRL_     85 #define OMAP5_GPIO8_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x118)
 81 #define OMAP5_MMC3_CLKCTRL      OMAP5_CLKCTRL_     86 #define OMAP5_MMC3_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x120)
 82 #define OMAP5_MMC4_CLKCTRL      OMAP5_CLKCTRL_     87 #define OMAP5_MMC4_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x128)
 83 #define OMAP5_UART1_CLKCTRL     OMAP5_CLKCTRL_     88 #define OMAP5_UART1_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x140)
 84 #define OMAP5_UART2_CLKCTRL     OMAP5_CLKCTRL_     89 #define OMAP5_UART2_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x148)
 85 #define OMAP5_UART3_CLKCTRL     OMAP5_CLKCTRL_     90 #define OMAP5_UART3_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x150)
 86 #define OMAP5_UART4_CLKCTRL     OMAP5_CLKCTRL_     91 #define OMAP5_UART4_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x158)
 87 #define OMAP5_MMC5_CLKCTRL      OMAP5_CLKCTRL_     92 #define OMAP5_MMC5_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x160)
 88 #define OMAP5_I2C5_CLKCTRL      OMAP5_CLKCTRL_     93 #define OMAP5_I2C5_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x168)
 89 #define OMAP5_UART5_CLKCTRL     OMAP5_CLKCTRL_     94 #define OMAP5_UART5_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x170)
 90 #define OMAP5_UART6_CLKCTRL     OMAP5_CLKCTRL_     95 #define OMAP5_UART6_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x178)
 91                                                    96 
 92 /* l4_secure clocks */                         << 
 93 #define OMAP5_L4_SECURE_CLKCTRL_OFFSET  0x1a0  << 
 94 #define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset)  << 
 95 #define OMAP5_AES1_CLKCTRL      OMAP5_L4_SECUR << 
 96 #define OMAP5_AES2_CLKCTRL      OMAP5_L4_SECUR << 
 97 #define OMAP5_DES3DES_CLKCTRL   OMAP5_L4_SECUR << 
 98 #define OMAP5_FPKA_CLKCTRL      OMAP5_L4_SECUR << 
 99 #define OMAP5_RNG_CLKCTRL       OMAP5_L4_SECUR << 
100 #define OMAP5_SHA2MD5_CLKCTRL   OMAP5_L4_SECUR << 
101 #define OMAP5_DMA_CRYPTO_CLKCTRL        OMAP5_ << 
102                                                << 
103 /* iva clocks */                               << 
104 #define OMAP5_IVA_CLKCTRL       OMAP5_CLKCTRL_ << 
105 #define OMAP5_SL2IF_CLKCTRL     OMAP5_CLKCTRL_ << 
106                                                << 
107 /* dss clocks */                                   97 /* dss clocks */
108 #define OMAP5_DSS_CORE_CLKCTRL  OMAP5_CLKCTRL_     98 #define OMAP5_DSS_CORE_CLKCTRL  OMAP5_CLKCTRL_INDEX(0x20)
109                                                << 
110 /* gpu clocks */                               << 
111 #define OMAP5_GPU_CLKCTRL       OMAP5_CLKCTRL_ << 
112                                                    99 
113 /* l3init clocks */                               100 /* l3init clocks */
114 #define OMAP5_MMC1_CLKCTRL      OMAP5_CLKCTRL_    101 #define OMAP5_MMC1_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x28)
115 #define OMAP5_MMC2_CLKCTRL      OMAP5_CLKCTRL_    102 #define OMAP5_MMC2_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x30)
116 #define OMAP5_USB_HOST_HS_CLKCTRL       OMAP5_    103 #define OMAP5_USB_HOST_HS_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x58)
117 #define OMAP5_USB_TLL_HS_CLKCTRL        OMAP5_    104 #define OMAP5_USB_TLL_HS_CLKCTRL        OMAP5_CLKCTRL_INDEX(0x68)
118 #define OMAP5_SATA_CLKCTRL      OMAP5_CLKCTRL_    105 #define OMAP5_SATA_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x88)
119 #define OMAP5_OCP2SCP1_CLKCTRL  OMAP5_CLKCTRL_    106 #define OMAP5_OCP2SCP1_CLKCTRL  OMAP5_CLKCTRL_INDEX(0xe0)
120 #define OMAP5_OCP2SCP3_CLKCTRL  OMAP5_CLKCTRL_    107 #define OMAP5_OCP2SCP3_CLKCTRL  OMAP5_CLKCTRL_INDEX(0xe8)
121 #define OMAP5_USB_OTG_SS_CLKCTRL        OMAP5_    108 #define OMAP5_USB_OTG_SS_CLKCTRL        OMAP5_CLKCTRL_INDEX(0xf0)
122                                                   109 
123 /* wkupaon clocks */                              110 /* wkupaon clocks */
124 #define OMAP5_L4_WKUP_CLKCTRL   OMAP5_CLKCTRL_    111 #define OMAP5_L4_WKUP_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x20)
125 #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_    112 #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
126 #define OMAP5_GPIO1_CLKCTRL     OMAP5_CLKCTRL_    113 #define OMAP5_GPIO1_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x38)
127 #define OMAP5_TIMER1_CLKCTRL    OMAP5_CLKCTRL_    114 #define OMAP5_TIMER1_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x40)
128 #define OMAP5_COUNTER_32K_CLKCTRL       OMAP5_    115 #define OMAP5_COUNTER_32K_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x50)
129 #define OMAP5_KBD_CLKCTRL       OMAP5_CLKCTRL_    116 #define OMAP5_KBD_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x78)
130                                                   117 
131 #endif                                            118 #endif
132                                                   119 

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