1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright 2017 Texas Instruments, Inc. 4 */ 5 #ifndef __DT_BINDINGS_CLK_OMAP5_H 6 #define __DT_BINDINGS_CLK_OMAP5_H 7 8 #define OMAP5_CLKCTRL_OFFSET 0x20 9 #define OMAP5_CLKCTRL_INDEX(offset) ((offs 10 11 /* mpu clocks */ 12 #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_ 13 14 /* dsp clocks */ 15 #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_ 16 17 /* abe clocks */ 18 #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_ 19 #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_ 20 #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_ 21 #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_ 22 #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_ 23 #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_ 24 #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_ 25 #define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_ 26 #define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_ 27 #define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_ 28 #define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_ 29 30 /* l3main1 clocks */ 31 #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_ 32 33 /* l3main2 clocks */ 34 #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_ 35 #define OMAP5_L3_MAIN_2_GPMC_CLKCTRL OMAP5_ 36 #define OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL 37 38 /* ipu clocks */ 39 #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_ 40 41 /* dma clocks */ 42 #define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_ 43 44 /* emif clocks */ 45 #define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_ 46 #define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_ 47 #define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_ 48 49 /* l4cfg clocks */ 50 #define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_ 51 #define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_ 52 #define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_ 53 54 /* l3instr clocks */ 55 #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_ 56 #define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_ 57 58 /* l4per clocks */ 59 #define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_ 60 #define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_ 61 #define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_ 62 #define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_ 63 #define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_ 64 #define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_ 65 #define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_ 66 #define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_ 67 #define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_ 68 #define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_ 69 #define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_ 70 #define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_ 71 #define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_ 72 #define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_ 73 #define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_ 74 #define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_ 75 #define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_ 76 #define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_ 77 #define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_ 78 #define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_ 79 #define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_ 80 #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_ 81 #define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_ 82 #define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_ 83 #define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_ 84 #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_ 85 #define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_ 86 #define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_ 87 #define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_ 88 #define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_ 89 #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_ 90 #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_ 91 92 /* l4_secure clocks */ 93 #define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 94 #define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) 95 #define OMAP5_AES1_CLKCTRL OMAP5_L4_SECUR 96 #define OMAP5_AES2_CLKCTRL OMAP5_L4_SECUR 97 #define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECUR 98 #define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECUR 99 #define OMAP5_RNG_CLKCTRL OMAP5_L4_SECUR 100 #define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECUR 101 #define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_ 102 103 /* iva clocks */ 104 #define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_ 105 #define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_ 106 107 /* dss clocks */ 108 #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_ 109 110 /* gpu clocks */ 111 #define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_ 112 113 /* l3init clocks */ 114 #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_ 115 #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_ 116 #define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_ 117 #define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_ 118 #define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_ 119 #define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_ 120 #define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_ 121 #define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_ 122 123 /* wkupaon clocks */ 124 #define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_ 125 #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_ 126 #define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_ 127 #define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_ 128 #define OMAP5_COUNTER_32K_CLKCTRL OMAP5_ 129 #define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_ 130 131 #endif 132
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