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Linux/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm8450-videocc.h

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Diff markup

Differences between /scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm8450-videocc.h (Architecture i386) and /scripts/dtc/include-prefixes/dt-bindings/clock/qcom,sm8450-videocc.h (Architecture m68k)


  1 /* SPDX-License-Identifier: (GPL-2.0-only OR B      1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2 /*                                                  2 /*
  3  * Copyright (c) 2023, Qualcomm Innovation Cen      3  * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4  */                                                 4  */
  5                                                     5 
  6 #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_      6 #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
  7 #define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_      7 #define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
  8                                                     8 
  9 /* VIDEO_CC clocks */                               9 /* VIDEO_CC clocks */
 10 #define VIDEO_CC_MVS0_CLK                          10 #define VIDEO_CC_MVS0_CLK                                       0
 11 #define VIDEO_CC_MVS0_CLK_SRC                      11 #define VIDEO_CC_MVS0_CLK_SRC                                   1
 12 #define VIDEO_CC_MVS0_DIV_CLK_SRC                  12 #define VIDEO_CC_MVS0_DIV_CLK_SRC                               2
 13 #define VIDEO_CC_MVS0C_CLK                         13 #define VIDEO_CC_MVS0C_CLK                                      3
 14 #define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC            14 #define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC                         4
 15 #define VIDEO_CC_MVS1_CLK                          15 #define VIDEO_CC_MVS1_CLK                                       5
 16 #define VIDEO_CC_MVS1_CLK_SRC                      16 #define VIDEO_CC_MVS1_CLK_SRC                                   6
 17 #define VIDEO_CC_MVS1_DIV_CLK_SRC                  17 #define VIDEO_CC_MVS1_DIV_CLK_SRC                               7
 18 #define VIDEO_CC_MVS1C_CLK                         18 #define VIDEO_CC_MVS1C_CLK                                      8
 19 #define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC            19 #define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC                         9
 20 #define VIDEO_CC_PLL0                              20 #define VIDEO_CC_PLL0                                           10
 21 #define VIDEO_CC_PLL1                              21 #define VIDEO_CC_PLL1                                           11
 22                                                    22 
 23 /* VIDEO_CC power domains */                       23 /* VIDEO_CC power domains */
 24 #define VIDEO_CC_MVS0C_GDSC                        24 #define VIDEO_CC_MVS0C_GDSC                                     0
 25 #define VIDEO_CC_MVS0_GDSC                         25 #define VIDEO_CC_MVS0_GDSC                                      1
 26 #define VIDEO_CC_MVS1C_GDSC                        26 #define VIDEO_CC_MVS1C_GDSC                                     2
 27 #define VIDEO_CC_MVS1_GDSC                         27 #define VIDEO_CC_MVS1_GDSC                                      3
 28                                                    28 
 29 /* VIDEO_CC resets */                              29 /* VIDEO_CC resets */
 30 #define CVP_VIDEO_CC_INTERFACE_BCR                 30 #define CVP_VIDEO_CC_INTERFACE_BCR                              0
 31 #define CVP_VIDEO_CC_MVS0_BCR                      31 #define CVP_VIDEO_CC_MVS0_BCR                                   1
 32 #define CVP_VIDEO_CC_MVS0C_BCR                     32 #define CVP_VIDEO_CC_MVS0C_BCR                                  2
 33 #define CVP_VIDEO_CC_MVS1_BCR                      33 #define CVP_VIDEO_CC_MVS1_BCR                                   3
 34 #define CVP_VIDEO_CC_MVS1C_BCR                     34 #define CVP_VIDEO_CC_MVS1C_BCR                                  4
 35 #define VIDEO_CC_MVS0C_CLK_ARES                    35 #define VIDEO_CC_MVS0C_CLK_ARES                                 5
 36 #define VIDEO_CC_MVS1C_CLK_ARES                    36 #define VIDEO_CC_MVS1C_CLK_ARES                                 6
 37                                                    37 
 38 #endif                                             38 #endif
 39                                                    39 

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