1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Cen 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 4 */ 5 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_ 6 #ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H 7 #define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_ 7 #define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H 8 8 9 /* GPU_CC clocks */ 9 /* GPU_CC clocks */ 10 #define GPU_CC_AHB_CLK 10 #define GPU_CC_AHB_CLK 0 11 #define GPU_CC_CB_CLK 11 #define GPU_CC_CB_CLK 1 12 #define GPU_CC_CRC_AHB_CLK 12 #define GPU_CC_CRC_AHB_CLK 2 13 #define GPU_CC_CX_FF_CLK 13 #define GPU_CC_CX_FF_CLK 3 14 #define GPU_CC_CX_GMU_CLK 14 #define GPU_CC_CX_GMU_CLK 4 15 #define GPU_CC_CXO_AON_CLK 15 #define GPU_CC_CXO_AON_CLK 5 16 #define GPU_CC_CXO_CLK 16 #define GPU_CC_CXO_CLK 6 17 #define GPU_CC_DEMET_CLK 17 #define GPU_CC_DEMET_CLK 7 18 #define GPU_CC_DEMET_DIV_CLK_SRC 18 #define GPU_CC_DEMET_DIV_CLK_SRC 8 19 #define GPU_CC_FF_CLK_SRC 19 #define GPU_CC_FF_CLK_SRC 9 20 #define GPU_CC_FREQ_MEASURE_CLK 20 #define GPU_CC_FREQ_MEASURE_CLK 10 21 #define GPU_CC_GMU_CLK_SRC 21 #define GPU_CC_GMU_CLK_SRC 11 22 #define GPU_CC_GX_GMU_CLK 22 #define GPU_CC_GX_GMU_CLK 12 23 #define GPU_CC_GX_VSENSE_CLK 23 #define GPU_CC_GX_VSENSE_CLK 13 24 #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 24 #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 25 #define GPU_CC_HUB_AON_CLK 25 #define GPU_CC_HUB_AON_CLK 15 26 #define GPU_CC_HUB_CLK_SRC 26 #define GPU_CC_HUB_CLK_SRC 16 27 #define GPU_CC_HUB_CX_INT_CLK 27 #define GPU_CC_HUB_CX_INT_CLK 17 28 #define GPU_CC_MEMNOC_GFX_CLK 28 #define GPU_CC_MEMNOC_GFX_CLK 18 29 #define GPU_CC_MND1X_0_GFX3D_CLK 29 #define GPU_CC_MND1X_0_GFX3D_CLK 19 30 #define GPU_CC_MND1X_1_GFX3D_CLK 30 #define GPU_CC_MND1X_1_GFX3D_CLK 20 31 #define GPU_CC_PLL0 31 #define GPU_CC_PLL0 21 32 #define GPU_CC_PLL1 32 #define GPU_CC_PLL1 22 33 #define GPU_CC_SLEEP_CLK 33 #define GPU_CC_SLEEP_CLK 23 34 #define GPU_CC_XO_CLK_SRC 34 #define GPU_CC_XO_CLK_SRC 24 35 #define GPU_CC_XO_DIV_CLK_SRC 35 #define GPU_CC_XO_DIV_CLK_SRC 25 36 36 37 /* GDSCs */ 37 /* GDSCs */ 38 #define GPU_CX_GDSC 38 #define GPU_CX_GDSC 0 39 #define GPU_GX_GDSC 39 #define GPU_GX_GDSC 1 40 40 41 #endif 41 #endif 42 42
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