1 /* SPDX-License-Identifier: GPL-2.0 1 2 * 3 * Copyright (C) 2018 Renesas Electronics Corp 4 */ 5 #ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H 6 #define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H 7 8 #include <dt-bindings/clock/renesas-cpg-mssr.h 9 10 /* r8a7744 CPG Core Clocks */ 11 #define R8A7744_CLK_Z 0 12 #define R8A7744_CLK_ZG 1 13 #define R8A7744_CLK_ZTR 2 14 #define R8A7744_CLK_ZTRD2 3 15 #define R8A7744_CLK_ZT 4 16 #define R8A7744_CLK_ZX 5 17 #define R8A7744_CLK_ZS 6 18 #define R8A7744_CLK_HP 7 19 #define R8A7744_CLK_B 9 20 #define R8A7744_CLK_LB 10 21 #define R8A7744_CLK_P 11 22 #define R8A7744_CLK_CL 12 23 #define R8A7744_CLK_M2 13 24 #define R8A7744_CLK_ZB3 15 25 #define R8A7744_CLK_ZB3D2 16 26 #define R8A7744_CLK_DDR 17 27 #define R8A7744_CLK_SDH 18 28 #define R8A7744_CLK_SD0 19 29 #define R8A7744_CLK_SD2 20 30 #define R8A7744_CLK_SD3 21 31 #define R8A7744_CLK_MMC0 22 32 #define R8A7744_CLK_MP 23 33 #define R8A7744_CLK_QSPI 26 34 #define R8A7744_CLK_CP 27 35 #define R8A7744_CLK_RCAN 28 36 #define R8A7744_CLK_R 29 37 #define R8A7744_CLK_OSC 30 38 39 #endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR 40
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