1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) 2015 Rockchip Electronics Co. 2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
4 * Author: Jeffy Chen <jeffy.chen@rock-chips.c 3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify
>> 6 * it under the terms of the GNU General Public License as published by
>> 7 * the Free Software Foundation; either version 2 of the License, or
>> 8 * (at your option) any later version.
>> 9 *
>> 10 * This program is distributed in the hope that it will be useful,
>> 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 13 * GNU General Public License for more details.
5 */ 14 */
6 15
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
9 18
10 /* core clocks */ 19 /* core clocks */
11 #define PLL_APLL 1 20 #define PLL_APLL 1
12 #define PLL_DPLL 2 21 #define PLL_DPLL 2
13 #define PLL_CPLL 3 22 #define PLL_CPLL 3
14 #define PLL_GPLL 4 23 #define PLL_GPLL 4
15 #define ARMCLK 5 24 #define ARMCLK 5
16 25
17 /* sclk gates (special clocks) */ 26 /* sclk gates (special clocks) */
18 #define SCLK_SPI0 65 27 #define SCLK_SPI0 65
19 #define SCLK_NANDC 67 28 #define SCLK_NANDC 67
20 #define SCLK_SDMMC 68 29 #define SCLK_SDMMC 68
21 #define SCLK_SDIO 69 30 #define SCLK_SDIO 69
22 #define SCLK_EMMC 71 31 #define SCLK_EMMC 71
23 #define SCLK_TSADC 72 32 #define SCLK_TSADC 72
24 #define SCLK_UART0 77 33 #define SCLK_UART0 77
25 #define SCLK_UART1 78 34 #define SCLK_UART1 78
26 #define SCLK_UART2 79 35 #define SCLK_UART2 79
27 #define SCLK_I2S0 80 36 #define SCLK_I2S0 80
28 #define SCLK_I2S1 81 37 #define SCLK_I2S1 81
29 #define SCLK_I2S2 82 38 #define SCLK_I2S2 82
30 #define SCLK_SPDIF 83 39 #define SCLK_SPDIF 83
31 #define SCLK_TIMER0 85 40 #define SCLK_TIMER0 85
32 #define SCLK_TIMER1 86 41 #define SCLK_TIMER1 86
33 #define SCLK_TIMER2 87 42 #define SCLK_TIMER2 87
34 #define SCLK_TIMER3 88 43 #define SCLK_TIMER3 88
35 #define SCLK_TIMER4 89 44 #define SCLK_TIMER4 89
36 #define SCLK_TIMER5 90 45 #define SCLK_TIMER5 90
37 #define SCLK_I2S_OUT 113 46 #define SCLK_I2S_OUT 113
38 #define SCLK_SDMMC_DRV 114 47 #define SCLK_SDMMC_DRV 114
39 #define SCLK_SDIO_DRV 115 48 #define SCLK_SDIO_DRV 115
40 #define SCLK_EMMC_DRV 117 49 #define SCLK_EMMC_DRV 117
41 #define SCLK_SDMMC_SAMPLE 118 50 #define SCLK_SDMMC_SAMPLE 118
42 #define SCLK_SDIO_SAMPLE 119 51 #define SCLK_SDIO_SAMPLE 119
43 #define SCLK_SDIO_SRC 120 52 #define SCLK_SDIO_SRC 120
44 #define SCLK_EMMC_SAMPLE 121 53 #define SCLK_EMMC_SAMPLE 121
45 #define SCLK_VOP 122 54 #define SCLK_VOP 122
46 #define SCLK_HDMI_HDCP 123 55 #define SCLK_HDMI_HDCP 123
47 #define SCLK_MAC_SRC 124 56 #define SCLK_MAC_SRC 124
48 #define SCLK_MAC_EXTCLK 125 57 #define SCLK_MAC_EXTCLK 125
49 #define SCLK_MAC 126 58 #define SCLK_MAC 126
50 #define SCLK_MAC_REFOUT 127 59 #define SCLK_MAC_REFOUT 127
51 #define SCLK_MAC_REF 128 60 #define SCLK_MAC_REF 128
52 #define SCLK_MAC_RX 129 61 #define SCLK_MAC_RX 129
53 #define SCLK_MAC_TX 130 62 #define SCLK_MAC_TX 130
54 #define SCLK_MAC_PHY 131 63 #define SCLK_MAC_PHY 131
55 #define SCLK_MAC_OUT 132 64 #define SCLK_MAC_OUT 132
56 #define SCLK_VDEC_CABAC 133 65 #define SCLK_VDEC_CABAC 133
57 #define SCLK_VDEC_CORE 134 66 #define SCLK_VDEC_CORE 134
58 #define SCLK_RGA 135 67 #define SCLK_RGA 135
59 #define SCLK_HDCP 136 68 #define SCLK_HDCP 136
60 #define SCLK_HDMI_CEC 137 69 #define SCLK_HDMI_CEC 137
61 #define SCLK_CRYPTO 138 70 #define SCLK_CRYPTO 138
62 #define SCLK_TSP 139 71 #define SCLK_TSP 139
63 #define SCLK_HSADC 140 72 #define SCLK_HSADC 140
64 #define SCLK_WIFI 141 73 #define SCLK_WIFI 141
65 #define SCLK_OTGPHY0 142 74 #define SCLK_OTGPHY0 142
66 #define SCLK_OTGPHY1 143 75 #define SCLK_OTGPHY1 143
67 #define SCLK_HDMI_PHY 144 <<
68 76
69 /* dclk gates */ 77 /* dclk gates */
70 #define DCLK_VOP 190 78 #define DCLK_VOP 190
71 #define DCLK_HDMI_PHY 191 79 #define DCLK_HDMI_PHY 191
72 80
73 /* aclk gates */ 81 /* aclk gates */
74 #define ACLK_DMAC 194 82 #define ACLK_DMAC 194
75 #define ACLK_CPU 195 83 #define ACLK_CPU 195
76 #define ACLK_VPU_PRE 196 84 #define ACLK_VPU_PRE 196
77 #define ACLK_RKVDEC_PRE 197 85 #define ACLK_RKVDEC_PRE 197
78 #define ACLK_RGA_PRE 198 86 #define ACLK_RGA_PRE 198
79 #define ACLK_IEP_PRE 199 87 #define ACLK_IEP_PRE 199
80 #define ACLK_HDCP_PRE 200 88 #define ACLK_HDCP_PRE 200
81 #define ACLK_VOP_PRE 201 89 #define ACLK_VOP_PRE 201
82 #define ACLK_VPU 202 90 #define ACLK_VPU 202
83 #define ACLK_RKVDEC 203 91 #define ACLK_RKVDEC 203
84 #define ACLK_IEP 204 92 #define ACLK_IEP 204
85 #define ACLK_RGA 205 93 #define ACLK_RGA 205
86 #define ACLK_HDCP 206 94 #define ACLK_HDCP 206
87 #define ACLK_PERI 210 95 #define ACLK_PERI 210
88 #define ACLK_VOP 211 96 #define ACLK_VOP 211
89 #define ACLK_GMAC 212 97 #define ACLK_GMAC 212
90 #define ACLK_GPU 213 98 #define ACLK_GPU 213
91 99
92 /* pclk gates */ 100 /* pclk gates */
93 #define PCLK_GPIO0 320 101 #define PCLK_GPIO0 320
94 #define PCLK_GPIO1 321 102 #define PCLK_GPIO1 321
95 #define PCLK_GPIO2 322 103 #define PCLK_GPIO2 322
96 #define PCLK_GPIO3 323 104 #define PCLK_GPIO3 323
97 #define PCLK_VIO_H2P 324 105 #define PCLK_VIO_H2P 324
98 #define PCLK_HDCP 325 106 #define PCLK_HDCP 325
99 #define PCLK_EFUSE_1024 326 107 #define PCLK_EFUSE_1024 326
100 #define PCLK_EFUSE_256 327 108 #define PCLK_EFUSE_256 327
101 #define PCLK_GRF 329 109 #define PCLK_GRF 329
102 #define PCLK_I2C0 332 110 #define PCLK_I2C0 332
103 #define PCLK_I2C1 333 111 #define PCLK_I2C1 333
104 #define PCLK_I2C2 334 112 #define PCLK_I2C2 334
105 #define PCLK_I2C3 335 113 #define PCLK_I2C3 335
106 #define PCLK_SPI0 338 114 #define PCLK_SPI0 338
107 #define PCLK_UART0 341 115 #define PCLK_UART0 341
108 #define PCLK_UART1 342 116 #define PCLK_UART1 342
109 #define PCLK_UART2 343 117 #define PCLK_UART2 343
110 #define PCLK_TSADC 344 118 #define PCLK_TSADC 344
111 #define PCLK_PWM 350 119 #define PCLK_PWM 350
112 #define PCLK_TIMER 353 120 #define PCLK_TIMER 353
113 #define PCLK_CPU 354 121 #define PCLK_CPU 354
114 #define PCLK_PERI 363 122 #define PCLK_PERI 363
115 #define PCLK_HDMI_CTRL 364 123 #define PCLK_HDMI_CTRL 364
116 #define PCLK_HDMI_PHY 365 124 #define PCLK_HDMI_PHY 365
117 #define PCLK_GMAC 367 125 #define PCLK_GMAC 367
118 126
119 /* hclk gates */ 127 /* hclk gates */
120 #define HCLK_I2S0_8CH 442 128 #define HCLK_I2S0_8CH 442
121 #define HCLK_I2S1_8CH 443 129 #define HCLK_I2S1_8CH 443
122 #define HCLK_I2S2_2CH 444 130 #define HCLK_I2S2_2CH 444
123 #define HCLK_SPDIF_8CH 445 131 #define HCLK_SPDIF_8CH 445
124 #define HCLK_VOP 452 132 #define HCLK_VOP 452
125 #define HCLK_NANDC 453 133 #define HCLK_NANDC 453
126 #define HCLK_SDMMC 456 134 #define HCLK_SDMMC 456
127 #define HCLK_SDIO 457 135 #define HCLK_SDIO 457
128 #define HCLK_EMMC 459 136 #define HCLK_EMMC 459
129 #define HCLK_CPU 460 137 #define HCLK_CPU 460
130 #define HCLK_VPU_PRE 461 138 #define HCLK_VPU_PRE 461
131 #define HCLK_RKVDEC_PRE 462 139 #define HCLK_RKVDEC_PRE 462
132 #define HCLK_VIO_PRE 463 140 #define HCLK_VIO_PRE 463
133 #define HCLK_VPU 464 141 #define HCLK_VPU 464
134 #define HCLK_RKVDEC 465 142 #define HCLK_RKVDEC 465
135 #define HCLK_VIO 466 143 #define HCLK_VIO 466
136 #define HCLK_RGA 467 144 #define HCLK_RGA 467
137 #define HCLK_IEP 468 145 #define HCLK_IEP 468
138 #define HCLK_VIO_H2P 469 146 #define HCLK_VIO_H2P 469
139 #define HCLK_HDCP_MMU 470 147 #define HCLK_HDCP_MMU 470
140 #define HCLK_HOST0 471 148 #define HCLK_HOST0 471
141 #define HCLK_HOST1 472 149 #define HCLK_HOST1 472
142 #define HCLK_HOST2 473 150 #define HCLK_HOST2 473
143 #define HCLK_OTG 474 151 #define HCLK_OTG 474
144 #define HCLK_TSP 475 152 #define HCLK_TSP 475
145 #define HCLK_M_CRYPTO 476 153 #define HCLK_M_CRYPTO 476
146 #define HCLK_S_CRYPTO 477 154 #define HCLK_S_CRYPTO 477
147 #define HCLK_PERI 478 155 #define HCLK_PERI 478
>> 156
>> 157 #define CLK_NR_CLKS (HCLK_PERI + 1)
148 158
149 /* soft-reset indices */ 159 /* soft-reset indices */
150 #define SRST_CORE0_PO 0 160 #define SRST_CORE0_PO 0
151 #define SRST_CORE1_PO 1 161 #define SRST_CORE1_PO 1
152 #define SRST_CORE2_PO 2 162 #define SRST_CORE2_PO 2
153 #define SRST_CORE3_PO 3 163 #define SRST_CORE3_PO 3
154 #define SRST_CORE0 4 164 #define SRST_CORE0 4
155 #define SRST_CORE1 5 165 #define SRST_CORE1 5
156 #define SRST_CORE2 6 166 #define SRST_CORE2 6
157 #define SRST_CORE3 7 167 #define SRST_CORE3 7
158 #define SRST_CORE0_DBG 8 168 #define SRST_CORE0_DBG 8
159 #define SRST_CORE1_DBG 9 169 #define SRST_CORE1_DBG 9
160 #define SRST_CORE2_DBG 10 170 #define SRST_CORE2_DBG 10
161 #define SRST_CORE3_DBG 11 171 #define SRST_CORE3_DBG 11
162 #define SRST_TOPDBG 12 172 #define SRST_TOPDBG 12
163 #define SRST_ACLK_CORE 13 173 #define SRST_ACLK_CORE 13
164 #define SRST_NOC 14 174 #define SRST_NOC 14
165 #define SRST_L2C 15 175 #define SRST_L2C 15
166 176
167 #define SRST_CPUSYS_H 18 177 #define SRST_CPUSYS_H 18
168 #define SRST_BUSSYS_H 19 178 #define SRST_BUSSYS_H 19
169 #define SRST_SPDIF 20 179 #define SRST_SPDIF 20
170 #define SRST_INTMEM 21 180 #define SRST_INTMEM 21
171 #define SRST_ROM 22 181 #define SRST_ROM 22
172 #define SRST_OTG_ADP 23 182 #define SRST_OTG_ADP 23
173 #define SRST_I2S0 24 183 #define SRST_I2S0 24
174 #define SRST_I2S1 25 184 #define SRST_I2S1 25
175 #define SRST_I2S2 26 185 #define SRST_I2S2 26
176 #define SRST_ACODEC_P 27 186 #define SRST_ACODEC_P 27
177 #define SRST_DFIMON 28 187 #define SRST_DFIMON 28
178 #define SRST_MSCH 29 188 #define SRST_MSCH 29
179 #define SRST_EFUSE1024 30 189 #define SRST_EFUSE1024 30
180 #define SRST_EFUSE256 31 190 #define SRST_EFUSE256 31
181 191
182 #define SRST_GPIO0 32 192 #define SRST_GPIO0 32
183 #define SRST_GPIO1 33 193 #define SRST_GPIO1 33
184 #define SRST_GPIO2 34 194 #define SRST_GPIO2 34
185 #define SRST_GPIO3 35 195 #define SRST_GPIO3 35
186 #define SRST_PERIPH_NOC_A 36 196 #define SRST_PERIPH_NOC_A 36
187 #define SRST_PERIPH_NOC_BUS_H 37 197 #define SRST_PERIPH_NOC_BUS_H 37
188 #define SRST_PERIPH_NOC_P 38 198 #define SRST_PERIPH_NOC_P 38
189 #define SRST_UART0 39 199 #define SRST_UART0 39
190 #define SRST_UART1 40 200 #define SRST_UART1 40
191 #define SRST_UART2 41 201 #define SRST_UART2 41
192 #define SRST_PHYNOC 42 202 #define SRST_PHYNOC 42
193 #define SRST_I2C0 43 203 #define SRST_I2C0 43
194 #define SRST_I2C1 44 204 #define SRST_I2C1 44
195 #define SRST_I2C2 45 205 #define SRST_I2C2 45
196 #define SRST_I2C3 46 206 #define SRST_I2C3 46
197 207
198 #define SRST_PWM 48 208 #define SRST_PWM 48
199 #define SRST_A53_GIC 49 209 #define SRST_A53_GIC 49
200 #define SRST_DAP 51 210 #define SRST_DAP 51
201 #define SRST_DAP_NOC 52 211 #define SRST_DAP_NOC 52
202 #define SRST_CRYPTO 53 212 #define SRST_CRYPTO 53
203 #define SRST_SGRF 54 213 #define SRST_SGRF 54
204 #define SRST_GRF 55 214 #define SRST_GRF 55
205 #define SRST_GMAC 56 215 #define SRST_GMAC 56
206 #define SRST_PERIPH_NOC_H 58 216 #define SRST_PERIPH_NOC_H 58
207 #define SRST_MACPHY 63 217 #define SRST_MACPHY 63
208 218
209 #define SRST_DMA 64 219 #define SRST_DMA 64
210 #define SRST_NANDC 68 220 #define SRST_NANDC 68
211 #define SRST_USBOTG 69 221 #define SRST_USBOTG 69
212 #define SRST_OTGC 70 222 #define SRST_OTGC 70
213 #define SRST_USBHOST0 71 223 #define SRST_USBHOST0 71
214 #define SRST_HOST_CTRL0 72 224 #define SRST_HOST_CTRL0 72
215 #define SRST_USBHOST1 73 225 #define SRST_USBHOST1 73
216 #define SRST_HOST_CTRL1 74 226 #define SRST_HOST_CTRL1 74
217 #define SRST_USBHOST2 75 227 #define SRST_USBHOST2 75
218 #define SRST_HOST_CTRL2 76 228 #define SRST_HOST_CTRL2 76
219 #define SRST_USBPOR0 77 229 #define SRST_USBPOR0 77
220 #define SRST_USBPOR1 78 230 #define SRST_USBPOR1 78
221 #define SRST_DDRMSCH 79 231 #define SRST_DDRMSCH 79
222 232
223 #define SRST_SMART_CARD 80 233 #define SRST_SMART_CARD 80
224 #define SRST_SDMMC 81 234 #define SRST_SDMMC 81
225 #define SRST_SDIO 82 235 #define SRST_SDIO 82
226 #define SRST_EMMC 83 236 #define SRST_EMMC 83
227 #define SRST_SPI 84 237 #define SRST_SPI 84
228 #define SRST_TSP_H 85 238 #define SRST_TSP_H 85
229 #define SRST_TSP 86 239 #define SRST_TSP 86
230 #define SRST_TSADC 87 240 #define SRST_TSADC 87
231 #define SRST_DDRPHY 88 241 #define SRST_DDRPHY 88
232 #define SRST_DDRPHY_P 89 242 #define SRST_DDRPHY_P 89
233 #define SRST_DDRCTRL 90 243 #define SRST_DDRCTRL 90
234 #define SRST_DDRCTRL_P 91 244 #define SRST_DDRCTRL_P 91
235 #define SRST_HOST0_ECHI 92 245 #define SRST_HOST0_ECHI 92
236 #define SRST_HOST1_ECHI 93 246 #define SRST_HOST1_ECHI 93
237 #define SRST_HOST2_ECHI 94 247 #define SRST_HOST2_ECHI 94
238 #define SRST_VOP_NOC_A 95 248 #define SRST_VOP_NOC_A 95
239 249
240 #define SRST_HDMI_P 96 250 #define SRST_HDMI_P 96
241 #define SRST_VIO_ARBI_H 97 251 #define SRST_VIO_ARBI_H 97
242 #define SRST_IEP_NOC_A 98 252 #define SRST_IEP_NOC_A 98
243 #define SRST_VIO_NOC_H 99 253 #define SRST_VIO_NOC_H 99
244 #define SRST_VOP_A 100 254 #define SRST_VOP_A 100
245 #define SRST_VOP_H 101 255 #define SRST_VOP_H 101
246 #define SRST_VOP_D 102 256 #define SRST_VOP_D 102
247 #define SRST_UTMI0 103 257 #define SRST_UTMI0 103
248 #define SRST_UTMI1 104 258 #define SRST_UTMI1 104
249 #define SRST_UTMI2 105 259 #define SRST_UTMI2 105
250 #define SRST_UTMI3 106 260 #define SRST_UTMI3 106
251 #define SRST_RGA 107 261 #define SRST_RGA 107
252 #define SRST_RGA_NOC_A 108 262 #define SRST_RGA_NOC_A 108
253 #define SRST_RGA_A 109 263 #define SRST_RGA_A 109
254 #define SRST_RGA_H 110 264 #define SRST_RGA_H 110
255 #define SRST_HDCP_A 111 265 #define SRST_HDCP_A 111
256 266
257 #define SRST_VPU_A 112 267 #define SRST_VPU_A 112
258 #define SRST_VPU_H 113 268 #define SRST_VPU_H 113
259 #define SRST_VPU_NOC_A 116 269 #define SRST_VPU_NOC_A 116
260 #define SRST_VPU_NOC_H 117 270 #define SRST_VPU_NOC_H 117
261 #define SRST_RKVDEC_A 118 271 #define SRST_RKVDEC_A 118
262 #define SRST_RKVDEC_NOC_A 119 272 #define SRST_RKVDEC_NOC_A 119
263 #define SRST_RKVDEC_H 120 273 #define SRST_RKVDEC_H 120
264 #define SRST_RKVDEC_NOC_H 121 274 #define SRST_RKVDEC_NOC_H 121
265 #define SRST_RKVDEC_CORE 122 275 #define SRST_RKVDEC_CORE 122
266 #define SRST_RKVDEC_CABAC 123 276 #define SRST_RKVDEC_CABAC 123
267 #define SRST_IEP_A 124 277 #define SRST_IEP_A 124
268 #define SRST_IEP_H 125 278 #define SRST_IEP_H 125
269 #define SRST_GPU_A 126 279 #define SRST_GPU_A 126
270 #define SRST_GPU_NOC_A 127 280 #define SRST_GPU_NOC_A 127
271 281
272 #define SRST_CORE_DBG 128 282 #define SRST_CORE_DBG 128
273 #define SRST_DBG_P 129 283 #define SRST_DBG_P 129
274 #define SRST_TIMER0 130 284 #define SRST_TIMER0 130
275 #define SRST_TIMER1 131 285 #define SRST_TIMER1 131
276 #define SRST_TIMER2 132 286 #define SRST_TIMER2 132
277 #define SRST_TIMER3 133 287 #define SRST_TIMER3 133
278 #define SRST_TIMER4 134 288 #define SRST_TIMER4 134
279 #define SRST_TIMER5 135 289 #define SRST_TIMER5 135
280 #define SRST_VIO_H2P 136 290 #define SRST_VIO_H2P 136
281 #define SRST_HDMIPHY 139 291 #define SRST_HDMIPHY 139
282 #define SRST_VDAC 140 292 #define SRST_VDAC 140
283 #define SRST_TIMER_6CH_P 141 293 #define SRST_TIMER_6CH_P 141
284 294
285 #endif 295 #endif
286 296
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