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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/dt-bindings/clock/rk3308-cru.h

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

Diff markup

Differences between /scripts/dtc/include-prefixes/dt-bindings/clock/rk3308-cru.h (Architecture i386) and /scripts/dtc/include-prefixes/dt-bindings/clock/rk3308-cru.h (Architecture alpha)


  1 /* SPDX-License-Identifier: GPL-2.0 */              1 /* SPDX-License-Identifier: GPL-2.0 */
  2 /*                                                  2 /*
  3  * Copyright (c) 2019 Rockchip Electronics Co.      3  * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
  4  * Author: Finley Xiao <finley.xiao@rock-chips      4  * Author: Finley Xiao <finley.xiao@rock-chips.com>
  5  */                                                 5  */
  6                                                     6 
  7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H          7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
  8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H          8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
  9                                                     9 
 10 /* core clocks */                                  10 /* core clocks */
 11 #define PLL_APLL                1                  11 #define PLL_APLL                1
 12 #define PLL_DPLL                2                  12 #define PLL_DPLL                2
 13 #define PLL_VPLL0               3                  13 #define PLL_VPLL0               3
 14 #define PLL_VPLL1               4                  14 #define PLL_VPLL1               4
 15 #define ARMCLK                  5                  15 #define ARMCLK                  5
 16                                                    16 
 17 /* sclk (special clocks) */                        17 /* sclk (special clocks) */
 18 #define USB480M                 14                 18 #define USB480M                 14
 19 #define SCLK_RTC32K             15                 19 #define SCLK_RTC32K             15
 20 #define SCLK_PVTM_CORE          16                 20 #define SCLK_PVTM_CORE          16
 21 #define SCLK_UART0              17                 21 #define SCLK_UART0              17
 22 #define SCLK_UART1              18                 22 #define SCLK_UART1              18
 23 #define SCLK_UART2              19                 23 #define SCLK_UART2              19
 24 #define SCLK_UART3              20                 24 #define SCLK_UART3              20
 25 #define SCLK_UART4              21                 25 #define SCLK_UART4              21
 26 #define SCLK_I2C0               22                 26 #define SCLK_I2C0               22
 27 #define SCLK_I2C1               23                 27 #define SCLK_I2C1               23
 28 #define SCLK_I2C2               24                 28 #define SCLK_I2C2               24
 29 #define SCLK_I2C3               25                 29 #define SCLK_I2C3               25
 30 #define SCLK_PWM0               26                 30 #define SCLK_PWM0               26
 31 #define SCLK_SPI0               27                 31 #define SCLK_SPI0               27
 32 #define SCLK_SPI1               28                 32 #define SCLK_SPI1               28
 33 #define SCLK_SPI2               29                 33 #define SCLK_SPI2               29
 34 #define SCLK_TIMER0             30                 34 #define SCLK_TIMER0             30
 35 #define SCLK_TIMER1             31                 35 #define SCLK_TIMER1             31
 36 #define SCLK_TIMER2             32                 36 #define SCLK_TIMER2             32
 37 #define SCLK_TIMER3             33                 37 #define SCLK_TIMER3             33
 38 #define SCLK_TIMER4             34                 38 #define SCLK_TIMER4             34
 39 #define SCLK_TIMER5             35                 39 #define SCLK_TIMER5             35
 40 #define SCLK_TSADC              36                 40 #define SCLK_TSADC              36
 41 #define SCLK_SARADC             37                 41 #define SCLK_SARADC             37
 42 #define SCLK_OTP                38                 42 #define SCLK_OTP                38
 43 #define SCLK_OTP_USR            39                 43 #define SCLK_OTP_USR            39
 44 #define SCLK_CPU_BOOST          40                 44 #define SCLK_CPU_BOOST          40
 45 #define SCLK_CRYPTO             41                 45 #define SCLK_CRYPTO             41
 46 #define SCLK_CRYPTO_APK         42                 46 #define SCLK_CRYPTO_APK         42
 47 #define SCLK_NANDC_DIV          43                 47 #define SCLK_NANDC_DIV          43
 48 #define SCLK_NANDC_DIV50        44                 48 #define SCLK_NANDC_DIV50        44
 49 #define SCLK_NANDC              45                 49 #define SCLK_NANDC              45
 50 #define SCLK_SDMMC_DIV          46                 50 #define SCLK_SDMMC_DIV          46
 51 #define SCLK_SDMMC_DIV50        47                 51 #define SCLK_SDMMC_DIV50        47
 52 #define SCLK_SDMMC              48                 52 #define SCLK_SDMMC              48
 53 #define SCLK_SDMMC_DRV          49                 53 #define SCLK_SDMMC_DRV          49
 54 #define SCLK_SDMMC_SAMPLE       50                 54 #define SCLK_SDMMC_SAMPLE       50
 55 #define SCLK_SDIO_DIV           51                 55 #define SCLK_SDIO_DIV           51
 56 #define SCLK_SDIO_DIV50         52                 56 #define SCLK_SDIO_DIV50         52
 57 #define SCLK_SDIO               53                 57 #define SCLK_SDIO               53
 58 #define SCLK_SDIO_DRV           54                 58 #define SCLK_SDIO_DRV           54
 59 #define SCLK_SDIO_SAMPLE        55                 59 #define SCLK_SDIO_SAMPLE        55
 60 #define SCLK_EMMC_DIV           56                 60 #define SCLK_EMMC_DIV           56
 61 #define SCLK_EMMC_DIV50         57                 61 #define SCLK_EMMC_DIV50         57
 62 #define SCLK_EMMC               58                 62 #define SCLK_EMMC               58
 63 #define SCLK_EMMC_DRV           59                 63 #define SCLK_EMMC_DRV           59
 64 #define SCLK_EMMC_SAMPLE        60                 64 #define SCLK_EMMC_SAMPLE        60
 65 #define SCLK_SFC                61                 65 #define SCLK_SFC                61
 66 #define SCLK_OTG_ADP            62                 66 #define SCLK_OTG_ADP            62
 67 #define SCLK_MAC_SRC            63                 67 #define SCLK_MAC_SRC            63
 68 #define SCLK_MAC                64                 68 #define SCLK_MAC                64
 69 #define SCLK_MAC_REF            65                 69 #define SCLK_MAC_REF            65
 70 #define SCLK_MAC_RX_TX          66                 70 #define SCLK_MAC_RX_TX          66
 71 #define SCLK_MAC_RMII           67                 71 #define SCLK_MAC_RMII           67
 72 #define SCLK_DDR_MON_TIMER      68                 72 #define SCLK_DDR_MON_TIMER      68
 73 #define SCLK_DDR_MON            69                 73 #define SCLK_DDR_MON            69
 74 #define SCLK_DDRCLK             70                 74 #define SCLK_DDRCLK             70
 75 #define SCLK_PMU                71                 75 #define SCLK_PMU                71
 76 #define SCLK_USBPHY_REF         72                 76 #define SCLK_USBPHY_REF         72
 77 #define SCLK_WIFI               73                 77 #define SCLK_WIFI               73
 78 #define SCLK_PVTM_PMU           74                 78 #define SCLK_PVTM_PMU           74
 79 #define SCLK_PDM                75                 79 #define SCLK_PDM                75
 80 #define SCLK_I2S0_8CH_TX        76                 80 #define SCLK_I2S0_8CH_TX        76
 81 #define SCLK_I2S0_8CH_TX_OUT    77                 81 #define SCLK_I2S0_8CH_TX_OUT    77
 82 #define SCLK_I2S0_8CH_RX        78                 82 #define SCLK_I2S0_8CH_RX        78
 83 #define SCLK_I2S0_8CH_RX_OUT    79                 83 #define SCLK_I2S0_8CH_RX_OUT    79
 84 #define SCLK_I2S1_8CH_TX        80                 84 #define SCLK_I2S1_8CH_TX        80
 85 #define SCLK_I2S1_8CH_TX_OUT    81                 85 #define SCLK_I2S1_8CH_TX_OUT    81
 86 #define SCLK_I2S1_8CH_RX        82                 86 #define SCLK_I2S1_8CH_RX        82
 87 #define SCLK_I2S1_8CH_RX_OUT    83                 87 #define SCLK_I2S1_8CH_RX_OUT    83
 88 #define SCLK_I2S2_8CH_TX        84                 88 #define SCLK_I2S2_8CH_TX        84
 89 #define SCLK_I2S2_8CH_TX_OUT    85                 89 #define SCLK_I2S2_8CH_TX_OUT    85
 90 #define SCLK_I2S2_8CH_RX        86                 90 #define SCLK_I2S2_8CH_RX        86
 91 #define SCLK_I2S2_8CH_RX_OUT    87                 91 #define SCLK_I2S2_8CH_RX_OUT    87
 92 #define SCLK_I2S3_8CH_TX        88                 92 #define SCLK_I2S3_8CH_TX        88
 93 #define SCLK_I2S3_8CH_TX_OUT    89                 93 #define SCLK_I2S3_8CH_TX_OUT    89
 94 #define SCLK_I2S3_8CH_RX        90                 94 #define SCLK_I2S3_8CH_RX        90
 95 #define SCLK_I2S3_8CH_RX_OUT    91                 95 #define SCLK_I2S3_8CH_RX_OUT    91
 96 #define SCLK_I2S0_2CH           92                 96 #define SCLK_I2S0_2CH           92
 97 #define SCLK_I2S0_2CH_OUT       93                 97 #define SCLK_I2S0_2CH_OUT       93
 98 #define SCLK_I2S1_2CH           94                 98 #define SCLK_I2S1_2CH           94
 99 #define SCLK_I2S1_2CH_OUT       95                 99 #define SCLK_I2S1_2CH_OUT       95
100 #define SCLK_SPDIF_TX_DIV       96                100 #define SCLK_SPDIF_TX_DIV       96
101 #define SCLK_SPDIF_TX_DIV50     97                101 #define SCLK_SPDIF_TX_DIV50     97
102 #define SCLK_SPDIF_TX           98                102 #define SCLK_SPDIF_TX           98
103 #define SCLK_SPDIF_RX_DIV       99                103 #define SCLK_SPDIF_RX_DIV       99
104 #define SCLK_SPDIF_RX_DIV50     100               104 #define SCLK_SPDIF_RX_DIV50     100
105 #define SCLK_SPDIF_RX           101               105 #define SCLK_SPDIF_RX           101
106 #define SCLK_I2S0_8CH_TX_MUX    102               106 #define SCLK_I2S0_8CH_TX_MUX    102
107 #define SCLK_I2S0_8CH_RX_MUX    103               107 #define SCLK_I2S0_8CH_RX_MUX    103
108 #define SCLK_I2S1_8CH_TX_MUX    104               108 #define SCLK_I2S1_8CH_TX_MUX    104
109 #define SCLK_I2S1_8CH_RX_MUX    105               109 #define SCLK_I2S1_8CH_RX_MUX    105
110 #define SCLK_I2S2_8CH_TX_MUX    106               110 #define SCLK_I2S2_8CH_TX_MUX    106
111 #define SCLK_I2S2_8CH_RX_MUX    107               111 #define SCLK_I2S2_8CH_RX_MUX    107
112 #define SCLK_I2S3_8CH_TX_MUX    108               112 #define SCLK_I2S3_8CH_TX_MUX    108
113 #define SCLK_I2S3_8CH_RX_MUX    109               113 #define SCLK_I2S3_8CH_RX_MUX    109
114 #define SCLK_I2S0_8CH_TX_SRC    110               114 #define SCLK_I2S0_8CH_TX_SRC    110
115 #define SCLK_I2S0_8CH_RX_SRC    111               115 #define SCLK_I2S0_8CH_RX_SRC    111
116 #define SCLK_I2S1_8CH_TX_SRC    112               116 #define SCLK_I2S1_8CH_TX_SRC    112
117 #define SCLK_I2S1_8CH_RX_SRC    113               117 #define SCLK_I2S1_8CH_RX_SRC    113
118 #define SCLK_I2S2_8CH_TX_SRC    114               118 #define SCLK_I2S2_8CH_TX_SRC    114
119 #define SCLK_I2S2_8CH_RX_SRC    115               119 #define SCLK_I2S2_8CH_RX_SRC    115
120 #define SCLK_I2S3_8CH_TX_SRC    116               120 #define SCLK_I2S3_8CH_TX_SRC    116
121 #define SCLK_I2S3_8CH_RX_SRC    117               121 #define SCLK_I2S3_8CH_RX_SRC    117
122 #define SCLK_I2S0_2CH_SRC       118               122 #define SCLK_I2S0_2CH_SRC       118
123 #define SCLK_I2S1_2CH_SRC       119               123 #define SCLK_I2S1_2CH_SRC       119
124 #define SCLK_PWM1               120               124 #define SCLK_PWM1               120
125 #define SCLK_PWM2               121               125 #define SCLK_PWM2               121
126 #define SCLK_OWIRE              122               126 #define SCLK_OWIRE              122
127                                                   127 
128 /* dclk */                                        128 /* dclk */
129 #define DCLK_VOP                125               129 #define DCLK_VOP                125
130                                                   130 
131 /* aclk */                                        131 /* aclk */
132 #define ACLK_BUS_SRC            130               132 #define ACLK_BUS_SRC            130
133 #define ACLK_BUS                131               133 #define ACLK_BUS                131
134 #define ACLK_PERI_SRC           132               134 #define ACLK_PERI_SRC           132
135 #define ACLK_PERI               133               135 #define ACLK_PERI               133
136 #define ACLK_MAC                134               136 #define ACLK_MAC                134
137 #define ACLK_CRYPTO             135               137 #define ACLK_CRYPTO             135
138 #define ACLK_VOP                136               138 #define ACLK_VOP                136
139 #define ACLK_GIC                137               139 #define ACLK_GIC                137
140 #define ACLK_DMAC0              138               140 #define ACLK_DMAC0              138
141 #define ACLK_DMAC1              139               141 #define ACLK_DMAC1              139
142                                                   142 
143 /* hclk */                                        143 /* hclk */
144 #define HCLK_BUS                150               144 #define HCLK_BUS                150
145 #define HCLK_PERI               151               145 #define HCLK_PERI               151
146 #define HCLK_AUDIO              152               146 #define HCLK_AUDIO              152
147 #define HCLK_NANDC              153               147 #define HCLK_NANDC              153
148 #define HCLK_SDMMC              154               148 #define HCLK_SDMMC              154
149 #define HCLK_SDIO               155               149 #define HCLK_SDIO               155
150 #define HCLK_EMMC               156               150 #define HCLK_EMMC               156
151 #define HCLK_SFC                157               151 #define HCLK_SFC                157
152 #define HCLK_OTG                158               152 #define HCLK_OTG                158
153 #define HCLK_HOST               159               153 #define HCLK_HOST               159
154 #define HCLK_HOST_ARB           160               154 #define HCLK_HOST_ARB           160
155 #define HCLK_PDM                161               155 #define HCLK_PDM                161
156 #define HCLK_SPDIFTX            162               156 #define HCLK_SPDIFTX            162
157 #define HCLK_SPDIFRX            163               157 #define HCLK_SPDIFRX            163
158 #define HCLK_I2S0_8CH           164               158 #define HCLK_I2S0_8CH           164
159 #define HCLK_I2S1_8CH           165               159 #define HCLK_I2S1_8CH           165
160 #define HCLK_I2S2_8CH           166               160 #define HCLK_I2S2_8CH           166
161 #define HCLK_I2S3_8CH           167               161 #define HCLK_I2S3_8CH           167
162 #define HCLK_I2S0_2CH           168               162 #define HCLK_I2S0_2CH           168
163 #define HCLK_I2S1_2CH           169               163 #define HCLK_I2S1_2CH           169
164 #define HCLK_VAD                170               164 #define HCLK_VAD                170
165 #define HCLK_CRYPTO             171               165 #define HCLK_CRYPTO             171
166 #define HCLK_VOP                172               166 #define HCLK_VOP                172
167                                                   167 
168 /* pclk */                                        168 /* pclk */
169 #define PCLK_BUS                190               169 #define PCLK_BUS                190
170 #define PCLK_DDR                191               170 #define PCLK_DDR                191
171 #define PCLK_PERI               192               171 #define PCLK_PERI               192
172 #define PCLK_PMU                193               172 #define PCLK_PMU                193
173 #define PCLK_AUDIO              194               173 #define PCLK_AUDIO              194
174 #define PCLK_MAC                195               174 #define PCLK_MAC                195
175 #define PCLK_ACODEC             196               175 #define PCLK_ACODEC             196
176 #define PCLK_UART0              197               176 #define PCLK_UART0              197
177 #define PCLK_UART1              198               177 #define PCLK_UART1              198
178 #define PCLK_UART2              199               178 #define PCLK_UART2              199
179 #define PCLK_UART3              200               179 #define PCLK_UART3              200
180 #define PCLK_UART4              201               180 #define PCLK_UART4              201
181 #define PCLK_I2C0               202               181 #define PCLK_I2C0               202
182 #define PCLK_I2C1               203               182 #define PCLK_I2C1               203
183 #define PCLK_I2C2               204               183 #define PCLK_I2C2               204
184 #define PCLK_I2C3               205               184 #define PCLK_I2C3               205
185 #define PCLK_PWM0               206               185 #define PCLK_PWM0               206
186 #define PCLK_SPI0               207               186 #define PCLK_SPI0               207
187 #define PCLK_SPI1               208               187 #define PCLK_SPI1               208
188 #define PCLK_SPI2               209               188 #define PCLK_SPI2               209
189 #define PCLK_SARADC             210               189 #define PCLK_SARADC             210
190 #define PCLK_TSADC              211               190 #define PCLK_TSADC              211
191 #define PCLK_TIMER              212               191 #define PCLK_TIMER              212
192 #define PCLK_OTP_NS             213               192 #define PCLK_OTP_NS             213
193 #define PCLK_WDT                214               193 #define PCLK_WDT                214
194 #define PCLK_GPIO0              215               194 #define PCLK_GPIO0              215
195 #define PCLK_GPIO1              216               195 #define PCLK_GPIO1              216
196 #define PCLK_GPIO2              217               196 #define PCLK_GPIO2              217
197 #define PCLK_GPIO3              218               197 #define PCLK_GPIO3              218
198 #define PCLK_GPIO4              219               198 #define PCLK_GPIO4              219
199 #define PCLK_SGRF               220               199 #define PCLK_SGRF               220
200 #define PCLK_GRF                221               200 #define PCLK_GRF                221
201 #define PCLK_USBSD_DET          222               201 #define PCLK_USBSD_DET          222
202 #define PCLK_DDR_UPCTL          223               202 #define PCLK_DDR_UPCTL          223
203 #define PCLK_DDR_MON            224               203 #define PCLK_DDR_MON            224
204 #define PCLK_DDRPHY             225               204 #define PCLK_DDRPHY             225
205 #define PCLK_DDR_STDBY          226               205 #define PCLK_DDR_STDBY          226
206 #define PCLK_USB_GRF            227               206 #define PCLK_USB_GRF            227
207 #define PCLK_CRU                228               207 #define PCLK_CRU                228
208 #define PCLK_OTP_PHY            229               208 #define PCLK_OTP_PHY            229
209 #define PCLK_CPU_BOOST          230               209 #define PCLK_CPU_BOOST          230
210 #define PCLK_PWM1               231               210 #define PCLK_PWM1               231
211 #define PCLK_PWM2               232               211 #define PCLK_PWM2               232
212 #define PCLK_CAN                233               212 #define PCLK_CAN                233
213 #define PCLK_OWIRE              234               213 #define PCLK_OWIRE              234
214                                                   214 
215 /* soft-reset indices */                          215 /* soft-reset indices */
216                                                   216 
217 /* cru_softrst_con0 */                            217 /* cru_softrst_con0 */
218 #define SRST_CORE0_PO           0                 218 #define SRST_CORE0_PO           0
219 #define SRST_CORE1_PO           1                 219 #define SRST_CORE1_PO           1
220 #define SRST_CORE2_PO           2                 220 #define SRST_CORE2_PO           2
221 #define SRST_CORE3_PO           3                 221 #define SRST_CORE3_PO           3
222 #define SRST_CORE0              4                 222 #define SRST_CORE0              4
223 #define SRST_CORE1              5                 223 #define SRST_CORE1              5
224 #define SRST_CORE2              6                 224 #define SRST_CORE2              6
225 #define SRST_CORE3              7                 225 #define SRST_CORE3              7
226 #define SRST_CORE0_DBG          8                 226 #define SRST_CORE0_DBG          8
227 #define SRST_CORE1_DBG          9                 227 #define SRST_CORE1_DBG          9
228 #define SRST_CORE2_DBG          10                228 #define SRST_CORE2_DBG          10
229 #define SRST_CORE3_DBG          11                229 #define SRST_CORE3_DBG          11
230 #define SRST_TOPDBG             12                230 #define SRST_TOPDBG             12
231 #define SRST_CORE_NOC           13                231 #define SRST_CORE_NOC           13
232 #define SRST_STRC_A             14                232 #define SRST_STRC_A             14
233 #define SRST_L2C                15                233 #define SRST_L2C                15
234                                                   234 
235 /* cru_softrst_con1 */                            235 /* cru_softrst_con1 */
236 #define SRST_DAP                16                236 #define SRST_DAP                16
237 #define SRST_CORE_PVTM          17                237 #define SRST_CORE_PVTM          17
238 #define SRST_CORE_PRF           18                238 #define SRST_CORE_PRF           18
239 #define SRST_CORE_GRF           19                239 #define SRST_CORE_GRF           19
240 #define SRST_DDRUPCTL           20                240 #define SRST_DDRUPCTL           20
241 #define SRST_DDRUPCTL_P         22                241 #define SRST_DDRUPCTL_P         22
242 #define SRST_MSCH               23                242 #define SRST_MSCH               23
243 #define SRST_DDRMON_P           25                243 #define SRST_DDRMON_P           25
244 #define SRST_DDRSTDBY_P         26                244 #define SRST_DDRSTDBY_P         26
245 #define SRST_DDRSTDBY           27                245 #define SRST_DDRSTDBY           27
246 #define SRST_DDRPHY             28                246 #define SRST_DDRPHY             28
247 #define SRST_DDRPHY_DIV         29                247 #define SRST_DDRPHY_DIV         29
248 #define SRST_DDRPHY_P           30                248 #define SRST_DDRPHY_P           30
249                                                   249 
250 /* cru_softrst_con2 */                            250 /* cru_softrst_con2 */
251 #define SRST_BUS_NIU_H          32                251 #define SRST_BUS_NIU_H          32
252 #define SRST_USB_NIU_P          33                252 #define SRST_USB_NIU_P          33
253 #define SRST_CRYPTO_A           34                253 #define SRST_CRYPTO_A           34
254 #define SRST_CRYPTO_H           35                254 #define SRST_CRYPTO_H           35
255 #define SRST_CRYPTO             36                255 #define SRST_CRYPTO             36
256 #define SRST_CRYPTO_APK         37                256 #define SRST_CRYPTO_APK         37
257 #define SRST_VOP_A              38                257 #define SRST_VOP_A              38
258 #define SRST_VOP_H              39                258 #define SRST_VOP_H              39
259 #define SRST_VOP_D              40                259 #define SRST_VOP_D              40
260 #define SRST_INTMEM_A           41                260 #define SRST_INTMEM_A           41
261 #define SRST_ROM_H              42                261 #define SRST_ROM_H              42
262 #define SRST_GIC_A              43                262 #define SRST_GIC_A              43
263 #define SRST_UART0_P            44                263 #define SRST_UART0_P            44
264 #define SRST_UART0              45                264 #define SRST_UART0              45
265 #define SRST_UART1_P            46                265 #define SRST_UART1_P            46
266 #define SRST_UART1              47                266 #define SRST_UART1              47
267                                                   267 
268 /* cru_softrst_con3 */                            268 /* cru_softrst_con3 */
269 #define SRST_UART2_P            48                269 #define SRST_UART2_P            48
270 #define SRST_UART2              49                270 #define SRST_UART2              49
271 #define SRST_UART3_P            50                271 #define SRST_UART3_P            50
272 #define SRST_UART3              51                272 #define SRST_UART3              51
273 #define SRST_UART4_P            52                273 #define SRST_UART4_P            52
274 #define SRST_UART4              53                274 #define SRST_UART4              53
275 #define SRST_I2C0_P             54                275 #define SRST_I2C0_P             54
276 #define SRST_I2C0               55                276 #define SRST_I2C0               55
277 #define SRST_I2C1_P             56                277 #define SRST_I2C1_P             56
278 #define SRST_I2C1               57                278 #define SRST_I2C1               57
279 #define SRST_I2C2_P             58                279 #define SRST_I2C2_P             58
280 #define SRST_I2C2               59                280 #define SRST_I2C2               59
281 #define SRST_I2C3_P             60                281 #define SRST_I2C3_P             60
282 #define SRST_I2C3               61                282 #define SRST_I2C3               61
283 #define SRST_PWM0_P             62                283 #define SRST_PWM0_P             62
284 #define SRST_PWM0               63                284 #define SRST_PWM0               63
285                                                   285 
286 /* cru_softrst_con4 */                            286 /* cru_softrst_con4 */
287 #define SRST_SPI0_P             64                287 #define SRST_SPI0_P             64
288 #define SRST_SPI0               65                288 #define SRST_SPI0               65
289 #define SRST_SPI1_P             66                289 #define SRST_SPI1_P             66
290 #define SRST_SPI1               67                290 #define SRST_SPI1               67
291 #define SRST_SPI2_P             68                291 #define SRST_SPI2_P             68
292 #define SRST_SPI2               69                292 #define SRST_SPI2               69
293 #define SRST_SARADC_P           70                293 #define SRST_SARADC_P           70
294 #define SRST_TSADC_P            71                294 #define SRST_TSADC_P            71
295 #define SRST_TSADC              72                295 #define SRST_TSADC              72
296 #define SRST_TIMER0_P           73                296 #define SRST_TIMER0_P           73
297 #define SRST_TIMER0             74                297 #define SRST_TIMER0             74
298 #define SRST_TIMER1             75                298 #define SRST_TIMER1             75
299 #define SRST_TIMER2             76                299 #define SRST_TIMER2             76
300 #define SRST_TIMER3             77                300 #define SRST_TIMER3             77
301 #define SRST_TIMER4             78                301 #define SRST_TIMER4             78
302 #define SRST_TIMER5             79                302 #define SRST_TIMER5             79
303                                                   303 
304 /* cru_softrst_con5 */                            304 /* cru_softrst_con5 */
305 #define SRST_OTP_NS_P           80                305 #define SRST_OTP_NS_P           80
306 #define SRST_OTP_NS_SBPI        81                306 #define SRST_OTP_NS_SBPI        81
307 #define SRST_OTP_NS_USR         82                307 #define SRST_OTP_NS_USR         82
308 #define SRST_OTP_PHY_P          83                308 #define SRST_OTP_PHY_P          83
309 #define SRST_OTP_PHY            84                309 #define SRST_OTP_PHY            84
310 #define SRST_GPIO0_P            86                310 #define SRST_GPIO0_P            86
311 #define SRST_GPIO1_P            87                311 #define SRST_GPIO1_P            87
312 #define SRST_GPIO2_P            88                312 #define SRST_GPIO2_P            88
313 #define SRST_GPIO3_P            89                313 #define SRST_GPIO3_P            89
314 #define SRST_GPIO4_P            90                314 #define SRST_GPIO4_P            90
315 #define SRST_GRF_P              91                315 #define SRST_GRF_P              91
316 #define SRST_USBSD_DET_P        92                316 #define SRST_USBSD_DET_P        92
317 #define SRST_PMU                93                317 #define SRST_PMU                93
318 #define SRST_PMU_PVTM           94                318 #define SRST_PMU_PVTM           94
319 #define SRST_USB_GRF_P          95                319 #define SRST_USB_GRF_P          95
320                                                   320 
321 /* cru_softrst_con6 */                            321 /* cru_softrst_con6 */
322 #define SRST_CPU_BOOST          96                322 #define SRST_CPU_BOOST          96
323 #define SRST_CPU_BOOST_P        97                323 #define SRST_CPU_BOOST_P        97
324 #define SRST_PWM1_P             98                324 #define SRST_PWM1_P             98
325 #define SRST_PWM1               99                325 #define SRST_PWM1               99
326 #define SRST_PWM2_P             100               326 #define SRST_PWM2_P             100
327 #define SRST_PWM2               101               327 #define SRST_PWM2               101
328 #define SRST_PERI_NIU_A         104               328 #define SRST_PERI_NIU_A         104
329 #define SRST_PERI_NIU_H         105               329 #define SRST_PERI_NIU_H         105
330 #define SRST_PERI_NIU_p         106               330 #define SRST_PERI_NIU_p         106
331 #define SRST_USB2OTG_H          107               331 #define SRST_USB2OTG_H          107
332 #define SRST_USB2OTG            108               332 #define SRST_USB2OTG            108
333 #define SRST_USB2OTG_ADP        109               333 #define SRST_USB2OTG_ADP        109
334 #define SRST_USB2HOST_H         110               334 #define SRST_USB2HOST_H         110
335 #define SRST_USB2HOST_ARB_H     111               335 #define SRST_USB2HOST_ARB_H     111
336                                                   336 
337 /* cru_softrst_con7 */                            337 /* cru_softrst_con7 */
338 #define SRST_USB2HOST_AUX_H     112               338 #define SRST_USB2HOST_AUX_H     112
339 #define SRST_USB2HOST_EHCI      113               339 #define SRST_USB2HOST_EHCI      113
340 #define SRST_USB2HOST           114               340 #define SRST_USB2HOST           114
341 #define SRST_USBPHYPOR          115               341 #define SRST_USBPHYPOR          115
342 #define SRST_UTMI0              116               342 #define SRST_UTMI0              116
343 #define SRST_UTMI1              117               343 #define SRST_UTMI1              117
344 #define SRST_SDIO_H             118               344 #define SRST_SDIO_H             118
345 #define SRST_EMMC_H             119               345 #define SRST_EMMC_H             119
346 #define SRST_SFC_H              120               346 #define SRST_SFC_H              120
347 #define SRST_SFC                121               347 #define SRST_SFC                121
348 #define SRST_SD_H               122               348 #define SRST_SD_H               122
349 #define SRST_NANDC_H            123               349 #define SRST_NANDC_H            123
350 #define SRST_NANDC_N            124               350 #define SRST_NANDC_N            124
351 #define SRST_MAC_A              125               351 #define SRST_MAC_A              125
352 #define SRST_CAN_P              126               352 #define SRST_CAN_P              126
353 #define SRST_OWIRE_P            127               353 #define SRST_OWIRE_P            127
354                                                   354 
355 /* cru_softrst_con8 */                            355 /* cru_softrst_con8 */
356 #define SRST_AUDIO_NIU_H        128               356 #define SRST_AUDIO_NIU_H        128
357 #define SRST_AUDIO_NIU_P        129               357 #define SRST_AUDIO_NIU_P        129
358 #define SRST_PDM_H              130               358 #define SRST_PDM_H              130
359 #define SRST_PDM_M              131               359 #define SRST_PDM_M              131
360 #define SRST_SPDIFTX_H          132               360 #define SRST_SPDIFTX_H          132
361 #define SRST_SPDIFTX_M          133               361 #define SRST_SPDIFTX_M          133
362 #define SRST_SPDIFRX_H          134               362 #define SRST_SPDIFRX_H          134
363 #define SRST_SPDIFRX_M          135               363 #define SRST_SPDIFRX_M          135
364 #define SRST_I2S0_8CH_H         136               364 #define SRST_I2S0_8CH_H         136
365 #define SRST_I2S0_8CH_TX_M      137               365 #define SRST_I2S0_8CH_TX_M      137
366 #define SRST_I2S0_8CH_RX_M      138               366 #define SRST_I2S0_8CH_RX_M      138
367 #define SRST_I2S1_8CH_H         139               367 #define SRST_I2S1_8CH_H         139
368 #define SRST_I2S1_8CH_TX_M      140               368 #define SRST_I2S1_8CH_TX_M      140
369 #define SRST_I2S1_8CH_RX_M      141               369 #define SRST_I2S1_8CH_RX_M      141
370 #define SRST_I2S2_8CH_H         142               370 #define SRST_I2S2_8CH_H         142
371 #define SRST_I2S2_8CH_TX_M      143               371 #define SRST_I2S2_8CH_TX_M      143
372                                                   372 
373 /* cru_softrst_con9 */                            373 /* cru_softrst_con9 */
374 #define SRST_I2S2_8CH_RX_M      144               374 #define SRST_I2S2_8CH_RX_M      144
375 #define SRST_I2S3_8CH_H         145               375 #define SRST_I2S3_8CH_H         145
376 #define SRST_I2S3_8CH_TX_M      146               376 #define SRST_I2S3_8CH_TX_M      146
377 #define SRST_I2S3_8CH_RX_M      147               377 #define SRST_I2S3_8CH_RX_M      147
378 #define SRST_I2S0_2CH_H         148               378 #define SRST_I2S0_2CH_H         148
379 #define SRST_I2S0_2CH_M         149               379 #define SRST_I2S0_2CH_M         149
380 #define SRST_I2S1_2CH_H         150               380 #define SRST_I2S1_2CH_H         150
381 #define SRST_I2S1_2CH_M         151               381 #define SRST_I2S1_2CH_M         151
382 #define SRST_VAD_H              152               382 #define SRST_VAD_H              152
383 #define SRST_ACODEC_P           153               383 #define SRST_ACODEC_P           153
384                                                   384 
385 #endif                                            385 #endif
386                                                   386 

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