1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright 2016 Maxime Ripard 2 * Copyright 2016 Maxime Ripard
4 * 3 *
5 * Maxime Ripard <maxime.ripard@free-electrons 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify
>> 7 * it under the terms of the GNU General Public License as published by
>> 8 * the Free Software Foundation; either version 2 of the License, or
>> 9 * (at your option) any later version.
>> 10 *
>> 11 * This program is distributed in the hope that it will be useful,
>> 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 14 * GNU General Public License for more details.
6 */ 15 */
7 16
8 #ifndef _DT_BINDINGS_CLK_SUN5I_H_ 17 #ifndef _DT_BINDINGS_CLK_SUN5I_H_
9 #define _DT_BINDINGS_CLK_SUN5I_H_ 18 #define _DT_BINDINGS_CLK_SUN5I_H_
10 19
11 #define CLK_HOSC 1 20 #define CLK_HOSC 1
12 21
13 #define CLK_PLL_VIDEO0_2X 9 <<
14 <<
15 #define CLK_PLL_VIDEO1_2X 16 <<
16 #define CLK_CPU 17 22 #define CLK_CPU 17
17 23
18 #define CLK_AHB_OTG 23 24 #define CLK_AHB_OTG 23
19 #define CLK_AHB_EHCI 24 25 #define CLK_AHB_EHCI 24
20 #define CLK_AHB_OHCI 25 26 #define CLK_AHB_OHCI 25
21 #define CLK_AHB_SS 26 27 #define CLK_AHB_SS 26
22 #define CLK_AHB_DMA 27 28 #define CLK_AHB_DMA 27
23 #define CLK_AHB_BIST 28 29 #define CLK_AHB_BIST 28
24 #define CLK_AHB_MMC0 29 30 #define CLK_AHB_MMC0 29
25 #define CLK_AHB_MMC1 30 31 #define CLK_AHB_MMC1 30
26 #define CLK_AHB_MMC2 31 32 #define CLK_AHB_MMC2 31
27 #define CLK_AHB_NAND 32 33 #define CLK_AHB_NAND 32
28 #define CLK_AHB_SDRAM 33 34 #define CLK_AHB_SDRAM 33
29 #define CLK_AHB_EMAC 34 35 #define CLK_AHB_EMAC 34
30 #define CLK_AHB_TS 35 36 #define CLK_AHB_TS 35
31 #define CLK_AHB_SPI0 36 37 #define CLK_AHB_SPI0 36
32 #define CLK_AHB_SPI1 37 38 #define CLK_AHB_SPI1 37
33 #define CLK_AHB_SPI2 38 39 #define CLK_AHB_SPI2 38
34 #define CLK_AHB_GPS 39 40 #define CLK_AHB_GPS 39
35 #define CLK_AHB_HSTIMER 40 41 #define CLK_AHB_HSTIMER 40
36 #define CLK_AHB_VE 41 42 #define CLK_AHB_VE 41
37 #define CLK_AHB_TVE 42 43 #define CLK_AHB_TVE 42
38 #define CLK_AHB_LCD 43 44 #define CLK_AHB_LCD 43
39 #define CLK_AHB_CSI 44 45 #define CLK_AHB_CSI 44
40 #define CLK_AHB_HDMI 45 46 #define CLK_AHB_HDMI 45
41 #define CLK_AHB_DE_BE 46 47 #define CLK_AHB_DE_BE 46
42 #define CLK_AHB_DE_FE 47 48 #define CLK_AHB_DE_FE 47
43 #define CLK_AHB_IEP 48 49 #define CLK_AHB_IEP 48
44 #define CLK_AHB_GPU 49 50 #define CLK_AHB_GPU 49
45 #define CLK_APB0_CODEC 50 51 #define CLK_APB0_CODEC 50
46 #define CLK_APB0_SPDIF 51 52 #define CLK_APB0_SPDIF 51
47 #define CLK_APB0_I2S 52 53 #define CLK_APB0_I2S 52
48 #define CLK_APB0_PIO 53 54 #define CLK_APB0_PIO 53
49 #define CLK_APB0_IR 54 55 #define CLK_APB0_IR 54
50 #define CLK_APB0_KEYPAD 55 56 #define CLK_APB0_KEYPAD 55
51 #define CLK_APB1_I2C0 56 57 #define CLK_APB1_I2C0 56
52 #define CLK_APB1_I2C1 57 58 #define CLK_APB1_I2C1 57
53 #define CLK_APB1_I2C2 58 59 #define CLK_APB1_I2C2 58
54 #define CLK_APB1_UART0 59 60 #define CLK_APB1_UART0 59
55 #define CLK_APB1_UART1 60 61 #define CLK_APB1_UART1 60
56 #define CLK_APB1_UART2 61 62 #define CLK_APB1_UART2 61
57 #define CLK_APB1_UART3 62 63 #define CLK_APB1_UART3 62
58 #define CLK_NAND 63 64 #define CLK_NAND 63
59 #define CLK_MMC0 64 65 #define CLK_MMC0 64
60 #define CLK_MMC1 65 66 #define CLK_MMC1 65
61 #define CLK_MMC2 66 67 #define CLK_MMC2 66
62 #define CLK_TS 67 68 #define CLK_TS 67
63 #define CLK_SS 68 69 #define CLK_SS 68
64 #define CLK_SPI0 69 70 #define CLK_SPI0 69
65 #define CLK_SPI1 70 71 #define CLK_SPI1 70
66 #define CLK_SPI2 71 72 #define CLK_SPI2 71
67 #define CLK_IR 72 73 #define CLK_IR 72
68 #define CLK_I2S 73 74 #define CLK_I2S 73
69 #define CLK_SPDIF 74 75 #define CLK_SPDIF 74
70 #define CLK_KEYPAD 75 76 #define CLK_KEYPAD 75
71 #define CLK_USB_OHCI 76 77 #define CLK_USB_OHCI 76
72 #define CLK_USB_PHY0 77 78 #define CLK_USB_PHY0 77
73 #define CLK_USB_PHY1 78 79 #define CLK_USB_PHY1 78
74 #define CLK_GPS 79 80 #define CLK_GPS 79
75 #define CLK_DRAM_VE 80 81 #define CLK_DRAM_VE 80
76 #define CLK_DRAM_CSI 81 82 #define CLK_DRAM_CSI 81
77 #define CLK_DRAM_TS 82 83 #define CLK_DRAM_TS 82
78 #define CLK_DRAM_TVE 83 84 #define CLK_DRAM_TVE 83
79 #define CLK_DRAM_DE_FE 84 85 #define CLK_DRAM_DE_FE 84
80 #define CLK_DRAM_DE_BE 85 86 #define CLK_DRAM_DE_BE 85
81 #define CLK_DRAM_ACE 86 87 #define CLK_DRAM_ACE 86
82 #define CLK_DRAM_IEP 87 88 #define CLK_DRAM_IEP 87
83 #define CLK_DE_BE 88 89 #define CLK_DE_BE 88
84 #define CLK_DE_FE 89 90 #define CLK_DE_FE 89
85 #define CLK_TCON_CH0 90 91 #define CLK_TCON_CH0 90
86 92
87 #define CLK_TCON_CH1 92 93 #define CLK_TCON_CH1 92
88 #define CLK_CSI 93 94 #define CLK_CSI 93
89 #define CLK_VE 94 95 #define CLK_VE 94
90 #define CLK_CODEC 95 96 #define CLK_CODEC 95
91 #define CLK_AVS 96 97 #define CLK_AVS 96
92 #define CLK_HDMI 97 98 #define CLK_HDMI 97
93 #define CLK_GPU 98 99 #define CLK_GPU 98
94 #define CLK_MBUS 99 !! 100
95 #define CLK_IEP 100 101 #define CLK_IEP 100
96 102
97 #endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ 103 #endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
98 104
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