Linux/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

Diff markup

1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION !! 2 /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ 3 3 4 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 4 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 5 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 5 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 6 6 7 /** 7 /** 8 * @file 8 * @file 9 * @defgroup bpmp_clock_ids Clock ID's 9 * @defgroup bpmp_clock_ids Clock ID's 10 * @{ 10 * @{ 11 */ 11 */ 12 /** @brief output of mux controlled by CLK_RST << 13 #define TEGRA234_CLK_ACTMON << 14 /** @brief output of gate CLK_ENB_ADSP */ << 15 #define TEGRA234_CLK_ADSP << 16 /** @brief output of gate CLK_ENB_ADSPNEON */ << 17 #define TEGRA234_CLK_ADSPNEON << 18 /** output of mux controlled by CLK_RST_CONTRO << 19 #define TEGRA234_CLK_AHUB << 20 /** @brief output of gate CLK_ENB_APB2APE */ << 21 #define TEGRA234_CLK_APB2APE << 22 /** @brief output of mux controlled by CLK_RST << 23 #define TEGRA234_CLK_APE << 24 /** @brief output of mux controlled by CLK_RST << 25 #define TEGRA234_CLK_AUD_MCLK << 26 /** @brief output of mux controlled by CLK_RST << 27 #define TEGRA234_CLK_AXI_CBB << 28 /** @brief output of mux controlled by CLK_RST << 29 #define TEGRA234_CLK_CAN1 << 30 /** @brief output of gate CLK_ENB_CAN1_HOST */ << 31 #define TEGRA234_CLK_CAN1_HOST << 32 /** @brief output of mux controlled by CLK_RST << 33 #define TEGRA234_CLK_CAN2 << 34 /** @brief output of gate CLK_ENB_CAN2_HOST */ << 35 #define TEGRA234_CLK_CAN2_HOST << 36 /** @brief output of divider CLK_RST_CONTROLLE << 37 #define TEGRA234_CLK_CLK_M << 38 /** @brief output of mux controlled by CLK_RST << 39 #define TEGRA234_CLK_DMIC1 << 40 /** @brief output of mux controlled by CLK_RST << 41 #define TEGRA234_CLK_DMIC2 << 42 /** @brief output of mux controlled by CLK_RST << 43 #define TEGRA234_CLK_DMIC3 << 44 /** @brief output of mux controlled by CLK_RST << 45 #define TEGRA234_CLK_DMIC4 << 46 /** @brief output of gate CLK_ENB_DPAUX */ << 47 #define TEGRA234_CLK_DPAUX << 48 /** @brief output of mux controlled by CLK_RST << 49 #define TEGRA234_CLK_NVJPG1 << 50 /** << 51 * @brief output of mux controlled by CLK_RST_ << 52 * divided by the divider controlled by ACLK_C << 53 * CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER << 54 */ << 55 #define TEGRA234_CLK_ACLK << 56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_E << 57 #define TEGRA234_CLK_MSS_ENCRYPT << 58 /** @brief clock recovered from EAVB input */ << 59 #define TEGRA234_CLK_EQOS_RX_INPUT << 60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_A << 61 #define TEGRA234_CLK_AON_APB << 62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE div << 63 #define TEGRA234_CLK_AON_NIC << 64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_C << 65 #define TEGRA234_CLK_AON_CPU_NIC << 66 /** @brief PLL controlled by CLK_RST_CONTROLLE << 67 #define TEGRA234_CLK_PLLA1 << 68 /** @brief output of mux controlled by CLK_RST << 69 #define TEGRA234_CLK_DSPK1 << 70 /** @brief output of mux controlled by CLK_RST << 71 #define TEGRA234_CLK_DSPK2 << 72 /** 12 /** 73 * @brief controls the EMC clock frequency. 13 * @brief controls the EMC clock frequency. 74 * @details Doing a clk_set_rate on this clock 14 * @details Doing a clk_set_rate on this clock will select the 75 * appropriate clock source, program the sourc 15 * appropriate clock source, program the source rate and execute a 76 * specific sequence to switch to the new cloc 16 * specific sequence to switch to the new clock source for both memory 77 * controllers. This can be used to control th 17 * controllers. This can be used to control the balance between memory 78 * throughput and memory controller power. 18 * throughput and memory controller power. 79 */ 19 */ 80 #define TEGRA234_CLK_EMC 20 #define TEGRA234_CLK_EMC 31U 81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_ << 82 #define TEGRA234_CLK_EQOS_AXI << 83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_ << 84 #define TEGRA234_CLK_EQOS_PTP_REF << 85 /** @brief output of gate CLK_ENB_EQOS_RX */ << 86 #define TEGRA234_CLK_EQOS_RX << 87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_ << 88 #define TEGRA234_CLK_EQOS_TX << 89 /** @brief output of mux controlled by CLK_RST << 90 #define TEGRA234_CLK_EXTPERIPH1 << 91 /** @brief output of mux controlled by CLK_RST << 92 #define TEGRA234_CLK_EXTPERIPH2 << 93 /** @brief output of mux controlled by CLK_RST << 94 #define TEGRA234_CLK_EXTPERIPH3 << 95 /** @brief output of mux controlled by CLK_RST << 96 #define TEGRA234_CLK_EXTPERIPH4 << 97 /** @brief output of gate CLK_ENB_FUSE */ 21 /** @brief output of gate CLK_ENB_FUSE */ 98 #define TEGRA234_CLK_FUSE 22 #define TEGRA234_CLK_FUSE 40U 99 /** @brief output of GPU GPC0 clkGen (in 1x mo << 100 #define TEGRA234_CLK_GPC0CLK << 101 /** @brief TODO */ << 102 #define TEGRA234_CLK_GPU_PWR << 103 /** output of mux controlled by CLK_RST_CONTRO << 104 /** @brief output of mux controlled by CLK_RST << 105 #define TEGRA234_CLK_HOST1X << 106 /** @brief xusb_hs_hsicp_clk */ << 107 #define TEGRA234_CLK_XUSB_HS_HSICP << 108 /** @brief output of mux controlled by CLK_RST << 109 #define TEGRA234_CLK_I2C1 << 110 /** @brief output of mux controlled by CLK_RST << 111 #define TEGRA234_CLK_I2C2 << 112 /** @brief output of mux controlled by CLK_RST << 113 #define TEGRA234_CLK_I2C3 << 114 /** output of mux controlled by CLK_RST_CONTRO << 115 #define TEGRA234_CLK_I2C4 << 116 /** @brief output of mux controlled by CLK_RST << 117 #define TEGRA234_CLK_I2C6 << 118 /** @brief output of mux controlled by CLK_RST << 119 #define TEGRA234_CLK_I2C7 << 120 /** @brief output of mux controlled by CLK_RST << 121 #define TEGRA234_CLK_I2C8 << 122 /** @brief output of mux controlled by CLK_RST << 123 #define TEGRA234_CLK_I2C9 << 124 /** output of mux controlled by CLK_RST_CONTRO << 125 #define TEGRA234_CLK_I2S1 << 126 /** @brief clock recovered from I2S1 input */ << 127 #define TEGRA234_CLK_I2S1_SYNC_INPUT << 128 /** @brief output of mux controlled by CLK_RST << 129 #define TEGRA234_CLK_I2S2 << 130 /** @brief clock recovered from I2S2 input */ << 131 #define TEGRA234_CLK_I2S2_SYNC_INPUT << 132 /** @brief output of mux controlled by CLK_RST << 133 #define TEGRA234_CLK_I2S3 << 134 /** @brief clock recovered from I2S3 input */ << 135 #define TEGRA234_CLK_I2S3_SYNC_INPUT << 136 /** output of mux controlled by CLK_RST_CONTRO << 137 #define TEGRA234_CLK_I2S4 << 138 /** @brief clock recovered from I2S4 input */ << 139 #define TEGRA234_CLK_I2S4_SYNC_INPUT << 140 /** output of mux controlled by CLK_RST_CONTRO << 141 #define TEGRA234_CLK_I2S5 << 142 /** @brief clock recovered from I2S5 input */ << 143 #define TEGRA234_CLK_I2S5_SYNC_INPUT << 144 /** @brief output of mux controlled by CLK_RST << 145 #define TEGRA234_CLK_I2S6 << 146 /** @brief clock recovered from I2S6 input */ << 147 #define TEGRA234_CLK_I2S6_SYNC_INPUT << 148 /** @brief output of mux controlled by CLK_RST << 149 #define TEGRA234_CLK_ISP << 150 /** @brief Monitored branch of EQOS_RX clock * << 151 #define TEGRA234_CLK_EQOS_RX_M << 152 /** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWIT << 153 #define TEGRA234_CLK_MAUD << 154 /** @brief output of gate CLK_ENB_MIPI_CAL */ << 155 #define TEGRA234_CLK_MIPI_CAL << 156 /** @brief output of the divider CLK_RST_CONTR << 157 #define TEGRA234_CLK_MPHY_CORE_PLL_FIXED << 158 /** @brief output of gate CLK_ENB_MPHY_L0_RX_A << 159 #define TEGRA234_CLK_MPHY_L0_RX_ANA << 160 /** @brief output of gate CLK_ENB_MPHY_L0_RX_L << 161 #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT << 162 /** @brief output of gate CLK_ENB_MPHY_L0_RX_S << 163 #define TEGRA234_CLK_MPHY_L0_RX_SYMB << 164 /** @brief output of gate CLK_ENB_MPHY_L0_TX_L << 165 #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT << 166 /** @brief output of gate CLK_ENB_MPHY_L0_TX_S << 167 #define TEGRA234_CLK_MPHY_L0_TX_SYMB << 168 /** @brief output of gate CLK_ENB_MPHY_L1_RX_A << 169 #define TEGRA234_CLK_MPHY_L1_RX_ANA << 170 /** @brief output of the divider CLK_RST_CONTR << 171 #define TEGRA234_CLK_MPHY_TX_1MHZ_REF << 172 /** @brief output of mux controlled by CLK_RST << 173 #define TEGRA234_CLK_NVCSI << 174 /** @brief output of mux controlled by CLK_RST << 175 #define TEGRA234_CLK_NVCSILP << 176 /** @brief output of mux controlled by CLK_RST << 177 #define TEGRA234_CLK_NVDEC << 178 /** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITC << 179 #define TEGRA234_CLK_HUB << 180 /** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_D << 181 #define TEGRA234_CLK_DISP << 182 /** @brief RG_CLK_CTRL__0_DIV divider output ( << 183 #define TEGRA234_CLK_NVDISPLAY_P0 << 184 /** @brief RG_CLK_CTRL__1_DIV divider output ( << 185 #define TEGRA234_CLK_NVDISPLAY_P1 << 186 /** @brief DSC_CLK (DISPCLK ÷ 3) */ << 187 #define TEGRA234_CLK_DSC << 188 /** @brief output of mux controlled by CLK_RST << 189 #define TEGRA234_CLK_NVENC << 190 /** @brief output of mux controlled by CLK_RST << 191 #define TEGRA234_CLK_NVJPG << 192 /** @brief input from Tegra's XTAL_IN */ << 193 #define TEGRA234_CLK_OSC << 194 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_T << 195 #define TEGRA234_CLK_AON_TOUCH << 196 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_ << 197 #define TEGRA234_CLK_PLLA << 198 /** @brief PLL controlled by CLK_RST_CONTROLLE << 199 #define TEGRA234_CLK_PLLAON << 200 /** Fixed 100MHz PLL for PCIe, SATA and supers << 201 #define TEGRA234_CLK_PLLE << 202 /** @brief PLLP vco output */ << 203 #define TEGRA234_CLK_PLLP << 204 /** @brief PLLP clk output */ << 205 #define TEGRA234_CLK_PLLP_OUT0 << 206 /** Fixed frequency 960MHz PLL for USB and EAV << 207 #define TEGRA234_CLK_UTMIP_PLL << 208 /** @brief output of the divider CLK_RST_CONTR << 209 #define TEGRA234_CLK_PLLA_OUT0 << 210 /** @brief output of mux controlled by CLK_RST << 211 #define TEGRA234_CLK_PWM1 << 212 /** @brief output of mux controlled by CLK_RST << 213 #define TEGRA234_CLK_PWM2 << 214 /** @brief output of mux controlled by CLK_RST << 215 #define TEGRA234_CLK_PWM3 << 216 /** @brief output of mux controlled by CLK_RST << 217 #define TEGRA234_CLK_PWM4 << 218 /** @brief output of mux controlled by CLK_RST << 219 #define TEGRA234_CLK_PWM5 << 220 /** @brief output of mux controlled by CLK_RST << 221 #define TEGRA234_CLK_PWM6 << 222 /** @brief output of mux controlled by CLK_RST << 223 #define TEGRA234_CLK_PWM7 << 224 /** @brief output of mux controlled by CLK_RST << 225 #define TEGRA234_CLK_PWM8 << 226 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_C << 227 #define TEGRA234_CLK_RCE_CPU_NIC << 228 /** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE div << 229 #define TEGRA234_CLK_RCE_NIC << 230 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I << 231 #define TEGRA234_CLK_AON_I2C_SLOW << 232 /** @brief output of mux controlled by CLK_RST << 233 #define TEGRA234_CLK_SCE_CPU_NIC << 234 /** @brief output of divider CLK_RST_CONTROLLE << 235 #define TEGRA234_CLK_SCE_NIC << 236 /** @brief output of mux controlled by CLK_RST << 237 #define TEGRA234_CLK_SDMMC1 << 238 /** @brief Logical clk for setting the UPHY PL << 239 #define TEGRA234_CLK_UPHY_PLL3 << 240 /** @brief output of mux controlled by CLK_RST 23 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 241 #define TEGRA234_CLK_SDMMC4 24 #define TEGRA234_CLK_SDMMC4 123U 242 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE sw << 243 #define TEGRA234_CLK_SE << 244 /** @brief VPLL select for sor0_ref clk driven << 245 #define TEGRA234_CLK_SOR0_PLL_REF << 246 /** @brief Output of mux controlled by disp_2c << 247 #define TEGRA234_CLK_SOR0_REF << 248 /** @brief VPLL select for sor1_ref clk driven << 249 #define TEGRA234_CLK_SOR1_PLL_REF << 250 /** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider << 251 #define TEGRA234_CLK_PRE_SOR0_REF << 252 /** @brief Output of mux controlled by disp_2c << 253 #define TEGRA234_CLK_SOR1_REF << 254 /** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider << 255 #define TEGRA234_CLK_PRE_SOR1_REF << 256 /** @brief output of gate CLK_ENB_SOR_SAFE */ << 257 #define TEGRA234_CLK_SOR_SAFE << 258 /** @brief SOR_CLK_CTRL__0_DIV divider output << 259 #define TEGRA234_CLK_SOR0_DIV << 260 /** @brief output of mux controlled by CLK_RST << 261 #define TEGRA234_CLK_DMIC5 << 262 /** @brief output of mux controlled by CLK_RST << 263 #define TEGRA234_CLK_SPI1 << 264 /** @brief output of mux controlled by CLK_RST << 265 #define TEGRA234_CLK_SPI2 << 266 /** @brief output of mux controlled by CLK_RST << 267 #define TEGRA234_CLK_SPI3 << 268 /** @brief output of mux controlled by CLK_RST << 269 #define TEGRA234_CLK_I2C_SLOW << 270 /** @brief output of mux controlled by CLK_RST << 271 #define TEGRA234_CLK_SYNC_DMIC1 << 272 /** @brief output of mux controlled by CLK_RST << 273 #define TEGRA234_CLK_SYNC_DMIC2 << 274 /** @brief output of mux controlled by CLK_RST << 275 #define TEGRA234_CLK_SYNC_DMIC3 << 276 /** @brief output of mux controlled by CLK_RST << 277 #define TEGRA234_CLK_SYNC_DMIC4 << 278 /** @brief output of mux controlled by CLK_RST << 279 #define TEGRA234_CLK_SYNC_DSPK1 << 280 /** @brief output of mux controlled by CLK_RST << 281 #define TEGRA234_CLK_SYNC_DSPK2 << 282 /** @brief output of mux controlled by CLK_RST << 283 #define TEGRA234_CLK_SYNC_I2S1 << 284 /** @brief output of mux controlled by CLK_RST << 285 #define TEGRA234_CLK_SYNC_I2S2 << 286 /** @brief output of mux controlled by CLK_RST << 287 #define TEGRA234_CLK_SYNC_I2S3 << 288 /** @brief output of mux controlled by CLK_RST << 289 #define TEGRA234_CLK_SYNC_I2S4 << 290 /** @brief output of mux controlled by CLK_RST << 291 #define TEGRA234_CLK_SYNC_I2S5 << 292 /** @brief output of mux controlled by CLK_RST << 293 #define TEGRA234_CLK_SYNC_I2S6 << 294 /** @brief controls MPHY_FORCE_LS_MODE upon en << 295 #define TEGRA234_CLK_MPHY_FORCE_LS_MODE << 296 /** @brief output of mux controlled by CLK_RST << 297 #define TEGRA234_CLK_TACH0 << 298 /** output of mux controlled by CLK_RST_CONTRO << 299 #define TEGRA234_CLK_TSEC << 300 /** output of mux controlled by CLK_RST_CONTRO << 301 #define TEGRA234_CLK_TSEC_PKA << 302 /** @brief output of mux controlled by CLK_RST 25 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 303 #define TEGRA234_CLK_UARTA 26 #define TEGRA234_CLK_UARTA 155U 304 /** @brief output of mux controlled by CLK_RST << 305 #define TEGRA234_CLK_UARTB << 306 /** @brief output of mux controlled by CLK_RST << 307 #define TEGRA234_CLK_UARTC << 308 /** @brief output of mux controlled by CLK_RST << 309 #define TEGRA234_CLK_UARTD << 310 /** @brief output of mux controlled by CLK_RST << 311 #define TEGRA234_CLK_UARTE << 312 /** @brief output of mux controlled by CLK_RST << 313 #define TEGRA234_CLK_UARTF << 314 /** @brief output of gate CLK_ENB_PEX1_CORE_6 << 315 #define TEGRA234_CLK_PEX1_C6_CORE << 316 /** @brief output of mux controlled by CLK_RST << 317 #define TEGRA234_CLK_UART_FST_MIPI_CAL << 318 /** @brief output of mux controlled by CLK_RST << 319 #define TEGRA234_CLK_UFSDEV_REF << 320 /** @brief output of mux controlled by CLK_RST << 321 #define TEGRA234_CLK_UFSHC << 322 /** @brief output of gate CLK_ENB_USB2_TRK */ << 323 #define TEGRA234_CLK_USB2_TRK << 324 /** @brief output of mux controlled by CLK_RST << 325 #define TEGRA234_CLK_VI << 326 /** @brief output of mux controlled by CLK_RST << 327 #define TEGRA234_CLK_VIC << 328 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE << 329 #define TEGRA234_CLK_CSITE << 330 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST s << 331 #define TEGRA234_CLK_IST << 332 /** @brief output of mux controlled by CLK_RST << 333 #define TEGRA234_CLK_JTAG_INTFC_PRE_CG << 334 /** @brief output of gate CLK_ENB_PEX2_CORE_7 << 335 #define TEGRA234_CLK_PEX2_C7_CORE << 336 /** @brief output of gate CLK_ENB_PEX2_CORE_8 << 337 #define TEGRA234_CLK_PEX2_C8_CORE << 338 /** @brief output of gate CLK_ENB_PEX2_CORE_9 << 339 #define TEGRA234_CLK_PEX2_C9_CORE << 340 /** @brief dla0_falcon_clk */ << 341 #define TEGRA234_CLK_DLA0_FALCON << 342 /** @brief dla0_core_clk */ << 343 #define TEGRA234_CLK_DLA0_CORE << 344 /** @brief dla1_falcon_clk */ << 345 #define TEGRA234_CLK_DLA1_FALCON << 346 /** @brief dla1_core_clk */ << 347 #define TEGRA234_CLK_DLA1_CORE << 348 /** @brief Output of mux controlled by disp_2c << 349 #define TEGRA234_CLK_SOR0 << 350 /** @brief Output of mux controlled by disp_2c << 351 #define TEGRA234_CLK_SOR1 << 352 /** @brief DP macro feedback clock (same as LI << 353 #define TEGRA234_CLK_SOR_PAD_INPUT << 354 /** @brief Output of mux controlled by disp_2c << 355 #define TEGRA234_CLK_PRE_SF0 << 356 /** @brief Output of mux controlled by disp_2c << 357 #define TEGRA234_CLK_SF0 << 358 /** @brief Output of mux controlled by disp_2c << 359 #define TEGRA234_CLK_SF1 << 360 /** @brief CLKOUT_AB output from DSI BRICK A ( << 361 #define TEGRA234_CLK_DSI_PAD_INPUT << 362 /** @brief output of gate CLK_ENB_PEX2_CORE_10 << 363 #define TEGRA234_CLK_PEX2_C10_CORE << 364 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI << 365 #define TEGRA234_CLK_UARTI << 366 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ << 367 #define TEGRA234_CLK_UARTJ << 368 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH << 369 #define TEGRA234_CLK_UARTH << 370 /** @brief ungated version of fuse clk */ << 371 #define TEGRA234_CLK_FUSE_SERIAL << 372 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 << 373 #define TEGRA234_CLK_QSPI0_2X_PM << 374 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 << 375 #define TEGRA234_CLK_QSPI1_2X_PM << 376 /** @brief output of the divider QSPI_CLK_DIV2 << 377 #define TEGRA234_CLK_QSPI0_PM << 378 /** @brief output of the divider QSPI_CLK_DIV2 << 379 #define TEGRA234_CLK_QSPI1_PM << 380 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CO << 381 #define TEGRA234_CLK_VI_CONST << 382 /** @brief NAFLL clock source for BPMP */ << 383 #define TEGRA234_CLK_NAFLL_BPMP << 384 /** @brief NAFLL clock source for SCE */ << 385 #define TEGRA234_CLK_NAFLL_SCE << 386 /** @brief NAFLL clock source for NVDEC */ << 387 #define TEGRA234_CLK_NAFLL_NVDEC << 388 /** @brief NAFLL clock source for NVJPG */ << 389 #define TEGRA234_CLK_NAFLL_NVJPG << 390 /** @brief NAFLL clock source for TSEC */ << 391 #define TEGRA234_CLK_NAFLL_TSEC << 392 /** @brief NAFLL clock source for VI */ << 393 #define TEGRA234_CLK_NAFLL_VI << 394 /** @brief NAFLL clock source for SE */ << 395 #define TEGRA234_CLK_NAFLL_SE << 396 /** @brief NAFLL clock source for NVENC */ << 397 #define TEGRA234_CLK_NAFLL_NVENC << 398 /** @brief NAFLL clock source for ISP */ << 399 #define TEGRA234_CLK_NAFLL_ISP << 400 /** @brief NAFLL clock source for VIC */ << 401 #define TEGRA234_CLK_NAFLL_VIC << 402 /** @brief NAFLL clock source for AXICBB */ << 403 #define TEGRA234_CLK_NAFLL_AXICBB << 404 /** @brief NAFLL clock source for NVJPG1 */ << 405 #define TEGRA234_CLK_NAFLL_NVJPG1 << 406 /** @brief NAFLL clock source for PVA core */ << 407 #define TEGRA234_CLK_NAFLL_PVA0_CORE << 408 /** @brief NAFLL clock source for PVA VPS */ << 409 #define TEGRA234_CLK_NAFLL_PVA0_VPS << 410 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAP << 411 #define TEGRA234_CLK_DBGAPB << 412 /** @brief NAFLL clock source for RCE */ << 413 #define TEGRA234_CLK_NAFLL_RCE << 414 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA sw << 415 #define TEGRA234_CLK_LA << 416 /** @brief output of the divider CLK_RST_CONTR << 417 #define TEGRA234_CLK_PLLP_OUT_JTAG << 418 /** @brief AXI_CBB branch sharing gate control << 419 #define TEGRA234_CLK_SDMMC4_AXICIF << 420 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC 27 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 421 #define TEGRA234_CLK_SDMMC_LEGACY_TM 28 #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 422 /** @brief output of gate CLK_ENB_PEX0_CORE_0 << 423 #define TEGRA234_CLK_PEX0_C0_CORE << 424 /** @brief output of gate CLK_ENB_PEX0_CORE_1 << 425 #define TEGRA234_CLK_PEX0_C1_CORE << 426 /** @brief output of gate CLK_ENB_PEX0_CORE_2 << 427 #define TEGRA234_CLK_PEX0_C2_CORE << 428 /** @brief output of gate CLK_ENB_PEX0_CORE_3 << 429 #define TEGRA234_CLK_PEX0_C3_CORE << 430 /** @brief output of gate CLK_ENB_PEX0_CORE_4 << 431 #define TEGRA234_CLK_PEX0_C4_CORE << 432 /** @brief output of gate CLK_ENB_PEX1_CORE_5 << 433 #define TEGRA234_CLK_PEX1_C5_CORE << 434 /** @brief Monitored branch of PEX0_C0_CORE cl << 435 #define TEGRA234_CLK_PEX0_C0_CORE_M << 436 /** @brief Monitored branch of PEX0_C1_CORE cl << 437 #define TEGRA234_CLK_PEX0_C1_CORE_M << 438 /** @brief Monitored branch of PEX0_C2_CORE cl << 439 #define TEGRA234_CLK_PEX0_C2_CORE_M << 440 /** @brief Monitored branch of PEX0_C3_CORE cl << 441 #define TEGRA234_CLK_PEX0_C3_CORE_M << 442 /** @brief Monitored branch of PEX0_C4_CORE cl << 443 #define TEGRA234_CLK_PEX0_C4_CORE_M << 444 /** @brief Monitored branch of PEX1_C5_CORE cl << 445 #define TEGRA234_CLK_PEX1_C5_CORE_M << 446 /** @brief Monitored branch of PEX1_C6_CORE cl << 447 #define TEGRA234_CLK_PEX1_C6_CORE_M << 448 /** @brief output of GPU GPC1 clkGen (in 1x mo << 449 #define TEGRA234_CLK_GPC1CLK << 450 /** @brief PLL controlled by CLK_RST_CONTROLLE 29 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 451 #define TEGRA234_CLK_PLLC4 30 #define TEGRA234_CLK_PLLC4 237U 452 /** @brief PLLC4 VCO followed by DIV3 path */ << 453 #define TEGRA234_CLK_PLLC4_OUT1 << 454 /** @brief PLLC4 VCO followed by DIV5 path */ << 455 #define TEGRA234_CLK_PLLC4_OUT2 << 456 /** @brief output of the mux controlled by PLL << 457 #define TEGRA234_CLK_PLLC4_MUXED << 458 /** @brief PLLC4 VCO followed by DIV2 path */ << 459 #define TEGRA234_CLK_PLLC4_VCO_DIV2 << 460 /** @brief PLL controlled by CLK_RST_CONTROLLE << 461 #define TEGRA234_CLK_PLLNVHS << 462 /** @brief Monitored branch of PEX2_C7_CORE cl << 463 #define TEGRA234_CLK_PEX2_C7_CORE_M << 464 /** @brief Monitored branch of PEX2_C8_CORE cl << 465 #define TEGRA234_CLK_PEX2_C8_CORE_M << 466 /** @brief Monitored branch of PEX2_C9_CORE cl << 467 #define TEGRA234_CLK_PEX2_C9_CORE_M << 468 /** @brief Monitored branch of PEX2_C10_CORE c << 469 #define TEGRA234_CLK_PEX2_C10_CORE_M << 470 /** @brief RX clock recovered from MGBE0 lane << 471 #define TEGRA234_CLK_MGBE0_RX_INPUT << 472 /** @brief RX clock recovered from MGBE1 lane << 473 #define TEGRA234_CLK_MGBE1_RX_INPUT << 474 /** @brief RX clock recovered from MGBE2 lane << 475 #define TEGRA234_CLK_MGBE2_RX_INPUT << 476 /** @brief RX clock recovered from MGBE3 lane << 477 #define TEGRA234_CLK_MGBE3_RX_INPUT << 478 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_S << 479 #define TEGRA234_CLK_PEX_SATA_USB_RX_BYP << 480 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_U << 481 #define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT << 482 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_U << 483 #define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT << 484 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_U << 485 #define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT << 486 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_U << 487 #define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT << 488 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_ << 489 #define TEGRA234_CLK_NVHS_RX_BYP_REF << 490 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_ << 491 #define TEGRA234_CLK_NVHS_PLL0_MGMT << 492 /** @brief xusb_core_dev_clk */ << 493 #define TEGRA234_CLK_XUSB_CORE_DEV << 494 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_ << 495 #define TEGRA234_CLK_XUSB_CORE_MUX << 496 /** @brief xusb_core_host_clk */ << 497 #define TEGRA234_CLK_XUSB_CORE_HOST << 498 /** @brief xusb_core_superspeed_clk */ << 499 #define TEGRA234_CLK_XUSB_CORE_SS << 500 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_ << 501 #define TEGRA234_CLK_XUSB_FALCON << 502 /** @brief xusb_falcon_host_clk */ << 503 #define TEGRA234_CLK_XUSB_FALCON_HOST << 504 /** @brief xusb_falcon_superspeed_clk */ << 505 #define TEGRA234_CLK_XUSB_FALCON_SS << 506 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_ << 507 #define TEGRA234_CLK_XUSB_FS << 508 /** @brief xusb_fs_host_clk */ << 509 #define TEGRA234_CLK_XUSB_FS_HOST << 510 /** @brief xusb_fs_dev_clk */ << 511 #define TEGRA234_CLK_XUSB_FS_DEV << 512 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_ << 513 #define TEGRA234_CLK_XUSB_SS << 514 /** @brief xusb_ss_dev_clk */ << 515 #define TEGRA234_CLK_XUSB_SS_DEV << 516 /** @brief xusb_ss_superspeed_clk */ << 517 #define TEGRA234_CLK_XUSB_SS_SUPERSPEED << 518 /** @brief NAFLL clock source for CPU cluster << 519 #define TEGRA234_CLK_NAFLL_CLUSTER0 << 520 #define TEGRA234_CLK_NAFLL_CLUSTER0_CORE << 521 /** @brief NAFLL clock source for CPU cluster << 522 #define TEGRA234_CLK_NAFLL_CLUSTER1 << 523 #define TEGRA234_CLK_NAFLL_CLUSTER1_CORE << 524 /** @brief NAFLL clock source for CPU cluster << 525 #define TEGRA234_CLK_NAFLL_CLUSTER2 << 526 #define TEGRA234_CLK_NAFLL_CLUSTER2_CORE << 527 /** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE d << 528 #define TEGRA234_CLK_CAN1_CORE << 529 /** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE d << 530 #define TEGRA234_CLK_CAN2_CORE << 531 /** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switc << 532 #define TEGRA234_CLK_PLLA1_OUT1 << 533 /** @brief NVHS PLL hardware power sequencer ( << 534 #define TEGRA234_CLK_PLLNVHS_HPS << 535 /** @brief PLL controlled by CLK_RST_CONTROLLE << 536 #define TEGRA234_CLK_PLLREFE_VCOOUT << 537 /** @brief 32K input clock provided by PMIC */ 31 /** @brief 32K input clock provided by PMIC */ 538 #define TEGRA234_CLK_CLK_32K 32 #define TEGRA234_CLK_CLK_32K 289U 539 /** @brief Fixed 48MHz clock divided down from << 540 #define TEGRA234_CLK_UTMIPLL_CLKOUT48 << 541 /** @brief Fixed 480MHz clock divided down fro << 542 #define TEGRA234_CLK_UTMIPLL_CLKOUT480 << 543 /** @brief PLL controlled by CLK_RST_CONTROLLE << 544 #define TEGRA234_CLK_PLLNVCSI << 545 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_ << 546 #define TEGRA234_CLK_PVA0_CPU_AXI << 547 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_ << 548 #define TEGRA234_CLK_PVA0_VPS << 549 /** @brief DLA0_CORE_NAFLL */ << 550 #define TEGRA234_CLK_NAFLL_DLA0_CORE << 551 /** @brief DLA0_FALCON_NAFLL */ << 552 #define TEGRA234_CLK_NAFLL_DLA0_FALCON << 553 /** @brief DLA1_CORE_NAFLL */ << 554 #define TEGRA234_CLK_NAFLL_DLA1_CORE << 555 /** @brief DLA1_FALCON_NAFLL */ << 556 #define TEGRA234_CLK_NAFLL_DLA1_FALCON << 557 /** @brief output of mux controlled by CLK_RST << 558 #define TEGRA234_CLK_AON_UART_FST_MIPI_CAL << 559 /** @brief GPU system clock */ << 560 #define TEGRA234_CLK_GPUSYS << 561 /** @brief output of mux controlled by CLK_RST << 562 #define TEGRA234_CLK_I2C5 << 563 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE sw << 564 #define TEGRA234_CLK_FR_SE << 565 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_ << 566 #define TEGRA234_CLK_BPMP_CPU_NIC << 567 /** @brief output of gate CLK_ENB_BPMP_CPU */ << 568 #define TEGRA234_CLK_BPMP_CPU << 569 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC s << 570 #define TEGRA234_CLK_TSC << 571 /** @brief output of mem pll A sync mux contro << 572 #define TEGRA234_CLK_EMCSA_MPLL << 573 /** @brief output of mem pll B sync mux contro << 574 #define TEGRA234_CLK_EMCSB_MPLL << 575 /** @brief output of mem pll C sync mux contro << 576 #define TEGRA234_CLK_EMCSC_MPLL << 577 /** @brief output of mem pll D sync mux contro << 578 #define TEGRA234_CLK_EMCSD_MPLL << 579 /** @brief PLL controlled by CLK_RST_CONTROLLE << 580 #define TEGRA234_CLK_PLLC << 581 /** @brief PLL controlled by CLK_RST_CONTROLLE << 582 #define TEGRA234_CLK_PLLC2 << 583 /** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK << 584 #define TEGRA234_CLK_TSC_REF << 585 /** @brief Dummy clock to ensure minimum SoC v << 586 #define TEGRA234_CLK_FUSE_BURN << 587 /** @brief GBE PLL */ << 588 #define TEGRA234_CLK_PLLGBE << 589 /** @brief GBE PLL hardware power sequencer */ << 590 #define TEGRA234_CLK_PLLGBE_HPS << 591 /** @brief output of EMC CDB side A fixed (DIV << 592 #define TEGRA234_CLK_EMCSA_EMC << 593 /** @brief output of EMC CDB side B fixed (DIV << 594 #define TEGRA234_CLK_EMCSB_EMC << 595 /** @brief output of EMC CDB side C fixed (DIV << 596 #define TEGRA234_CLK_EMCSC_EMC << 597 /** @brief output of EMC CDB side D fixed (DIV << 598 #define TEGRA234_CLK_EMCSD_EMC << 599 /** @brief PLLE hardware power sequencer (over << 600 #define TEGRA234_CLK_PLLE_HPS << 601 /** @brief CLK_ENB_PLLREFE_OUT gate output */ << 602 #define TEGRA234_CLK_PLLREFE_VCOOUT_GATED << 603 /** @brief TEGRA234_CLK_SOR_SAFE clk source (P << 604 #define TEGRA234_CLK_PLLP_DIV17 << 605 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_T << 606 #define TEGRA234_CLK_SOC_THERM << 607 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENS << 608 #define TEGRA234_CLK_TSENSE << 609 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 << 610 #define TEGRA234_CLK_FR_SEU1 << 611 /** @brief NAFLL clock source for OFA */ << 612 #define TEGRA234_CLK_NAFLL_OFA << 613 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA s << 614 #define TEGRA234_CLK_OFA << 615 /** @brief NAFLL clock source for SEU1 */ << 616 #define TEGRA234_CLK_NAFLL_SEU1 << 617 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 << 618 #define TEGRA234_CLK_SEU1 << 619 /** @brief output of mux controlled by CLK_RST << 620 #define TEGRA234_CLK_SPI4 << 621 /** @brief output of mux controlled by CLK_RST << 622 #define TEGRA234_CLK_SPI5 << 623 /** @brief output of mux controlled by CLK_RST << 624 #define TEGRA234_CLK_DCE_CPU_NIC << 625 /** @brief output of divider CLK_RST_CONTROLLE << 626 #define TEGRA234_CLK_DCE_NIC << 627 /** @brief NAFLL clock source for DCE */ << 628 #define TEGRA234_CLK_NAFLL_DCE << 629 /** @brief Monitored branch of MPHY_L0_RX_ANA << 630 #define TEGRA234_CLK_MPHY_L0_RX_ANA_M << 631 /** @brief Monitored branch of MPHY_L1_RX_ANA << 632 #define TEGRA234_CLK_MPHY_L1_RX_ANA_M << 633 /** @brief ungated version of TX symbol clock << 634 #define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB << 635 /** @brief output of divider CLK_RST_CONTROLLE << 636 #define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV << 637 /** @brief output of gate CLK_ENB_MPHY_L0_TX_2 << 638 #define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB << 639 /** @brief output of SW_MPHY_L0_TX_HS_SYMB div << 640 #define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV << 641 /** @brief output of SW_MPHY_L0_TX_LS_3XBIT di << 642 #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV << 643 /** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_ << 644 #define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV << 645 /** @brief Monitored branch of MPHY_L0_TX_SYMB << 646 #define TEGRA234_CLK_MPHY_L0_TX_SYMB_M << 647 /** @brief output of divider CLK_RST_CONTROLLE << 648 #define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV << 649 /** @brief output of SW_MPHY_L0_RX_HS_SYMB div << 650 #define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV << 651 /** @brief output of SW_MPHY_L0_RX_LS_BIT divi << 652 #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV << 653 /** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_ << 654 #define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV << 655 /** @brief Monitored branch of MPHY_L0_RX_SYMB << 656 #define TEGRA234_CLK_MPHY_L0_RX_SYMB_M << 657 /** @brief Monitored branch of MBGE0 RX input << 658 #define TEGRA234_CLK_MGBE0_RX_INPUT_M << 659 /** @brief Monitored branch of MBGE1 RX input << 660 #define TEGRA234_CLK_MGBE1_RX_INPUT_M << 661 /** @brief Monitored branch of MBGE2 RX input << 662 #define TEGRA234_CLK_MGBE2_RX_INPUT_M << 663 /** @brief Monitored branch of MBGE3 RX input << 664 #define TEGRA234_CLK_MGBE3_RX_INPUT_M << 665 /** @brief Monitored branch of MGBE0 RX PCS mu << 666 #define TEGRA234_CLK_MGBE0_RX_PCS_M << 667 /** @brief Monitored branch of MGBE1 RX PCS mu << 668 #define TEGRA234_CLK_MGBE1_RX_PCS_M << 669 /** @brief Monitored branch of MGBE2 RX PCS mu << 670 #define TEGRA234_CLK_MGBE2_RX_PCS_M << 671 /** @brief Monitored branch of MGBE3 RX PCS mu << 672 #define TEGRA234_CLK_MGBE3_RX_PCS_M << 673 /** @brief output of mux controlled by CLK_RST << 674 #define TEGRA234_CLK_TACH1 << 675 /** @brief GBE_UPHY_MGBES_APP_CLK switch divid << 676 #define TEGRA234_CLK_MGBES_APP << 677 /** @brief Logical clk for setting GBE UPHY PL << 678 #define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF << 679 /** @brief Logical clk for setting GBE UPHY PL << 680 #define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG << 681 /** @brief RX PCS clock recovered from MGBE0 l << 682 #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT << 683 /** @brief RX PCS clock recovered from MGBE1 l << 684 #define TEGRA234_CLK_MGBE1_RX_PCS_INPUT << 685 /** @brief RX PCS clock recovered from MGBE2 l << 686 #define TEGRA234_CLK_MGBE2_RX_PCS_INPUT << 687 /** @brief RX PCS clock recovered from MGBE3 l << 688 #define TEGRA234_CLK_MGBE3_RX_PCS_INPUT << 689 /** @brief output of mux controlled by GBE_UPH << 690 #define TEGRA234_CLK_MGBE0_RX_PCS << 691 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated << 692 #define TEGRA234_CLK_MGBE0_TX << 693 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider g << 694 #define TEGRA234_CLK_MGBE0_TX_PCS << 695 /** @brief GBE_UPHY_MGBE0_MAC_CLK divider outp << 696 #define TEGRA234_CLK_MGBE0_MAC_DIVIDER << 697 /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output << 698 #define TEGRA234_CLK_MGBE0_MAC << 699 /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate outp << 700 #define TEGRA234_CLK_MGBE0_MACSEC << 701 /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate out << 702 #define TEGRA234_CLK_MGBE0_EEE_PCS << 703 /** @brief GBE_UPHY_MGBE0_APP_CLK gate output << 704 #define TEGRA234_CLK_MGBE0_APP << 705 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider << 706 #define TEGRA234_CLK_MGBE0_PTP_REF << 707 /** @brief output of mux controlled by GBE_UPH << 708 #define TEGRA234_CLK_MGBE1_RX_PCS << 709 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated << 710 #define TEGRA234_CLK_MGBE1_TX << 711 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider g << 712 #define TEGRA234_CLK_MGBE1_TX_PCS << 713 /** @brief GBE_UPHY_MGBE1_MAC_CLK divider outp << 714 #define TEGRA234_CLK_MGBE1_MAC_DIVIDER << 715 /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output << 716 #define TEGRA234_CLK_MGBE1_MAC << 717 /** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate outp << 718 #define TEGRA234_CLK_MGBE1_MACSEC << 719 /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate out << 720 #define TEGRA234_CLK_MGBE1_EEE_PCS << 721 /** @brief GBE_UPHY_MGBE1_APP_CLK gate output << 722 #define TEGRA234_CLK_MGBE1_APP << 723 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider << 724 #define TEGRA234_CLK_MGBE1_PTP_REF << 725 /** @brief output of mux controlled by GBE_UPH << 726 #define TEGRA234_CLK_MGBE2_RX_PCS << 727 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated << 728 #define TEGRA234_CLK_MGBE2_TX << 729 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider g << 730 #define TEGRA234_CLK_MGBE2_TX_PCS << 731 /** @brief GBE_UPHY_MGBE2_MAC_CLK divider outp << 732 #define TEGRA234_CLK_MGBE2_MAC_DIVIDER << 733 /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output << 734 #define TEGRA234_CLK_MGBE2_MAC << 735 /** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate outp << 736 #define TEGRA234_CLK_MGBE2_MACSEC << 737 /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate out << 738 #define TEGRA234_CLK_MGBE2_EEE_PCS << 739 /** @brief GBE_UPHY_MGBE2_APP_CLK gate output << 740 #define TEGRA234_CLK_MGBE2_APP << 741 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider << 742 #define TEGRA234_CLK_MGBE2_PTP_REF << 743 /** @brief output of mux controlled by GBE_UPH << 744 #define TEGRA234_CLK_MGBE3_RX_PCS << 745 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated << 746 #define TEGRA234_CLK_MGBE3_TX << 747 /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider g << 748 #define TEGRA234_CLK_MGBE3_TX_PCS << 749 /** @brief GBE_UPHY_MGBE3_MAC_CLK divider outp << 750 #define TEGRA234_CLK_MGBE3_MAC_DIVIDER << 751 /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output << 752 #define TEGRA234_CLK_MGBE3_MAC << 753 /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate outp << 754 #define TEGRA234_CLK_MGBE3_MACSEC << 755 /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate out << 756 #define TEGRA234_CLK_MGBE3_EEE_PCS << 757 /** @brief GBE_UPHY_MGBE3_APP_CLK gate output << 758 #define TEGRA234_CLK_MGBE3_APP << 759 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider << 760 #define TEGRA234_CLK_MGBE3_PTP_REF << 761 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_R << 762 #define TEGRA234_CLK_GBE_RX_BYP_REF << 763 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_P << 764 #define TEGRA234_CLK_GBE_PLL0_MGMT << 765 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_P << 766 #define TEGRA234_CLK_GBE_PLL1_MGMT << 767 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_P << 768 #define TEGRA234_CLK_GBE_PLL2_MGMT << 769 /** @brief output of gate CLK_ENB_EQOS_MACSEC_ << 770 #define TEGRA234_CLK_EQOS_MACSEC_RX << 771 /** @brief output of gate CLK_ENB_EQOS_MACSEC_ << 772 #define TEGRA234_CLK_EQOS_MACSEC_TX << 773 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_ << 774 #define TEGRA234_CLK_EQOS_TX_DIVIDER << 775 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_ << 776 #define TEGRA234_CLK_NVHS_PLL1_MGMT << 777 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHU << 778 #define TEGRA234_CLK_EMCHUB << 779 /** @brief clock recovered from I2S7 input */ << 780 #define TEGRA234_CLK_I2S7_SYNC_INPUT << 781 /** @brief output of mux controlled by CLK_RST << 782 #define TEGRA234_CLK_SYNC_I2S7 << 783 /** @brief output of mux controlled by CLK_RST << 784 #define TEGRA234_CLK_I2S7 << 785 /** @brief Monitored output of I2S7 pad macro << 786 #define TEGRA234_CLK_I2S7_PAD_M << 787 /** @brief clock recovered from I2S8 input */ << 788 #define TEGRA234_CLK_I2S8_SYNC_INPUT << 789 /** @brief output of mux controlled by CLK_RST << 790 #define TEGRA234_CLK_SYNC_I2S8 << 791 /** @brief output of mux controlled by CLK_RST << 792 #define TEGRA234_CLK_I2S8 << 793 /** @brief Monitored output of I2S8 pad macro << 794 #define TEGRA234_CLK_I2S8_PAD_M << 795 /** @brief NAFLL clock source for GPU GPC0 */ << 796 #define TEGRA234_CLK_NAFLL_GPC0 << 797 /** @brief NAFLL clock source for GPU GPC1 */ << 798 #define TEGRA234_CLK_NAFLL_GPC1 << 799 /** @brief NAFLL clock source for GPU SYSCLK * << 800 #define TEGRA234_CLK_NAFLL_GPUSYS << 801 /** @brief NAFLL clock source for CPU cluster << 802 #define TEGRA234_CLK_NAFLL_DSU0 << 803 #define TEGRA234_CLK_NAFLL_CLUSTER0_DSU << 804 /** @brief NAFLL clock source for CPU cluster << 805 #define TEGRA234_CLK_NAFLL_DSU1 << 806 #define TEGRA234_CLK_NAFLL_CLUSTER1_DSU << 807 /** @brief NAFLL clock source for CPU cluster << 808 #define TEGRA234_CLK_NAFLL_DSU2 << 809 #define TEGRA234_CLK_NAFLL_CLUSTER2_DSU << 810 /** @brief output of gate CLK_ENB_SCE_CPU */ << 811 #define TEGRA234_CLK_SCE_CPU << 812 /** @brief output of gate CLK_ENB_RCE_CPU */ << 813 #define TEGRA234_CLK_RCE_CPU << 814 /** @brief output of gate CLK_ENB_DCE_CPU */ << 815 #define TEGRA234_CLK_DCE_CPU << 816 /** @brief DSIPLL VCO output */ << 817 #define TEGRA234_CLK_DSIPLL_VCO << 818 /** @brief DSIPLL SYNC_CLKOUTP/N differential << 819 #define TEGRA234_CLK_DSIPLL_CLKOUTPN << 820 /** @brief DSIPLL SYNC_CLKOUTA output */ << 821 #define TEGRA234_CLK_DSIPLL_CLKOUTA << 822 /** @brief SPPLL0 VCO output */ << 823 #define TEGRA234_CLK_SPPLL0_VCO << 824 /** @brief SPPLL0 SYNC_CLKOUTP/N differential << 825 #define TEGRA234_CLK_SPPLL0_CLKOUTPN << 826 /** @brief SPPLL0 SYNC_CLKOUTA output */ << 827 #define TEGRA234_CLK_SPPLL0_CLKOUTA << 828 /** @brief SPPLL0 SYNC_CLKOUTB output */ << 829 #define TEGRA234_CLK_SPPLL0_CLKOUTB << 830 /** @brief SPPLL0 CLKOUT_DIVBY10 output */ << 831 #define TEGRA234_CLK_SPPLL0_DIV10 << 832 /** @brief SPPLL0 CLKOUT_DIVBY25 output */ << 833 #define TEGRA234_CLK_SPPLL0_DIV25 << 834 /** @brief SPPLL0 CLKOUT_DIVBY27P/N differenti << 835 #define TEGRA234_CLK_SPPLL0_DIV27PN << 836 /** @brief SPPLL1 VCO output */ << 837 #define TEGRA234_CLK_SPPLL1_VCO << 838 /** @brief SPPLL1 SYNC_CLKOUTP/N differential << 839 #define TEGRA234_CLK_SPPLL1_CLKOUTPN << 840 /** @brief SPPLL1 CLKOUT_DIVBY27P/N differenti << 841 #define TEGRA234_CLK_SPPLL1_DIV27PN << 842 /** @brief VPLL0 reference clock */ << 843 #define TEGRA234_CLK_VPLL0_REF << 844 /** @brief VPLL0 */ << 845 #define TEGRA234_CLK_VPLL0 << 846 /** @brief VPLL1 */ << 847 #define TEGRA234_CLK_VPLL1 << 848 /** @brief NVDISPLAY_P0_CLK reference select * << 849 #define TEGRA234_CLK_NVDISPLAY_P0_REF << 850 /** @brief RG0_PCLK */ << 851 #define TEGRA234_CLK_RG0 << 852 /** @brief RG1_PCLK */ << 853 #define TEGRA234_CLK_RG1 << 854 /** @brief DISPPLL output */ << 855 #define TEGRA234_CLK_DISPPLL << 856 /** @brief DISPHUBPLL output */ << 857 #define TEGRA234_CLK_DISPHUBPLL << 858 /** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DI << 859 #define TEGRA234_CLK_DSI_LP << 860 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_ << 861 #define TEGRA234_CLK_AZA_2XBIT << 862 /** @brief aza_2xbitclk / 2 (aza_bitclk) */ << 863 #define TEGRA234_CLK_AZA_BIT << 864 /** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE << 865 #define TEGRA234_CLK_DSI_CORE << 866 /** @brief Output of mux controlled by pkt_wr_ << 867 #define TEGRA234_CLK_DSI_PIXEL << 868 /** @brief Output of mux controlled by disp_2c << 869 #define TEGRA234_CLK_PRE_SOR0 << 870 /** @brief Output of mux controlled by disp_2c << 871 #define TEGRA234_CLK_PRE_SOR1 << 872 /** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG_ << 873 #define TEGRA234_CLK_DP_LINK_REF << 874 /** @brief Link clock input from DP macro bric << 875 #define TEGRA234_CLK_SOR_LINKA_INPUT << 876 /** @brief SOR AFIFO clock outut */ << 877 #define TEGRA234_CLK_SOR_LINKA_AFIFO << 878 /** @brief Monitored branch of linka_afifo_clk << 879 #define TEGRA234_CLK_SOR_LINKA_AFIFO_M << 880 /** @brief Monitored branch of rg0_pclk */ << 881 #define TEGRA234_CLK_RG0_M << 882 /** @brief Monitored branch of rg1_pclk */ << 883 #define TEGRA234_CLK_RG1_M << 884 /** @brief Monitored branch of sor0_clk */ << 885 #define TEGRA234_CLK_SOR0_M << 886 /** @brief Monitored branch of sor1_clk */ << 887 #define TEGRA234_CLK_SOR1_M << 888 /** @brief EMC PLLHUB output */ << 889 #define TEGRA234_CLK_PLLHUB << 890 /** @brief output of fixed (DIV2) MC HUB divid << 891 #define TEGRA234_CLK_MCHUB << 892 /** @brief output of divider controlled by EMC << 893 #define TEGRA234_CLK_EMCSA_MC << 894 /** @brief output of divider controlled by EMC << 895 #define TEGRA234_CLK_EMCSB_MC << 896 /** @brief output of divider controlled by EMC << 897 #define TEGRA234_CLK_EMCSC_MC << 898 /** @brief output of divider controlled by EMC << 899 #define TEGRA234_CLK_EMCSD_MC << 900 << 901 /** @} */ << 902 33 903 #endif 34 #endif 904 35

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h

Diff markup

Differences between /scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h (Version linux-5.17.15)

TOMOYO Linux Cross Reference Linux/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h

Diff markup

Differences between /scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h (Version linux-5.17.15)

TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h