Linux/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION 2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 3 3 4 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 4 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 5 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 5 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 6 6 7 /** 7 /** 8 * @file 8 * @file 9 * @defgroup bpmp_clock_ids Clock ID's 9 * @defgroup bpmp_clock_ids Clock ID's 10 * @{ 10 * @{ 11 */ 11 */ 12 /** @brief output of mux controlled by CLK_RST << 13 #define TEGRA234_CLK_ACTMON << 14 /** @brief output of gate CLK_ENB_ADSP */ << 15 #define TEGRA234_CLK_ADSP << 16 /** @brief output of gate CLK_ENB_ADSPNEON */ << 17 #define TEGRA234_CLK_ADSPNEON << 18 /** output of mux controlled by CLK_RST_CONTRO 12 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 19 #define TEGRA234_CLK_AHUB 13 #define TEGRA234_CLK_AHUB 4U 20 /** @brief output of gate CLK_ENB_APB2APE */ 14 /** @brief output of gate CLK_ENB_APB2APE */ 21 #define TEGRA234_CLK_APB2APE 15 #define TEGRA234_CLK_APB2APE 5U 22 /** @brief output of mux controlled by CLK_RST 16 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 23 #define TEGRA234_CLK_APE 17 #define TEGRA234_CLK_APE 6U 24 /** @brief output of mux controlled by CLK_RST 18 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 25 #define TEGRA234_CLK_AUD_MCLK 19 #define TEGRA234_CLK_AUD_MCLK 7U 26 /** @brief output of mux controlled by CLK_RST << 27 #define TEGRA234_CLK_AXI_CBB << 28 /** @brief output of mux controlled by CLK_RST << 29 #define TEGRA234_CLK_CAN1 << 30 /** @brief output of gate CLK_ENB_CAN1_HOST */ << 31 #define TEGRA234_CLK_CAN1_HOST << 32 /** @brief output of mux controlled by CLK_RST << 33 #define TEGRA234_CLK_CAN2 << 34 /** @brief output of gate CLK_ENB_CAN2_HOST */ << 35 #define TEGRA234_CLK_CAN2_HOST << 36 /** @brief output of divider CLK_RST_CONTROLLE << 37 #define TEGRA234_CLK_CLK_M << 38 /** @brief output of mux controlled by CLK_RST 20 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 39 #define TEGRA234_CLK_DMIC1 21 #define TEGRA234_CLK_DMIC1 15U 40 /** @brief output of mux controlled by CLK_RST 22 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 41 #define TEGRA234_CLK_DMIC2 23 #define TEGRA234_CLK_DMIC2 16U 42 /** @brief output of mux controlled by CLK_RST 24 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 43 #define TEGRA234_CLK_DMIC3 25 #define TEGRA234_CLK_DMIC3 17U 44 /** @brief output of mux controlled by CLK_RST 26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 45 #define TEGRA234_CLK_DMIC4 27 #define TEGRA234_CLK_DMIC4 18U 46 /** @brief output of gate CLK_ENB_DPAUX */ << 47 #define TEGRA234_CLK_DPAUX << 48 /** @brief output of mux controlled by CLK_RST << 49 #define TEGRA234_CLK_NVJPG1 << 50 /** << 51 * @brief output of mux controlled by CLK_RST_ << 52 * divided by the divider controlled by ACLK_C << 53 * CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER << 54 */ << 55 #define TEGRA234_CLK_ACLK << 56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_E << 57 #define TEGRA234_CLK_MSS_ENCRYPT << 58 /** @brief clock recovered from EAVB input */ << 59 #define TEGRA234_CLK_EQOS_RX_INPUT << 60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_A << 61 #define TEGRA234_CLK_AON_APB << 62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE div << 63 #define TEGRA234_CLK_AON_NIC << 64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_C << 65 #define TEGRA234_CLK_AON_CPU_NIC << 66 /** @brief PLL controlled by CLK_RST_CONTROLLE << 67 #define TEGRA234_CLK_PLLA1 << 68 /** @brief output of mux controlled by CLK_RST 28 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 69 #define TEGRA234_CLK_DSPK1 29 #define TEGRA234_CLK_DSPK1 29U 70 /** @brief output of mux controlled by CLK_RST 30 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 71 #define TEGRA234_CLK_DSPK2 31 #define TEGRA234_CLK_DSPK2 30U 72 /** 32 /** 73 * @brief controls the EMC clock frequency. 33 * @brief controls the EMC clock frequency. 74 * @details Doing a clk_set_rate on this clock 34 * @details Doing a clk_set_rate on this clock will select the 75 * appropriate clock source, program the sourc 35 * appropriate clock source, program the source rate and execute a 76 * specific sequence to switch to the new cloc 36 * specific sequence to switch to the new clock source for both memory 77 * controllers. This can be used to control th 37 * controllers. This can be used to control the balance between memory 78 * throughput and memory controller power. 38 * throughput and memory controller power. 79 */ 39 */ 80 #define TEGRA234_CLK_EMC 40 #define TEGRA234_CLK_EMC 31U 81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_ !! 41 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 82 #define TEGRA234_CLK_EQOS_AXI !! 42 #define TEGRA234_CLK_HOST1X 46U 83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_ << 84 #define TEGRA234_CLK_EQOS_PTP_REF << 85 /** @brief output of gate CLK_ENB_EQOS_RX */ << 86 #define TEGRA234_CLK_EQOS_RX << 87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_ << 88 #define TEGRA234_CLK_EQOS_TX << 89 /** @brief output of mux controlled by CLK_RST << 90 #define TEGRA234_CLK_EXTPERIPH1 << 91 /** @brief output of mux controlled by CLK_RST << 92 #define TEGRA234_CLK_EXTPERIPH2 << 93 /** @brief output of mux controlled by CLK_RST << 94 #define TEGRA234_CLK_EXTPERIPH3 << 95 /** @brief output of mux controlled by CLK_RST << 96 #define TEGRA234_CLK_EXTPERIPH4 << 97 /** @brief output of gate CLK_ENB_FUSE */ 43 /** @brief output of gate CLK_ENB_FUSE */ 98 #define TEGRA234_CLK_FUSE 44 #define TEGRA234_CLK_FUSE 40U 99 /** @brief output of GPU GPC0 clkGen (in 1x mo << 100 #define TEGRA234_CLK_GPC0CLK << 101 /** @brief TODO */ << 102 #define TEGRA234_CLK_GPU_PWR << 103 /** output of mux controlled by CLK_RST_CONTRO << 104 /** @brief output of mux controlled by CLK_RST << 105 #define TEGRA234_CLK_HOST1X << 106 /** @brief xusb_hs_hsicp_clk */ << 107 #define TEGRA234_CLK_XUSB_HS_HSICP << 108 /** @brief output of mux controlled by CLK_RST 45 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ 109 #define TEGRA234_CLK_I2C1 46 #define TEGRA234_CLK_I2C1 48U 110 /** @brief output of mux controlled by CLK_RST 47 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 111 #define TEGRA234_CLK_I2C2 48 #define TEGRA234_CLK_I2C2 49U 112 /** @brief output of mux controlled by CLK_RST 49 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 113 #define TEGRA234_CLK_I2C3 50 #define TEGRA234_CLK_I2C3 50U 114 /** output of mux controlled by CLK_RST_CONTRO 51 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 115 #define TEGRA234_CLK_I2C4 52 #define TEGRA234_CLK_I2C4 51U 116 /** @brief output of mux controlled by CLK_RST 53 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 117 #define TEGRA234_CLK_I2C6 54 #define TEGRA234_CLK_I2C6 52U 118 /** @brief output of mux controlled by CLK_RST 55 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 119 #define TEGRA234_CLK_I2C7 56 #define TEGRA234_CLK_I2C7 53U 120 /** @brief output of mux controlled by CLK_RST 57 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 121 #define TEGRA234_CLK_I2C8 58 #define TEGRA234_CLK_I2C8 54U 122 /** @brief output of mux controlled by CLK_RST 59 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 123 #define TEGRA234_CLK_I2C9 60 #define TEGRA234_CLK_I2C9 55U 124 /** output of mux controlled by CLK_RST_CONTRO 61 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 125 #define TEGRA234_CLK_I2S1 62 #define TEGRA234_CLK_I2S1 56U 126 /** @brief clock recovered from I2S1 input */ 63 /** @brief clock recovered from I2S1 input */ 127 #define TEGRA234_CLK_I2S1_SYNC_INPUT 64 #define TEGRA234_CLK_I2S1_SYNC_INPUT 57U 128 /** @brief output of mux controlled by CLK_RST 65 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 129 #define TEGRA234_CLK_I2S2 66 #define TEGRA234_CLK_I2S2 58U 130 /** @brief clock recovered from I2S2 input */ 67 /** @brief clock recovered from I2S2 input */ 131 #define TEGRA234_CLK_I2S2_SYNC_INPUT 68 #define TEGRA234_CLK_I2S2_SYNC_INPUT 59U 132 /** @brief output of mux controlled by CLK_RST 69 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 133 #define TEGRA234_CLK_I2S3 70 #define TEGRA234_CLK_I2S3 60U 134 /** @brief clock recovered from I2S3 input */ 71 /** @brief clock recovered from I2S3 input */ 135 #define TEGRA234_CLK_I2S3_SYNC_INPUT 72 #define TEGRA234_CLK_I2S3_SYNC_INPUT 61U 136 /** output of mux controlled by CLK_RST_CONTRO 73 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 137 #define TEGRA234_CLK_I2S4 74 #define TEGRA234_CLK_I2S4 62U 138 /** @brief clock recovered from I2S4 input */ 75 /** @brief clock recovered from I2S4 input */ 139 #define TEGRA234_CLK_I2S4_SYNC_INPUT 76 #define TEGRA234_CLK_I2S4_SYNC_INPUT 63U 140 /** output of mux controlled by CLK_RST_CONTRO 77 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 141 #define TEGRA234_CLK_I2S5 78 #define TEGRA234_CLK_I2S5 64U 142 /** @brief clock recovered from I2S5 input */ 79 /** @brief clock recovered from I2S5 input */ 143 #define TEGRA234_CLK_I2S5_SYNC_INPUT 80 #define TEGRA234_CLK_I2S5_SYNC_INPUT 65U 144 /** @brief output of mux controlled by CLK_RST 81 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ 145 #define TEGRA234_CLK_I2S6 82 #define TEGRA234_CLK_I2S6 66U 146 /** @brief clock recovered from I2S6 input */ 83 /** @brief clock recovered from I2S6 input */ 147 #define TEGRA234_CLK_I2S6_SYNC_INPUT 84 #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U 148 /** @brief output of mux controlled by CLK_RST << 149 #define TEGRA234_CLK_ISP << 150 /** @brief Monitored branch of EQOS_RX clock * << 151 #define TEGRA234_CLK_EQOS_RX_M << 152 /** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWIT << 153 #define TEGRA234_CLK_MAUD << 154 /** @brief output of gate CLK_ENB_MIPI_CAL */ << 155 #define TEGRA234_CLK_MIPI_CAL << 156 /** @brief output of the divider CLK_RST_CONTR << 157 #define TEGRA234_CLK_MPHY_CORE_PLL_FIXED << 158 /** @brief output of gate CLK_ENB_MPHY_L0_RX_A << 159 #define TEGRA234_CLK_MPHY_L0_RX_ANA << 160 /** @brief output of gate CLK_ENB_MPHY_L0_RX_L << 161 #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT << 162 /** @brief output of gate CLK_ENB_MPHY_L0_RX_S << 163 #define TEGRA234_CLK_MPHY_L0_RX_SYMB << 164 /** @brief output of gate CLK_ENB_MPHY_L0_TX_L << 165 #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT << 166 /** @brief output of gate CLK_ENB_MPHY_L0_TX_S << 167 #define TEGRA234_CLK_MPHY_L0_TX_SYMB << 168 /** @brief output of gate CLK_ENB_MPHY_L1_RX_A << 169 #define TEGRA234_CLK_MPHY_L1_RX_ANA << 170 /** @brief output of the divider CLK_RST_CONTR << 171 #define TEGRA234_CLK_MPHY_TX_1MHZ_REF << 172 /** @brief output of mux controlled by CLK_RST << 173 #define TEGRA234_CLK_NVCSI << 174 /** @brief output of mux controlled by CLK_RST << 175 #define TEGRA234_CLK_NVCSILP << 176 /** @brief output of mux controlled by CLK_RST << 177 #define TEGRA234_CLK_NVDEC << 178 /** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITC << 179 #define TEGRA234_CLK_HUB << 180 /** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_D << 181 #define TEGRA234_CLK_DISP << 182 /** @brief RG_CLK_CTRL__0_DIV divider output ( << 183 #define TEGRA234_CLK_NVDISPLAY_P0 << 184 /** @brief RG_CLK_CTRL__1_DIV divider output ( << 185 #define TEGRA234_CLK_NVDISPLAY_P1 << 186 /** @brief DSC_CLK (DISPCLK ÷ 3) */ << 187 #define TEGRA234_CLK_DSC << 188 /** @brief output of mux controlled by CLK_RST << 189 #define TEGRA234_CLK_NVENC << 190 /** @brief output of mux controlled by CLK_RST << 191 #define TEGRA234_CLK_NVJPG << 192 /** @brief input from Tegra's XTAL_IN */ << 193 #define TEGRA234_CLK_OSC << 194 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_T << 195 #define TEGRA234_CLK_AON_TOUCH << 196 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_ 85 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 197 #define TEGRA234_CLK_PLLA 86 #define TEGRA234_CLK_PLLA 93U 198 /** @brief PLL controlled by CLK_RST_CONTROLLE << 199 #define TEGRA234_CLK_PLLAON << 200 /** Fixed 100MHz PLL for PCIe, SATA and supers << 201 #define TEGRA234_CLK_PLLE << 202 /** @brief PLLP vco output */ << 203 #define TEGRA234_CLK_PLLP << 204 /** @brief PLLP clk output */ 87 /** @brief PLLP clk output */ 205 #define TEGRA234_CLK_PLLP_OUT0 88 #define TEGRA234_CLK_PLLP_OUT0 102U 206 /** Fixed frequency 960MHz PLL for USB and EAV << 207 #define TEGRA234_CLK_UTMIP_PLL << 208 /** @brief output of the divider CLK_RST_CONTR 89 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 209 #define TEGRA234_CLK_PLLA_OUT0 90 #define TEGRA234_CLK_PLLA_OUT0 104U 210 /** @brief output of mux controlled by CLK_RST 91 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 211 #define TEGRA234_CLK_PWM1 92 #define TEGRA234_CLK_PWM1 105U 212 /** @brief output of mux controlled by CLK_RST 93 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 213 #define TEGRA234_CLK_PWM2 94 #define TEGRA234_CLK_PWM2 106U 214 /** @brief output of mux controlled by CLK_RST 95 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 215 #define TEGRA234_CLK_PWM3 96 #define TEGRA234_CLK_PWM3 107U 216 /** @brief output of mux controlled by CLK_RST 97 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 217 #define TEGRA234_CLK_PWM4 98 #define TEGRA234_CLK_PWM4 108U 218 /** @brief output of mux controlled by CLK_RST 99 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 219 #define TEGRA234_CLK_PWM5 100 #define TEGRA234_CLK_PWM5 109U 220 /** @brief output of mux controlled by CLK_RST 101 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 221 #define TEGRA234_CLK_PWM6 102 #define TEGRA234_CLK_PWM6 110U 222 /** @brief output of mux controlled by CLK_RST 103 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 223 #define TEGRA234_CLK_PWM7 104 #define TEGRA234_CLK_PWM7 111U 224 /** @brief output of mux controlled by CLK_RST 105 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 225 #define TEGRA234_CLK_PWM8 106 #define TEGRA234_CLK_PWM8 112U 226 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_C << 227 #define TEGRA234_CLK_RCE_CPU_NIC << 228 /** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE div << 229 #define TEGRA234_CLK_RCE_NIC << 230 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I << 231 #define TEGRA234_CLK_AON_I2C_SLOW << 232 /** @brief output of mux controlled by CLK_RST << 233 #define TEGRA234_CLK_SCE_CPU_NIC << 234 /** @brief output of divider CLK_RST_CONTROLLE << 235 #define TEGRA234_CLK_SCE_NIC << 236 /** @brief output of mux controlled by CLK_RST << 237 #define TEGRA234_CLK_SDMMC1 << 238 /** @brief Logical clk for setting the UPHY PL << 239 #define TEGRA234_CLK_UPHY_PLL3 << 240 /** @brief output of mux controlled by CLK_RST 107 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 241 #define TEGRA234_CLK_SDMMC4 108 #define TEGRA234_CLK_SDMMC4 123U 242 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE sw << 243 #define TEGRA234_CLK_SE << 244 /** @brief VPLL select for sor0_ref clk driven << 245 #define TEGRA234_CLK_SOR0_PLL_REF << 246 /** @brief Output of mux controlled by disp_2c << 247 #define TEGRA234_CLK_SOR0_REF << 248 /** @brief VPLL select for sor1_ref clk driven << 249 #define TEGRA234_CLK_SOR1_PLL_REF << 250 /** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider << 251 #define TEGRA234_CLK_PRE_SOR0_REF << 252 /** @brief Output of mux controlled by disp_2c << 253 #define TEGRA234_CLK_SOR1_REF << 254 /** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider << 255 #define TEGRA234_CLK_PRE_SOR1_REF << 256 /** @brief output of gate CLK_ENB_SOR_SAFE */ << 257 #define TEGRA234_CLK_SOR_SAFE << 258 /** @brief SOR_CLK_CTRL__0_DIV divider output << 259 #define TEGRA234_CLK_SOR0_DIV << 260 /** @brief output of mux controlled by CLK_RST << 261 #define TEGRA234_CLK_DMIC5 << 262 /** @brief output of mux controlled by CLK_RST << 263 #define TEGRA234_CLK_SPI1 << 264 /** @brief output of mux controlled by CLK_RST << 265 #define TEGRA234_CLK_SPI2 << 266 /** @brief output of mux controlled by CLK_RST << 267 #define TEGRA234_CLK_SPI3 << 268 /** @brief output of mux controlled by CLK_RST << 269 #define TEGRA234_CLK_I2C_SLOW << 270 /** @brief output of mux controlled by CLK_RST 109 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 271 #define TEGRA234_CLK_SYNC_DMIC1 110 #define TEGRA234_CLK_SYNC_DMIC1 139U 272 /** @brief output of mux controlled by CLK_RST 111 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 273 #define TEGRA234_CLK_SYNC_DMIC2 112 #define TEGRA234_CLK_SYNC_DMIC2 140U 274 /** @brief output of mux controlled by CLK_RST 113 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 275 #define TEGRA234_CLK_SYNC_DMIC3 114 #define TEGRA234_CLK_SYNC_DMIC3 141U 276 /** @brief output of mux controlled by CLK_RST 115 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 277 #define TEGRA234_CLK_SYNC_DMIC4 116 #define TEGRA234_CLK_SYNC_DMIC4 142U 278 /** @brief output of mux controlled by CLK_RST 117 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 279 #define TEGRA234_CLK_SYNC_DSPK1 118 #define TEGRA234_CLK_SYNC_DSPK1 143U 280 /** @brief output of mux controlled by CLK_RST 119 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 281 #define TEGRA234_CLK_SYNC_DSPK2 120 #define TEGRA234_CLK_SYNC_DSPK2 144U 282 /** @brief output of mux controlled by CLK_RST 121 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 283 #define TEGRA234_CLK_SYNC_I2S1 122 #define TEGRA234_CLK_SYNC_I2S1 145U 284 /** @brief output of mux controlled by CLK_RST 123 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 285 #define TEGRA234_CLK_SYNC_I2S2 124 #define TEGRA234_CLK_SYNC_I2S2 146U 286 /** @brief output of mux controlled by CLK_RST 125 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 287 #define TEGRA234_CLK_SYNC_I2S3 126 #define TEGRA234_CLK_SYNC_I2S3 147U 288 /** @brief output of mux controlled by CLK_RST 127 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 289 #define TEGRA234_CLK_SYNC_I2S4 128 #define TEGRA234_CLK_SYNC_I2S4 148U 290 /** @brief output of mux controlled by CLK_RST 129 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 291 #define TEGRA234_CLK_SYNC_I2S5 130 #define TEGRA234_CLK_SYNC_I2S5 149U 292 /** @brief output of mux controlled by CLK_RST 131 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 293 #define TEGRA234_CLK_SYNC_I2S6 132 #define TEGRA234_CLK_SYNC_I2S6 150U 294 /** @brief controls MPHY_FORCE_LS_MODE upon en << 295 #define TEGRA234_CLK_MPHY_FORCE_LS_MODE << 296 /** @brief output of mux controlled by CLK_RST << 297 #define TEGRA234_CLK_TACH0 << 298 /** output of mux controlled by CLK_RST_CONTRO << 299 #define TEGRA234_CLK_TSEC << 300 /** output of mux controlled by CLK_RST_CONTRO << 301 #define TEGRA234_CLK_TSEC_PKA << 302 /** @brief output of mux controlled by CLK_RST 133 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 303 #define TEGRA234_CLK_UARTA 134 #define TEGRA234_CLK_UARTA 155U 304 /** @brief output of mux controlled by CLK_RST << 305 #define TEGRA234_CLK_UARTB << 306 /** @brief output of mux controlled by CLK_RST << 307 #define TEGRA234_CLK_UARTC << 308 /** @brief output of mux controlled by CLK_RST << 309 #define TEGRA234_CLK_UARTD << 310 /** @brief output of mux controlled by CLK_RST << 311 #define TEGRA234_CLK_UARTE << 312 /** @brief output of mux controlled by CLK_RST << 313 #define TEGRA234_CLK_UARTF << 314 /** @brief output of gate CLK_ENB_PEX1_CORE_6 135 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ 315 #define TEGRA234_CLK_PEX1_C6_CORE 136 #define TEGRA234_CLK_PEX1_C6_CORE 161U 316 /** @brief output of mux controlled by CLK_RST << 317 #define TEGRA234_CLK_UART_FST_MIPI_CAL << 318 /** @brief output of mux controlled by CLK_RST << 319 #define TEGRA234_CLK_UFSDEV_REF << 320 /** @brief output of mux controlled by CLK_RST << 321 #define TEGRA234_CLK_UFSHC << 322 /** @brief output of gate CLK_ENB_USB2_TRK */ << 323 #define TEGRA234_CLK_USB2_TRK << 324 /** @brief output of mux controlled by CLK_RST << 325 #define TEGRA234_CLK_VI << 326 /** @brief output of mux controlled by CLK_RST 137 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 327 #define TEGRA234_CLK_VIC !! 138 #define TEGRA234_CLK_VIC 167U 328 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE << 329 #define TEGRA234_CLK_CSITE << 330 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST s << 331 #define TEGRA234_CLK_IST << 332 /** @brief output of mux controlled by CLK_RST << 333 #define TEGRA234_CLK_JTAG_INTFC_PRE_CG << 334 /** @brief output of gate CLK_ENB_PEX2_CORE_7 139 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ 335 #define TEGRA234_CLK_PEX2_C7_CORE 140 #define TEGRA234_CLK_PEX2_C7_CORE 171U 336 /** @brief output of gate CLK_ENB_PEX2_CORE_8 141 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ 337 #define TEGRA234_CLK_PEX2_C8_CORE 142 #define TEGRA234_CLK_PEX2_C8_CORE 172U 338 /** @brief output of gate CLK_ENB_PEX2_CORE_9 143 /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ 339 #define TEGRA234_CLK_PEX2_C9_CORE 144 #define TEGRA234_CLK_PEX2_C9_CORE 173U 340 /** @brief dla0_falcon_clk */ << 341 #define TEGRA234_CLK_DLA0_FALCON << 342 /** @brief dla0_core_clk */ << 343 #define TEGRA234_CLK_DLA0_CORE << 344 /** @brief dla1_falcon_clk */ << 345 #define TEGRA234_CLK_DLA1_FALCON << 346 /** @brief dla1_core_clk */ << 347 #define TEGRA234_CLK_DLA1_CORE << 348 /** @brief Output of mux controlled by disp_2c << 349 #define TEGRA234_CLK_SOR0 << 350 /** @brief Output of mux controlled by disp_2c << 351 #define TEGRA234_CLK_SOR1 << 352 /** @brief DP macro feedback clock (same as LI << 353 #define TEGRA234_CLK_SOR_PAD_INPUT << 354 /** @brief Output of mux controlled by disp_2c << 355 #define TEGRA234_CLK_PRE_SF0 << 356 /** @brief Output of mux controlled by disp_2c << 357 #define TEGRA234_CLK_SF0 << 358 /** @brief Output of mux controlled by disp_2c << 359 #define TEGRA234_CLK_SF1 << 360 /** @brief CLKOUT_AB output from DSI BRICK A ( << 361 #define TEGRA234_CLK_DSI_PAD_INPUT << 362 /** @brief output of gate CLK_ENB_PEX2_CORE_10 145 /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ 363 #define TEGRA234_CLK_PEX2_C10_CORE 146 #define TEGRA234_CLK_PEX2_C10_CORE 187U 364 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI !! 147 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ 365 #define TEGRA234_CLK_UARTI << 366 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ << 367 #define TEGRA234_CLK_UARTJ << 368 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH << 369 #define TEGRA234_CLK_UARTH << 370 /** @brief ungated version of fuse clk */ << 371 #define TEGRA234_CLK_FUSE_SERIAL << 372 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 << 373 #define TEGRA234_CLK_QSPI0_2X_PM 148 #define TEGRA234_CLK_QSPI0_2X_PM 192U 374 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 !! 149 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ 375 #define TEGRA234_CLK_QSPI1_2X_PM 150 #define TEGRA234_CLK_QSPI1_2X_PM 193U 376 /** @brief output of the divider QSPI_CLK_DIV2 !! 151 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ 377 #define TEGRA234_CLK_QSPI0_PM 152 #define TEGRA234_CLK_QSPI0_PM 194U 378 /** @brief output of the divider QSPI_CLK_DIV2 !! 153 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ 379 #define TEGRA234_CLK_QSPI1_PM 154 #define TEGRA234_CLK_QSPI1_PM 195U 380 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CO << 381 #define TEGRA234_CLK_VI_CONST << 382 /** @brief NAFLL clock source for BPMP */ << 383 #define TEGRA234_CLK_NAFLL_BPMP << 384 /** @brief NAFLL clock source for SCE */ << 385 #define TEGRA234_CLK_NAFLL_SCE << 386 /** @brief NAFLL clock source for NVDEC */ << 387 #define TEGRA234_CLK_NAFLL_NVDEC << 388 /** @brief NAFLL clock source for NVJPG */ << 389 #define TEGRA234_CLK_NAFLL_NVJPG << 390 /** @brief NAFLL clock source for TSEC */ << 391 #define TEGRA234_CLK_NAFLL_TSEC << 392 /** @brief NAFLL clock source for VI */ << 393 #define TEGRA234_CLK_NAFLL_VI << 394 /** @brief NAFLL clock source for SE */ << 395 #define TEGRA234_CLK_NAFLL_SE << 396 /** @brief NAFLL clock source for NVENC */ << 397 #define TEGRA234_CLK_NAFLL_NVENC << 398 /** @brief NAFLL clock source for ISP */ << 399 #define TEGRA234_CLK_NAFLL_ISP << 400 /** @brief NAFLL clock source for VIC */ << 401 #define TEGRA234_CLK_NAFLL_VIC << 402 /** @brief NAFLL clock source for AXICBB */ << 403 #define TEGRA234_CLK_NAFLL_AXICBB << 404 /** @brief NAFLL clock source for NVJPG1 */ << 405 #define TEGRA234_CLK_NAFLL_NVJPG1 << 406 /** @brief NAFLL clock source for PVA core */ << 407 #define TEGRA234_CLK_NAFLL_PVA0_CORE << 408 /** @brief NAFLL clock source for PVA VPS */ << 409 #define TEGRA234_CLK_NAFLL_PVA0_VPS << 410 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAP << 411 #define TEGRA234_CLK_DBGAPB << 412 /** @brief NAFLL clock source for RCE */ << 413 #define TEGRA234_CLK_NAFLL_RCE << 414 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA sw << 415 #define TEGRA234_CLK_LA << 416 /** @brief output of the divider CLK_RST_CONTR << 417 #define TEGRA234_CLK_PLLP_OUT_JTAG << 418 /** @brief AXI_CBB branch sharing gate control << 419 #define TEGRA234_CLK_SDMMC4_AXICIF << 420 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC 155 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 421 #define TEGRA234_CLK_SDMMC_LEGACY_TM 156 #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 422 /** @brief output of gate CLK_ENB_PEX0_CORE_0 157 /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ 423 #define TEGRA234_CLK_PEX0_C0_CORE 158 #define TEGRA234_CLK_PEX0_C0_CORE 220U 424 /** @brief output of gate CLK_ENB_PEX0_CORE_1 159 /** @brief output of gate CLK_ENB_PEX0_CORE_1 */ 425 #define TEGRA234_CLK_PEX0_C1_CORE 160 #define TEGRA234_CLK_PEX0_C1_CORE 221U 426 /** @brief output of gate CLK_ENB_PEX0_CORE_2 161 /** @brief output of gate CLK_ENB_PEX0_CORE_2 */ 427 #define TEGRA234_CLK_PEX0_C2_CORE 162 #define TEGRA234_CLK_PEX0_C2_CORE 222U 428 /** @brief output of gate CLK_ENB_PEX0_CORE_3 163 /** @brief output of gate CLK_ENB_PEX0_CORE_3 */ 429 #define TEGRA234_CLK_PEX0_C3_CORE 164 #define TEGRA234_CLK_PEX0_C3_CORE 223U 430 /** @brief output of gate CLK_ENB_PEX0_CORE_4 165 /** @brief output of gate CLK_ENB_PEX0_CORE_4 */ 431 #define TEGRA234_CLK_PEX0_C4_CORE 166 #define TEGRA234_CLK_PEX0_C4_CORE 224U 432 /** @brief output of gate CLK_ENB_PEX1_CORE_5 167 /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ 433 #define TEGRA234_CLK_PEX1_C5_CORE 168 #define TEGRA234_CLK_PEX1_C5_CORE 225U 434 /** @brief Monitored branch of PEX0_C0_CORE cl << 435 #define TEGRA234_CLK_PEX0_C0_CORE_M << 436 /** @brief Monitored branch of PEX0_C1_CORE cl << 437 #define TEGRA234_CLK_PEX0_C1_CORE_M << 438 /** @brief Monitored branch of PEX0_C2_CORE cl << 439 #define TEGRA234_CLK_PEX0_C2_CORE_M << 440 /** @brief Monitored branch of PEX0_C3_CORE cl << 441 #define TEGRA234_CLK_PEX0_C3_CORE_M << 442 /** @brief Monitored branch of PEX0_C4_CORE cl << 443 #define TEGRA234_CLK_PEX0_C4_CORE_M << 444 /** @brief Monitored branch of PEX1_C5_CORE cl << 445 #define TEGRA234_CLK_PEX1_C5_CORE_M << 446 /** @brief Monitored branch of PEX1_C6_CORE cl << 447 #define TEGRA234_CLK_PEX1_C6_CORE_M << 448 /** @brief output of GPU GPC1 clkGen (in 1x mo << 449 #define TEGRA234_CLK_GPC1CLK << 450 /** @brief PLL controlled by CLK_RST_CONTROLLE 169 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 451 #define TEGRA234_CLK_PLLC4 170 #define TEGRA234_CLK_PLLC4 237U 452 /** @brief PLLC4 VCO followed by DIV3 path */ << 453 #define TEGRA234_CLK_PLLC4_OUT1 << 454 /** @brief PLLC4 VCO followed by DIV5 path */ << 455 #define TEGRA234_CLK_PLLC4_OUT2 << 456 /** @brief output of the mux controlled by PLL << 457 #define TEGRA234_CLK_PLLC4_MUXED << 458 /** @brief PLLC4 VCO followed by DIV2 path */ << 459 #define TEGRA234_CLK_PLLC4_VCO_DIV2 << 460 /** @brief PLL controlled by CLK_RST_CONTROLLE << 461 #define TEGRA234_CLK_PLLNVHS << 462 /** @brief Monitored branch of PEX2_C7_CORE cl << 463 #define TEGRA234_CLK_PEX2_C7_CORE_M << 464 /** @brief Monitored branch of PEX2_C8_CORE cl << 465 #define TEGRA234_CLK_PEX2_C8_CORE_M << 466 /** @brief Monitored branch of PEX2_C9_CORE cl << 467 #define TEGRA234_CLK_PEX2_C9_CORE_M << 468 /** @brief Monitored branch of PEX2_C10_CORE c << 469 #define TEGRA234_CLK_PEX2_C10_CORE_M << 470 /** @brief RX clock recovered from MGBE0 lane 171 /** @brief RX clock recovered from MGBE0 lane input */ 471 #define TEGRA234_CLK_MGBE0_RX_INPUT 172 #define TEGRA234_CLK_MGBE0_RX_INPUT 248U 472 /** @brief RX clock recovered from MGBE1 lane 173 /** @brief RX clock recovered from MGBE1 lane input */ 473 #define TEGRA234_CLK_MGBE1_RX_INPUT 174 #define TEGRA234_CLK_MGBE1_RX_INPUT 249U 474 /** @brief RX clock recovered from MGBE2 lane 175 /** @brief RX clock recovered from MGBE2 lane input */ 475 #define TEGRA234_CLK_MGBE2_RX_INPUT 176 #define TEGRA234_CLK_MGBE2_RX_INPUT 250U 476 /** @brief RX clock recovered from MGBE3 lane 177 /** @brief RX clock recovered from MGBE3 lane input */ 477 #define TEGRA234_CLK_MGBE3_RX_INPUT 178 #define TEGRA234_CLK_MGBE3_RX_INPUT 251U 478 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_S << 479 #define TEGRA234_CLK_PEX_SATA_USB_RX_BYP << 480 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_U << 481 #define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT << 482 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_U << 483 #define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT << 484 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_U << 485 #define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT << 486 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_U << 487 #define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT << 488 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_ << 489 #define TEGRA234_CLK_NVHS_RX_BYP_REF << 490 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_ << 491 #define TEGRA234_CLK_NVHS_PLL0_MGMT << 492 /** @brief xusb_core_dev_clk */ << 493 #define TEGRA234_CLK_XUSB_CORE_DEV << 494 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_ << 495 #define TEGRA234_CLK_XUSB_CORE_MUX << 496 /** @brief xusb_core_host_clk */ << 497 #define TEGRA234_CLK_XUSB_CORE_HOST << 498 /** @brief xusb_core_superspeed_clk */ << 499 #define TEGRA234_CLK_XUSB_CORE_SS << 500 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_ << 501 #define TEGRA234_CLK_XUSB_FALCON << 502 /** @brief xusb_falcon_host_clk */ << 503 #define TEGRA234_CLK_XUSB_FALCON_HOST << 504 /** @brief xusb_falcon_superspeed_clk */ << 505 #define TEGRA234_CLK_XUSB_FALCON_SS << 506 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_ << 507 #define TEGRA234_CLK_XUSB_FS << 508 /** @brief xusb_fs_host_clk */ << 509 #define TEGRA234_CLK_XUSB_FS_HOST << 510 /** @brief xusb_fs_dev_clk */ << 511 #define TEGRA234_CLK_XUSB_FS_DEV << 512 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_ << 513 #define TEGRA234_CLK_XUSB_SS << 514 /** @brief xusb_ss_dev_clk */ << 515 #define TEGRA234_CLK_XUSB_SS_DEV << 516 /** @brief xusb_ss_superspeed_clk */ << 517 #define TEGRA234_CLK_XUSB_SS_SUPERSPEED << 518 /** @brief NAFLL clock source for CPU cluster << 519 #define TEGRA234_CLK_NAFLL_CLUSTER0 << 520 #define TEGRA234_CLK_NAFLL_CLUSTER0_CORE << 521 /** @brief NAFLL clock source for CPU cluster << 522 #define TEGRA234_CLK_NAFLL_CLUSTER1 << 523 #define TEGRA234_CLK_NAFLL_CLUSTER1_CORE << 524 /** @brief NAFLL clock source for CPU cluster << 525 #define TEGRA234_CLK_NAFLL_CLUSTER2 << 526 #define TEGRA234_CLK_NAFLL_CLUSTER2_CORE << 527 /** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE d << 528 #define TEGRA234_CLK_CAN1_CORE << 529 /** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE d << 530 #define TEGRA234_CLK_CAN2_CORE << 531 /** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switc << 532 #define TEGRA234_CLK_PLLA1_OUT1 << 533 /** @brief NVHS PLL hardware power sequencer ( << 534 #define TEGRA234_CLK_PLLNVHS_HPS << 535 /** @brief PLL controlled by CLK_RST_CONTROLLE << 536 #define TEGRA234_CLK_PLLREFE_VCOOUT << 537 /** @brief 32K input clock provided by PMIC */ 179 /** @brief 32K input clock provided by PMIC */ 538 #define TEGRA234_CLK_CLK_32K 180 #define TEGRA234_CLK_CLK_32K 289U 539 /** @brief Fixed 48MHz clock divided down from << 540 #define TEGRA234_CLK_UTMIPLL_CLKOUT48 << 541 /** @brief Fixed 480MHz clock divided down fro << 542 #define TEGRA234_CLK_UTMIPLL_CLKOUT480 << 543 /** @brief PLL controlled by CLK_RST_CONTROLLE << 544 #define TEGRA234_CLK_PLLNVCSI << 545 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_ << 546 #define TEGRA234_CLK_PVA0_CPU_AXI << 547 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_ << 548 #define TEGRA234_CLK_PVA0_VPS << 549 /** @brief DLA0_CORE_NAFLL */ << 550 #define TEGRA234_CLK_NAFLL_DLA0_CORE << 551 /** @brief DLA0_FALCON_NAFLL */ << 552 #define TEGRA234_CLK_NAFLL_DLA0_FALCON << 553 /** @brief DLA1_CORE_NAFLL */ << 554 #define TEGRA234_CLK_NAFLL_DLA1_CORE << 555 /** @brief DLA1_FALCON_NAFLL */ << 556 #define TEGRA234_CLK_NAFLL_DLA1_FALCON << 557 /** @brief output of mux controlled by CLK_RST << 558 #define TEGRA234_CLK_AON_UART_FST_MIPI_CAL << 559 /** @brief GPU system clock */ << 560 #define TEGRA234_CLK_GPUSYS << 561 /** @brief output of mux controlled by CLK_RST << 562 #define TEGRA234_CLK_I2C5 << 563 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE sw << 564 #define TEGRA234_CLK_FR_SE << 565 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_ << 566 #define TEGRA234_CLK_BPMP_CPU_NIC << 567 /** @brief output of gate CLK_ENB_BPMP_CPU */ << 568 #define TEGRA234_CLK_BPMP_CPU << 569 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC s << 570 #define TEGRA234_CLK_TSC << 571 /** @brief output of mem pll A sync mux contro << 572 #define TEGRA234_CLK_EMCSA_MPLL << 573 /** @brief output of mem pll B sync mux contro << 574 #define TEGRA234_CLK_EMCSB_MPLL << 575 /** @brief output of mem pll C sync mux contro << 576 #define TEGRA234_CLK_EMCSC_MPLL << 577 /** @brief output of mem pll D sync mux contro << 578 #define TEGRA234_CLK_EMCSD_MPLL << 579 /** @brief PLL controlled by CLK_RST_CONTROLLE << 580 #define TEGRA234_CLK_PLLC << 581 /** @brief PLL controlled by CLK_RST_CONTROLLE << 582 #define TEGRA234_CLK_PLLC2 << 583 /** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK << 584 #define TEGRA234_CLK_TSC_REF << 585 /** @brief Dummy clock to ensure minimum SoC v << 586 #define TEGRA234_CLK_FUSE_BURN << 587 /** @brief GBE PLL */ << 588 #define TEGRA234_CLK_PLLGBE << 589 /** @brief GBE PLL hardware power sequencer */ << 590 #define TEGRA234_CLK_PLLGBE_HPS << 591 /** @brief output of EMC CDB side A fixed (DIV << 592 #define TEGRA234_CLK_EMCSA_EMC << 593 /** @brief output of EMC CDB side B fixed (DIV << 594 #define TEGRA234_CLK_EMCSB_EMC << 595 /** @brief output of EMC CDB side C fixed (DIV << 596 #define TEGRA234_CLK_EMCSC_EMC << 597 /** @brief output of EMC CDB side D fixed (DIV << 598 #define TEGRA234_CLK_EMCSD_EMC << 599 /** @brief PLLE hardware power sequencer (over << 600 #define TEGRA234_CLK_PLLE_HPS << 601 /** @brief CLK_ENB_PLLREFE_OUT gate output */ << 602 #define TEGRA234_CLK_PLLREFE_VCOOUT_GATED << 603 /** @brief TEGRA234_CLK_SOR_SAFE clk source (P << 604 #define TEGRA234_CLK_PLLP_DIV17 << 605 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_T << 606 #define TEGRA234_CLK_SOC_THERM << 607 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENS << 608 #define TEGRA234_CLK_TSENSE << 609 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 << 610 #define TEGRA234_CLK_FR_SEU1 << 611 /** @brief NAFLL clock source for OFA */ << 612 #define TEGRA234_CLK_NAFLL_OFA << 613 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA s << 614 #define TEGRA234_CLK_OFA << 615 /** @brief NAFLL clock source for SEU1 */ << 616 #define TEGRA234_CLK_NAFLL_SEU1 << 617 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 << 618 #define TEGRA234_CLK_SEU1 << 619 /** @brief output of mux controlled by CLK_RST << 620 #define TEGRA234_CLK_SPI4 << 621 /** @brief output of mux controlled by CLK_RST << 622 #define TEGRA234_CLK_SPI5 << 623 /** @brief output of mux controlled by CLK_RST << 624 #define TEGRA234_CLK_DCE_CPU_NIC << 625 /** @brief output of divider CLK_RST_CONTROLLE << 626 #define TEGRA234_CLK_DCE_NIC << 627 /** @brief NAFLL clock source for DCE */ << 628 #define TEGRA234_CLK_NAFLL_DCE << 629 /** @brief Monitored branch of MPHY_L0_RX_ANA << 630 #define TEGRA234_CLK_MPHY_L0_RX_ANA_M << 631 /** @brief Monitored branch of MPHY_L1_RX_ANA << 632 #define TEGRA234_CLK_MPHY_L1_RX_ANA_M << 633 /** @brief ungated version of TX symbol clock << 634 #define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB << 635 /** @brief output of divider CLK_RST_CONTROLLE << 636 #define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV << 637 /** @brief output of gate CLK_ENB_MPHY_L0_TX_2 << 638 #define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB << 639 /** @brief output of SW_MPHY_L0_TX_HS_SYMB div << 640 #define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV << 641 /** @brief output of SW_MPHY_L0_TX_LS_3XBIT di << 642 #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV << 643 /** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_ << 644 #define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV << 645 /** @brief Monitored branch of MPHY_L0_TX_SYMB << 646 #define TEGRA234_CLK_MPHY_L0_TX_SYMB_M << 647 /** @brief output of divider CLK_RST_CONTROLLE << 648 #define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV << 649 /** @brief output of SW_MPHY_L0_RX_HS_SYMB div << 650 #define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV << 651 /** @brief output of SW_MPHY_L0_RX_LS_BIT divi << 652 #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV << 653 /** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_ << 654 #define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV << 655 /** @brief Monitored branch of MPHY_L0_RX_SYMB << 656 #define TEGRA234_CLK_MPHY_L0_RX_SYMB_M << 657 /** @brief Monitored branch of MBGE0 RX input 181 /** @brief Monitored branch of MBGE0 RX input clock */ 658 #define TEGRA234_CLK_MGBE0_RX_INPUT_M 182 #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U 659 /** @brief Monitored branch of MBGE1 RX input 183 /** @brief Monitored branch of MBGE1 RX input clock */ 660 #define TEGRA234_CLK_MGBE1_RX_INPUT_M 184 #define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U 661 /** @brief Monitored branch of MBGE2 RX input 185 /** @brief Monitored branch of MBGE2 RX input clock */ 662 #define TEGRA234_CLK_MGBE2_RX_INPUT_M 186 #define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U 663 /** @brief Monitored branch of MBGE3 RX input 187 /** @brief Monitored branch of MBGE3 RX input clock */ 664 #define TEGRA234_CLK_MGBE3_RX_INPUT_M 188 #define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U 665 /** @brief Monitored branch of MGBE0 RX PCS mu 189 /** @brief Monitored branch of MGBE0 RX PCS mux output */ 666 #define TEGRA234_CLK_MGBE0_RX_PCS_M 190 #define TEGRA234_CLK_MGBE0_RX_PCS_M 361U 667 /** @brief Monitored branch of MGBE1 RX PCS mu 191 /** @brief Monitored branch of MGBE1 RX PCS mux output */ 668 #define TEGRA234_CLK_MGBE1_RX_PCS_M 192 #define TEGRA234_CLK_MGBE1_RX_PCS_M 362U 669 /** @brief Monitored branch of MGBE2 RX PCS mu 193 /** @brief Monitored branch of MGBE2 RX PCS mux output */ 670 #define TEGRA234_CLK_MGBE2_RX_PCS_M 194 #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U 671 /** @brief Monitored branch of MGBE3 RX PCS mu 195 /** @brief Monitored branch of MGBE3 RX PCS mux output */ 672 #define TEGRA234_CLK_MGBE3_RX_PCS_M 196 #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U 673 /** @brief output of mux controlled by CLK_RST << 674 #define TEGRA234_CLK_TACH1 << 675 /** @brief GBE_UPHY_MGBES_APP_CLK switch divid << 676 #define TEGRA234_CLK_MGBES_APP << 677 /** @brief Logical clk for setting GBE UPHY PL << 678 #define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF << 679 /** @brief Logical clk for setting GBE UPHY PL << 680 #define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG << 681 /** @brief RX PCS clock recovered from MGBE0 l 197 /** @brief RX PCS clock recovered from MGBE0 lane input */ 682 #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 198 #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U 683 /** @brief RX PCS clock recovered from MGBE1 l 199 /** @brief RX PCS clock recovered from MGBE1 lane input */ 684 #define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 200 #define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U 685 /** @brief RX PCS clock recovered from MGBE2 l 201 /** @brief RX PCS clock recovered from MGBE2 lane input */ 686 #define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 202 #define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U 687 /** @brief RX PCS clock recovered from MGBE3 l 203 /** @brief RX PCS clock recovered from MGBE3 lane input */ 688 #define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 204 #define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U 689 /** @brief output of mux controlled by GBE_UPH 205 /** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ 690 #define TEGRA234_CLK_MGBE0_RX_PCS 206 #define TEGRA234_CLK_MGBE0_RX_PCS 373U 691 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated 207 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ 692 #define TEGRA234_CLK_MGBE0_TX 208 #define TEGRA234_CLK_MGBE0_TX 374U 693 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider g 209 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ 694 #define TEGRA234_CLK_MGBE0_TX_PCS 210 #define TEGRA234_CLK_MGBE0_TX_PCS 375U 695 /** @brief GBE_UPHY_MGBE0_MAC_CLK divider outp 211 /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ 696 #define TEGRA234_CLK_MGBE0_MAC_DIVIDER 212 #define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U 697 /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output 213 /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ 698 #define TEGRA234_CLK_MGBE0_MAC 214 #define TEGRA234_CLK_MGBE0_MAC 377U 699 /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate outp 215 /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ 700 #define TEGRA234_CLK_MGBE0_MACSEC 216 #define TEGRA234_CLK_MGBE0_MACSEC 378U 701 /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate out 217 /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ 702 #define TEGRA234_CLK_MGBE0_EEE_PCS 218 #define TEGRA234_CLK_MGBE0_EEE_PCS 379U 703 /** @brief GBE_UPHY_MGBE0_APP_CLK gate output 219 /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ 704 #define TEGRA234_CLK_MGBE0_APP 220 #define TEGRA234_CLK_MGBE0_APP 380U 705 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider 221 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ 706 #define TEGRA234_CLK_MGBE0_PTP_REF 222 #define TEGRA234_CLK_MGBE0_PTP_REF 381U 707 /** @brief output of mux controlled by GBE_UPH 223 /** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ 708 #define TEGRA234_CLK_MGBE1_RX_PCS 224 #define TEGRA234_CLK_MGBE1_RX_PCS 382U 709 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated 225 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ 710 #define TEGRA234_CLK_MGBE1_TX 226 #define TEGRA234_CLK_MGBE1_TX 383U 711 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider g 227 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ 712 #define TEGRA234_CLK_MGBE1_TX_PCS 228 #define TEGRA234_CLK_MGBE1_TX_PCS 384U 713 /** @brief GBE_UPHY_MGBE1_MAC_CLK divider outp 229 /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ 714 #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 230 #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U 715 /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output 231 /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ 716 #define TEGRA234_CLK_MGBE1_MAC 232 #define TEGRA234_CLK_MGBE1_MAC 386U 717 /** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate outp << 718 #define TEGRA234_CLK_MGBE1_MACSEC << 719 /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate out 233 /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ 720 #define TEGRA234_CLK_MGBE1_EEE_PCS 234 #define TEGRA234_CLK_MGBE1_EEE_PCS 388U 721 /** @brief GBE_UPHY_MGBE1_APP_CLK gate output 235 /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ 722 #define TEGRA234_CLK_MGBE1_APP 236 #define TEGRA234_CLK_MGBE1_APP 389U 723 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider 237 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ 724 #define TEGRA234_CLK_MGBE1_PTP_REF 238 #define TEGRA234_CLK_MGBE1_PTP_REF 390U 725 /** @brief output of mux controlled by GBE_UPH 239 /** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ 726 #define TEGRA234_CLK_MGBE2_RX_PCS 240 #define TEGRA234_CLK_MGBE2_RX_PCS 391U 727 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated 241 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ 728 #define TEGRA234_CLK_MGBE2_TX 242 #define TEGRA234_CLK_MGBE2_TX 392U 729 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider g 243 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ 730 #define TEGRA234_CLK_MGBE2_TX_PCS 244 #define TEGRA234_CLK_MGBE2_TX_PCS 393U 731 /** @brief GBE_UPHY_MGBE2_MAC_CLK divider outp 245 /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ 732 #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 246 #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U 733 /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output 247 /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ 734 #define TEGRA234_CLK_MGBE2_MAC 248 #define TEGRA234_CLK_MGBE2_MAC 395U 735 /** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate outp << 736 #define TEGRA234_CLK_MGBE2_MACSEC << 737 /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate out 249 /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ 738 #define TEGRA234_CLK_MGBE2_EEE_PCS 250 #define TEGRA234_CLK_MGBE2_EEE_PCS 397U 739 /** @brief GBE_UPHY_MGBE2_APP_CLK gate output 251 /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ 740 #define TEGRA234_CLK_MGBE2_APP 252 #define TEGRA234_CLK_MGBE2_APP 398U 741 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider 253 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ 742 #define TEGRA234_CLK_MGBE2_PTP_REF 254 #define TEGRA234_CLK_MGBE2_PTP_REF 399U 743 /** @brief output of mux controlled by GBE_UPH 255 /** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ 744 #define TEGRA234_CLK_MGBE3_RX_PCS 256 #define TEGRA234_CLK_MGBE3_RX_PCS 400U 745 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated 257 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ 746 #define TEGRA234_CLK_MGBE3_TX 258 #define TEGRA234_CLK_MGBE3_TX 401U 747 /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider g 259 /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ 748 #define TEGRA234_CLK_MGBE3_TX_PCS 260 #define TEGRA234_CLK_MGBE3_TX_PCS 402U 749 /** @brief GBE_UPHY_MGBE3_MAC_CLK divider outp 261 /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ 750 #define TEGRA234_CLK_MGBE3_MAC_DIVIDER 262 #define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U 751 /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output 263 /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ 752 #define TEGRA234_CLK_MGBE3_MAC 264 #define TEGRA234_CLK_MGBE3_MAC 404U 753 /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate outp 265 /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ 754 #define TEGRA234_CLK_MGBE3_MACSEC 266 #define TEGRA234_CLK_MGBE3_MACSEC 405U 755 /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate out 267 /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ 756 #define TEGRA234_CLK_MGBE3_EEE_PCS 268 #define TEGRA234_CLK_MGBE3_EEE_PCS 406U 757 /** @brief GBE_UPHY_MGBE3_APP_CLK gate output 269 /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ 758 #define TEGRA234_CLK_MGBE3_APP 270 #define TEGRA234_CLK_MGBE3_APP 407U 759 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider 271 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ 760 #define TEGRA234_CLK_MGBE3_PTP_REF 272 #define TEGRA234_CLK_MGBE3_PTP_REF 408U 761 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_R << 762 #define TEGRA234_CLK_GBE_RX_BYP_REF << 763 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_P << 764 #define TEGRA234_CLK_GBE_PLL0_MGMT << 765 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_P << 766 #define TEGRA234_CLK_GBE_PLL1_MGMT << 767 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_P << 768 #define TEGRA234_CLK_GBE_PLL2_MGMT << 769 /** @brief output of gate CLK_ENB_EQOS_MACSEC_ << 770 #define TEGRA234_CLK_EQOS_MACSEC_RX << 771 /** @brief output of gate CLK_ENB_EQOS_MACSEC_ << 772 #define TEGRA234_CLK_EQOS_MACSEC_TX << 773 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_ << 774 #define TEGRA234_CLK_EQOS_TX_DIVIDER << 775 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_ << 776 #define TEGRA234_CLK_NVHS_PLL1_MGMT << 777 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHU << 778 #define TEGRA234_CLK_EMCHUB << 779 /** @brief clock recovered from I2S7 input */ << 780 #define TEGRA234_CLK_I2S7_SYNC_INPUT << 781 /** @brief output of mux controlled by CLK_RST << 782 #define TEGRA234_CLK_SYNC_I2S7 << 783 /** @brief output of mux controlled by CLK_RST << 784 #define TEGRA234_CLK_I2S7 << 785 /** @brief Monitored output of I2S7 pad macro << 786 #define TEGRA234_CLK_I2S7_PAD_M << 787 /** @brief clock recovered from I2S8 input */ << 788 #define TEGRA234_CLK_I2S8_SYNC_INPUT << 789 /** @brief output of mux controlled by CLK_RST << 790 #define TEGRA234_CLK_SYNC_I2S8 << 791 /** @brief output of mux controlled by CLK_RST << 792 #define TEGRA234_CLK_I2S8 << 793 /** @brief Monitored output of I2S8 pad macro << 794 #define TEGRA234_CLK_I2S8_PAD_M << 795 /** @brief NAFLL clock source for GPU GPC0 */ << 796 #define TEGRA234_CLK_NAFLL_GPC0 << 797 /** @brief NAFLL clock source for GPU GPC1 */ << 798 #define TEGRA234_CLK_NAFLL_GPC1 << 799 /** @brief NAFLL clock source for GPU SYSCLK * << 800 #define TEGRA234_CLK_NAFLL_GPUSYS << 801 /** @brief NAFLL clock source for CPU cluster << 802 #define TEGRA234_CLK_NAFLL_DSU0 << 803 #define TEGRA234_CLK_NAFLL_CLUSTER0_DSU << 804 /** @brief NAFLL clock source for CPU cluster << 805 #define TEGRA234_CLK_NAFLL_DSU1 << 806 #define TEGRA234_CLK_NAFLL_CLUSTER1_DSU << 807 /** @brief NAFLL clock source for CPU cluster << 808 #define TEGRA234_CLK_NAFLL_DSU2 << 809 #define TEGRA234_CLK_NAFLL_CLUSTER2_DSU << 810 /** @brief output of gate CLK_ENB_SCE_CPU */ << 811 #define TEGRA234_CLK_SCE_CPU << 812 /** @brief output of gate CLK_ENB_RCE_CPU */ << 813 #define TEGRA234_CLK_RCE_CPU << 814 /** @brief output of gate CLK_ENB_DCE_CPU */ << 815 #define TEGRA234_CLK_DCE_CPU << 816 /** @brief DSIPLL VCO output */ << 817 #define TEGRA234_CLK_DSIPLL_VCO << 818 /** @brief DSIPLL SYNC_CLKOUTP/N differential << 819 #define TEGRA234_CLK_DSIPLL_CLKOUTPN << 820 /** @brief DSIPLL SYNC_CLKOUTA output */ << 821 #define TEGRA234_CLK_DSIPLL_CLKOUTA << 822 /** @brief SPPLL0 VCO output */ << 823 #define TEGRA234_CLK_SPPLL0_VCO << 824 /** @brief SPPLL0 SYNC_CLKOUTP/N differential << 825 #define TEGRA234_CLK_SPPLL0_CLKOUTPN << 826 /** @brief SPPLL0 SYNC_CLKOUTA output */ << 827 #define TEGRA234_CLK_SPPLL0_CLKOUTA << 828 /** @brief SPPLL0 SYNC_CLKOUTB output */ << 829 #define TEGRA234_CLK_SPPLL0_CLKOUTB << 830 /** @brief SPPLL0 CLKOUT_DIVBY10 output */ << 831 #define TEGRA234_CLK_SPPLL0_DIV10 << 832 /** @brief SPPLL0 CLKOUT_DIVBY25 output */ << 833 #define TEGRA234_CLK_SPPLL0_DIV25 << 834 /** @brief SPPLL0 CLKOUT_DIVBY27P/N differenti << 835 #define TEGRA234_CLK_SPPLL0_DIV27PN << 836 /** @brief SPPLL1 VCO output */ << 837 #define TEGRA234_CLK_SPPLL1_VCO << 838 /** @brief SPPLL1 SYNC_CLKOUTP/N differential << 839 #define TEGRA234_CLK_SPPLL1_CLKOUTPN << 840 /** @brief SPPLL1 CLKOUT_DIVBY27P/N differenti << 841 #define TEGRA234_CLK_SPPLL1_DIV27PN << 842 /** @brief VPLL0 reference clock */ << 843 #define TEGRA234_CLK_VPLL0_REF << 844 /** @brief VPLL0 */ << 845 #define TEGRA234_CLK_VPLL0 << 846 /** @brief VPLL1 */ << 847 #define TEGRA234_CLK_VPLL1 << 848 /** @brief NVDISPLAY_P0_CLK reference select * << 849 #define TEGRA234_CLK_NVDISPLAY_P0_REF << 850 /** @brief RG0_PCLK */ << 851 #define TEGRA234_CLK_RG0 << 852 /** @brief RG1_PCLK */ << 853 #define TEGRA234_CLK_RG1 << 854 /** @brief DISPPLL output */ << 855 #define TEGRA234_CLK_DISPPLL << 856 /** @brief DISPHUBPLL output */ << 857 #define TEGRA234_CLK_DISPHUBPLL << 858 /** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DI << 859 #define TEGRA234_CLK_DSI_LP << 860 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_ 273 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ 861 #define TEGRA234_CLK_AZA_2XBIT 274 #define TEGRA234_CLK_AZA_2XBIT 457U 862 /** @brief aza_2xbitclk / 2 (aza_bitclk) */ 275 /** @brief aza_2xbitclk / 2 (aza_bitclk) */ 863 #define TEGRA234_CLK_AZA_BIT 276 #define TEGRA234_CLK_AZA_BIT 458U 864 /** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE << 865 #define TEGRA234_CLK_DSI_CORE << 866 /** @brief Output of mux controlled by pkt_wr_ << 867 #define TEGRA234_CLK_DSI_PIXEL << 868 /** @brief Output of mux controlled by disp_2c << 869 #define TEGRA234_CLK_PRE_SOR0 << 870 /** @brief Output of mux controlled by disp_2c << 871 #define TEGRA234_CLK_PRE_SOR1 << 872 /** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG_ << 873 #define TEGRA234_CLK_DP_LINK_REF << 874 /** @brief Link clock input from DP macro bric << 875 #define TEGRA234_CLK_SOR_LINKA_INPUT << 876 /** @brief SOR AFIFO clock outut */ << 877 #define TEGRA234_CLK_SOR_LINKA_AFIFO << 878 /** @brief Monitored branch of linka_afifo_clk << 879 #define TEGRA234_CLK_SOR_LINKA_AFIFO_M << 880 /** @brief Monitored branch of rg0_pclk */ << 881 #define TEGRA234_CLK_RG0_M << 882 /** @brief Monitored branch of rg1_pclk */ << 883 #define TEGRA234_CLK_RG1_M << 884 /** @brief Monitored branch of sor0_clk */ << 885 #define TEGRA234_CLK_SOR0_M << 886 /** @brief Monitored branch of sor1_clk */ << 887 #define TEGRA234_CLK_SOR1_M << 888 /** @brief EMC PLLHUB output */ << 889 #define TEGRA234_CLK_PLLHUB << 890 /** @brief output of fixed (DIV2) MC HUB divid << 891 #define TEGRA234_CLK_MCHUB << 892 /** @brief output of divider controlled by EMC << 893 #define TEGRA234_CLK_EMCSA_MC << 894 /** @brief output of divider controlled by EMC << 895 #define TEGRA234_CLK_EMCSB_MC << 896 /** @brief output of divider controlled by EMC << 897 #define TEGRA234_CLK_EMCSC_MC << 898 /** @brief output of divider controlled by EMC << 899 #define TEGRA234_CLK_EMCSD_MC << 900 << 901 /** @} */ << 902 277 903 #endif 278 #endif 904 279

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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h

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Differences between /scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h (Version linux-6.1.116)

TOMOYO Linux Cross Reference Linux/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h

Diff markup

Differences between /scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h (Version linux-6.1.116)

TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/dt-bindings/clock/tegra234-clock.h