1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * This header provides macros for at91 dma bi 3 * This header provides macros for at91 dma bindings. 4 * 4 * 5 * Copyright (C) 2013 Ludovic Desroches <ludov 5 * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 6 */ 6 */ 7 7 8 #ifndef __DT_BINDINGS_AT91_DMA_H__ 8 #ifndef __DT_BINDINGS_AT91_DMA_H__ 9 #define __DT_BINDINGS_AT91_DMA_H__ 9 #define __DT_BINDINGS_AT91_DMA_H__ 10 10 11 /* ---------- HDMAC ---------- */ 11 /* ---------- HDMAC ---------- */ 12 12 13 /* 13 /* 14 * Source and/or destination peripheral ID 14 * Source and/or destination peripheral ID 15 */ 15 */ 16 #define AT91_DMA_CFG_PER_ID_MASK (0xff) 16 #define AT91_DMA_CFG_PER_ID_MASK (0xff) 17 #define AT91_DMA_CFG_PER_ID(id) (id & 17 #define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) 18 18 19 /* 19 /* 20 * FIFO configuration: it defines when a reque 20 * FIFO configuration: it defines when a request is serviced. 21 */ 21 */ 22 #define AT91_DMA_CFG_FIFOCFG_OFFSET (8) 22 #define AT91_DMA_CFG_FIFOCFG_OFFSET (8) 23 #define AT91_DMA_CFG_FIFOCFG_MASK (0xf < 23 #define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) 24 #define AT91_DMA_CFG_FIFOCFG_HALF (0x0 < 24 #define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ 25 #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 < 25 #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ 26 #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 < 26 #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ 27 27 28 28 29 /* ---------- XDMAC ---------- */ 29 /* ---------- XDMAC ---------- */ 30 #define AT91_XDMAC_DT_MEM_IF_MASK (0x1) 30 #define AT91_XDMAC_DT_MEM_IF_MASK (0x1) 31 #define AT91_XDMAC_DT_MEM_IF_OFFSET (13) 31 #define AT91_XDMAC_DT_MEM_IF_OFFSET (13) 32 #define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem 32 #define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ 33 << AT9 33 << AT91_XDMAC_DT_MEM_IF_OFFSET) 34 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg 34 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ 35 & AT91 35 & AT91_XDMAC_DT_MEM_IF_MASK) 36 36 37 #define AT91_XDMAC_DT_PER_IF_MASK (0x1) 37 #define AT91_XDMAC_DT_PER_IF_MASK (0x1) 38 #define AT91_XDMAC_DT_PER_IF_OFFSET (14) 38 #define AT91_XDMAC_DT_PER_IF_OFFSET (14) 39 #define AT91_XDMAC_DT_PER_IF(per_if) (((per 39 #define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ 40 << AT9 40 << AT91_XDMAC_DT_PER_IF_OFFSET) 41 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg 41 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ 42 & AT91 42 & AT91_XDMAC_DT_PER_IF_MASK) 43 43 44 #define AT91_XDMAC_DT_PERID_MASK (0x7f) 44 #define AT91_XDMAC_DT_PERID_MASK (0x7f) 45 #define AT91_XDMAC_DT_PERID_OFFSET (24) 45 #define AT91_XDMAC_DT_PERID_OFFSET (24) 46 #define AT91_XDMAC_DT_PERID(perid) (((per 46 #define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ 47 << AT9 47 << AT91_XDMAC_DT_PERID_OFFSET) 48 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg 48 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ 49 & AT91 49 & AT91_XDMAC_DT_PERID_MASK) 50 50 51 #endif /* __DT_BINDINGS_AT91_DMA_H__ */ 51 #endif /* __DT_BINDINGS_AT91_DMA_H__ */ 52 52
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