1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Dennis-YC Hsieh <dennis-yc.hsieh@me 5 */ 6 7 #ifndef _DT_BINDINGS_GCE_MT6779_H 8 #define _DT_BINDINGS_GCE_MT6779_H 9 10 #define CMDQ_NO_TIMEOUT 0xffffffff 11 12 /* GCE HW thread priority */ 13 #define CMDQ_THR_PRIO_LOWEST 0 14 #define CMDQ_THR_PRIO_1 1 15 #define CMDQ_THR_PRIO_2 2 16 #define CMDQ_THR_PRIO_3 3 17 #define CMDQ_THR_PRIO_4 4 18 #define CMDQ_THR_PRIO_5 5 19 #define CMDQ_THR_PRIO_6 6 20 #define CMDQ_THR_PRIO_HIGHEST 7 21 22 /* GCE subsys table */ 23 #define SUBSYS_1300XXXX 0 24 #define SUBSYS_1400XXXX 1 25 #define SUBSYS_1401XXXX 2 26 #define SUBSYS_1402XXXX 3 27 #define SUBSYS_1502XXXX 4 28 #define SUBSYS_1880XXXX 5 29 #define SUBSYS_1881XXXX 6 30 #define SUBSYS_1882XXXX 7 31 #define SUBSYS_1883XXXX 8 32 #define SUBSYS_1884XXXX 9 33 #define SUBSYS_1000XXXX 10 34 #define SUBSYS_1001XXXX 11 35 #define SUBSYS_1002XXXX 12 36 #define SUBSYS_1003XXXX 13 37 #define SUBSYS_1004XXXX 14 38 #define SUBSYS_1005XXXX 15 39 #define SUBSYS_1020XXXX 16 40 #define SUBSYS_1028XXXX 17 41 #define SUBSYS_1700XXXX 18 42 #define SUBSYS_1701XXXX 19 43 #define SUBSYS_1702XXXX 20 44 #define SUBSYS_1703XXXX 21 45 #define SUBSYS_1800XXXX 22 46 #define SUBSYS_1801XXXX 23 47 #define SUBSYS_1802XXXX 24 48 #define SUBSYS_1804XXXX 25 49 #define SUBSYS_1805XXXX 26 50 #define SUBSYS_1808XXXX 27 51 #define SUBSYS_180aXXXX 28 52 #define SUBSYS_180bXXXX 29 53 #define CMDQ_SUBSYS_OFF 32 54 55 /* GCE hardware events */ 56 #define CMDQ_EVENT_DISP_RDMA0_SOF 57 #define CMDQ_EVENT_DISP_RDMA1_SOF 58 #define CMDQ_EVENT_MDP_RDMA0_SOF 59 #define CMDQ_EVENT_MDP_RDMA1_SOF 60 #define CMDQ_EVENT_MDP_RSZ0_SOF 61 #define CMDQ_EVENT_MDP_RSZ1_SOF 62 #define CMDQ_EVENT_MDP_TDSHP_SOF 63 #define CMDQ_EVENT_MDP_WROT0_SOF 64 #define CMDQ_EVENT_MDP_WROT1_SOF 65 #define CMDQ_EVENT_DISP_OVL0_SOF 66 #define CMDQ_EVENT_DISP_2L_OVL0_SOF 67 #define CMDQ_EVENT_DISP_2L_OVL1_SOF 68 #define CMDQ_EVENT_DISP_WDMA0_SOF 69 #define CMDQ_EVENT_DISP_COLOR0_SOF 70 #define CMDQ_EVENT_DISP_CCORR0_SOF 71 #define CMDQ_EVENT_DISP_AAL0_SOF 72 #define CMDQ_EVENT_DISP_GAMMA0_SOF 73 #define CMDQ_EVENT_DISP_DITHER0_SOF 74 #define CMDQ_EVENT_DISP_PWM0_SOF 75 #define CMDQ_EVENT_DISP_DSI0_SOF 76 #define CMDQ_EVENT_DISP_DPI0_SOF 77 #define CMDQ_EVENT_DISP_POSTMASK0_SOF 78 #define CMDQ_EVENT_DISP_RSZ0_SOF 79 #define CMDQ_EVENT_MDP_AAL_SOF 80 #define CMDQ_EVENT_MDP_CCORR_SOF 81 #define CMDQ_EVENT_DISP_DBI0_SOF 82 #define CMDQ_EVENT_ISP_RELAY_SOF 83 #define CMDQ_EVENT_IPU_RELAY_SOF 84 #define CMDQ_EVENT_DISP_RDMA0_EOF 85 #define CMDQ_EVENT_DISP_RDMA1_EOF 86 #define CMDQ_EVENT_MDP_RDMA0_EOF 87 #define CMDQ_EVENT_MDP_RDMA1_EOF 88 #define CMDQ_EVENT_MDP_RSZ0_EOF 89 #define CMDQ_EVENT_MDP_RSZ1_EOF 90 #define CMDQ_EVENT_MDP_TDSHP_EOF 91 #define CMDQ_EVENT_MDP_WROT0_W_EOF 92 #define CMDQ_EVENT_MDP_WROT1_W_EOF 93 #define CMDQ_EVENT_DISP_OVL0_EOF 94 #define CMDQ_EVENT_DISP_2L_OVL0_EOF 95 #define CMDQ_EVENT_DISP_2L_OVL1_EOF 96 #define CMDQ_EVENT_DISP_WDMA0_EOF 97 #define CMDQ_EVENT_DISP_COLOR0_EOF 98 #define CMDQ_EVENT_DISP_CCORR0_EOF 99 #define CMDQ_EVENT_DISP_AAL0_EOF 100 #define CMDQ_EVENT_DISP_GAMMA0_EOF 101 #define CMDQ_EVENT_DISP_DITHER0_EOF 102 #define CMDQ_EVENT_DISP_DSI0_EOF 103 #define CMDQ_EVENT_DISP_DPI0_EOF 104 #define CMDQ_EVENT_DISP_RSZ0_EOF 105 #define CMDQ_EVENT_MDP_AAL_FRAME_DONE 106 #define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 107 #define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 108 #define CMDQ_EVENT_MUTEX0_STREAM_EOF 109 #define CMDQ_EVENT_MUTEX1_STREAM_EOF 110 #define CMDQ_EVENT_MUTEX2_STREAM_EOF 111 #define CMDQ_EVENT_MUTEX3_STREAM_EOF 112 #define CMDQ_EVENT_MUTEX4_STREAM_EOF 113 #define CMDQ_EVENT_MUTEX5_STREAM_EOF 114 #define CMDQ_EVENT_MUTEX6_STREAM_EOF 115 #define CMDQ_EVENT_MUTEX7_STREAM_EOF 116 #define CMDQ_EVENT_MUTEX8_STREAM_EOF 117 #define CMDQ_EVENT_MUTEX9_STREAM_EOF 118 #define CMDQ_EVENT_MUTEX10_STREAM_EOF 119 #define CMDQ_EVENT_MUTEX11_STREAM_EOF 120 #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 121 #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 122 #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 123 #define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 124 #define CMDQ_EVENT_DSI0_TE 125 #define CMDQ_EVENT_DSI0_IRQ_EVENT 126 #define CMDQ_EVENT_DSI0_DONE_EVENT 127 #define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 128 #define CMDQ_EVENT_DISP_WDMA0_RST_DONE 129 #define CMDQ_EVENT_MDP_WROT0_RST_DONE 130 #define CMDQ_EVENT_MDP_RDMA0_RST_DONE 131 #define CMDQ_EVENT_DISP_OVL0_RST_DONE 132 #define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 133 #define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 134 #define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 135 #define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 136 #define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 137 #define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 138 #define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 139 #define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 140 #define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 141 #define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 142 #define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 143 #define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 144 #define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 145 #define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 146 #define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 147 #define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 148 #define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 149 #define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 150 #define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 151 #define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 152 #define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 153 #define CMDQ_EVENT_DIP_DMA_ERR_EVENT 154 #define CMDQ_EVENT_AMD_FRAME_DONE 155 #define CMDQ_EVENT_MFB_DONE 156 #define CMDQ_EVENT_WPE_A_EOF 157 #define CMDQ_EVENT_VENC_EOF 158 #define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 159 #define CMDQ_EVENT_JPEG_ENC_EOF 160 #define CMDQ_EVENT_VENC_MB_DONE 161 #define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 162 #define CMDQ_EVENT_ISP_FRAME_DONE_A 163 #define CMDQ_EVENT_ISP_FRAME_DONE_B 164 #define CMDQ_EVENT_ISP_FRAME_DONE_C 165 #define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 166 #define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 167 #define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 168 #define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 169 #define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 170 #define CMDQ_EVENT_ISP_TSF_DONE 171 #define CMDQ_EVENT_SENINF_0_FIFO_FULL 172 #define CMDQ_EVENT_SENINF_1_FIFO_FULL 173 #define CMDQ_EVENT_SENINF_2_FIFO_FULL 174 #define CMDQ_EVENT_SENINF_3_FIFO_FULL 175 #define CMDQ_EVENT_SENINF_4_FIFO_FULL 176 #define CMDQ_EVENT_SENINF_5_FIFO_FULL 177 #define CMDQ_EVENT_SENINF_6_FIFO_FULL 178 #define CMDQ_EVENT_SENINF_7_FIFO_FULL 179 #define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 180 #define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 181 #define CMDQ_EVENT_TG_OVRUN_C_INT 182 #define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 183 #define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 184 #define CMDQ_EVENT_TG_GRABERR_C_INT 185 #define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 186 #define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 187 #define CMDQ_EVENT_CQ_VR_SNAP_C_INT 188 #define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 189 #define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 190 #define CMDQ_EVENT_DMA_R1_ERROR_C_INT 191 #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 192 #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 193 #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 194 #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 195 #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 196 #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 197 #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 198 #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 199 #define CMDQ_EVENT_VDEC_EVENT_0 200 #define CMDQ_EVENT_VDEC_EVENT_1 201 #define CMDQ_EVENT_VDEC_EVENT_2 202 #define CMDQ_EVENT_VDEC_EVENT_3 203 #define CMDQ_EVENT_VDEC_EVENT_4 204 #define CMDQ_EVENT_VDEC_EVENT_5 205 #define CMDQ_EVENT_VDEC_EVENT_6 206 #define CMDQ_EVENT_VDEC_EVENT_7 207 #define CMDQ_EVENT_VDEC_EVENT_8 208 #define CMDQ_EVENT_VDEC_EVENT_9 209 #define CMDQ_EVENT_VDEC_EVENT_10 210 #define CMDQ_EVENT_VDEC_EVENT_11 211 #define CMDQ_EVENT_VDEC_EVENT_12 212 #define CMDQ_EVENT_VDEC_EVENT_13 213 #define CMDQ_EVENT_VDEC_EVENT_14 214 #define CMDQ_EVENT_VDEC_EVENT_15 215 #define CMDQ_EVENT_FDVT_DONE 216 #define CMDQ_EVENT_FE_DONE 217 #define CMDQ_EVENT_RSC_EOF 218 #define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 219 #define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 220 #define CMDQ_EVENT_DSI0_TE_INFRA 221 222 #endif 223
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