1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* Copyright (c) 2020, NVIDIA CORPORATION. All 3 4 /* 5 * This header provides constants for binding 6 * 7 * The first cell in Tegra's GPIO specifier is 8 * provide names for this. 9 * 10 * The second cell contains standard flag valu 11 */ 12 13 #ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 14 #define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 15 16 #include <dt-bindings/gpio/gpio.h> 17 18 /* GPIOs implemented by main GPIO controller * 19 #define TEGRA234_MAIN_GPIO_PORT_A 0 20 #define TEGRA234_MAIN_GPIO_PORT_B 1 21 #define TEGRA234_MAIN_GPIO_PORT_C 2 22 #define TEGRA234_MAIN_GPIO_PORT_D 3 23 #define TEGRA234_MAIN_GPIO_PORT_E 4 24 #define TEGRA234_MAIN_GPIO_PORT_F 5 25 #define TEGRA234_MAIN_GPIO_PORT_G 6 26 #define TEGRA234_MAIN_GPIO_PORT_H 7 27 #define TEGRA234_MAIN_GPIO_PORT_I 8 28 #define TEGRA234_MAIN_GPIO_PORT_J 9 29 #define TEGRA234_MAIN_GPIO_PORT_K 10 30 #define TEGRA234_MAIN_GPIO_PORT_L 11 31 #define TEGRA234_MAIN_GPIO_PORT_M 12 32 #define TEGRA234_MAIN_GPIO_PORT_N 13 33 #define TEGRA234_MAIN_GPIO_PORT_P 14 34 #define TEGRA234_MAIN_GPIO_PORT_Q 15 35 #define TEGRA234_MAIN_GPIO_PORT_R 16 36 #define TEGRA234_MAIN_GPIO_PORT_X 17 37 #define TEGRA234_MAIN_GPIO_PORT_Y 18 38 #define TEGRA234_MAIN_GPIO_PORT_Z 19 39 #define TEGRA234_MAIN_GPIO_PORT_AC 20 40 #define TEGRA234_MAIN_GPIO_PORT_AD 21 41 #define TEGRA234_MAIN_GPIO_PORT_AE 22 42 #define TEGRA234_MAIN_GPIO_PORT_AF 23 43 #define TEGRA234_MAIN_GPIO_PORT_AG 24 44 45 #define TEGRA234_MAIN_GPIO(port, offset) \ 46 ((TEGRA234_MAIN_GPIO_PORT_##port * 8) 47 48 /* GPIOs implemented by AON GPIO controller */ 49 #define TEGRA234_AON_GPIO_PORT_AA 0 50 #define TEGRA234_AON_GPIO_PORT_BB 1 51 #define TEGRA234_AON_GPIO_PORT_CC 2 52 #define TEGRA234_AON_GPIO_PORT_DD 3 53 #define TEGRA234_AON_GPIO_PORT_EE 4 54 #define TEGRA234_AON_GPIO_PORT_GG 5 55 56 #define TEGRA234_AON_GPIO(port, offset) \ 57 ((TEGRA234_AON_GPIO_PORT_##port * 8) + 58 59 #endif 60
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