1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) * 1 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Chun-Jie Chen <chun-jie.chen@mediat 5 */ 6 7 #ifndef _DT_BINDINGS_POWER_MT8195_POWER_H 8 #define _DT_BINDINGS_POWER_MT8195_POWER_H 9 10 #define MT8195_POWER_DOMAIN_PCIE_MAC_P0 11 #define MT8195_POWER_DOMAIN_PCIE_MAC_P1 12 #define MT8195_POWER_DOMAIN_PCIE_PHY 13 #define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 14 #define MT8195_POWER_DOMAIN_CSI_RX_TOP 15 #define MT8195_POWER_DOMAIN_ETHER 16 #define MT8195_POWER_DOMAIN_ADSP 17 #define MT8195_POWER_DOMAIN_AUDIO 18 #define MT8195_POWER_DOMAIN_MFG0 19 #define MT8195_POWER_DOMAIN_MFG1 20 #define MT8195_POWER_DOMAIN_MFG2 21 #define MT8195_POWER_DOMAIN_MFG3 22 #define MT8195_POWER_DOMAIN_MFG4 23 #define MT8195_POWER_DOMAIN_MFG5 24 #define MT8195_POWER_DOMAIN_MFG6 25 #define MT8195_POWER_DOMAIN_VPPSYS0 26 #define MT8195_POWER_DOMAIN_VDOSYS0 27 #define MT8195_POWER_DOMAIN_VPPSYS1 28 #define MT8195_POWER_DOMAIN_VDOSYS1 29 #define MT8195_POWER_DOMAIN_DP_TX 30 #define MT8195_POWER_DOMAIN_EPD_TX 31 #define MT8195_POWER_DOMAIN_HDMI_TX 32 #define MT8195_POWER_DOMAIN_WPESYS 33 #define MT8195_POWER_DOMAIN_VDEC0 34 #define MT8195_POWER_DOMAIN_VDEC1 35 #define MT8195_POWER_DOMAIN_VDEC2 36 #define MT8195_POWER_DOMAIN_VENC 37 #define MT8195_POWER_DOMAIN_VENC_CORE1 38 #define MT8195_POWER_DOMAIN_IMG 39 #define MT8195_POWER_DOMAIN_DIP 40 #define MT8195_POWER_DOMAIN_IPE 41 #define MT8195_POWER_DOMAIN_CAM 42 #define MT8195_POWER_DOMAIN_CAM_RAWA 43 #define MT8195_POWER_DOMAIN_CAM_RAWB 44 #define MT8195_POWER_DOMAIN_CAM_MRAW 45 46 #endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */ 47
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