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Linux/scripts/dtc/include-prefixes/dt-bindings/reset/airoha,en7581-reset.h

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Diff markup

Differences between /scripts/dtc/include-prefixes/dt-bindings/reset/airoha,en7581-reset.h (Architecture i386) and /scripts/dtc/include-prefixes/dt-bindings/reset/airoha,en7581-reset.h (Architecture alpha)


  1 // SPDX-License-Identifier: GPL-2.0-only            1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*                                                  2 /*
  3  * Copyright (c) 2024 AIROHA Inc                    3  * Copyright (c) 2024 AIROHA Inc
  4  * Author: Lorenzo Bianconi <lorenzo@kernel.or      4  * Author: Lorenzo Bianconi <lorenzo@kernel.org>
  5  */                                                 5  */
  6                                                     6 
  7 #ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_      7 #ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
  8 #define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_      8 #define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
  9                                                     9 
 10 /* RST_CTRL2 */                                    10 /* RST_CTRL2 */
 11 #define EN7581_XPON_PHY_RST              0         11 #define EN7581_XPON_PHY_RST              0
 12 #define EN7581_CPU_TIMER2_RST            1         12 #define EN7581_CPU_TIMER2_RST            1
 13 #define EN7581_HSUART_RST                2         13 #define EN7581_HSUART_RST                2
 14 #define EN7581_UART4_RST                 3         14 #define EN7581_UART4_RST                 3
 15 #define EN7581_UART5_RST                 4         15 #define EN7581_UART5_RST                 4
 16 #define EN7581_I2C2_RST                  5         16 #define EN7581_I2C2_RST                  5
 17 #define EN7581_XSI_MAC_RST               6         17 #define EN7581_XSI_MAC_RST               6
 18 #define EN7581_XSI_PHY_RST               7         18 #define EN7581_XSI_PHY_RST               7
 19 #define EN7581_NPU_RST                   8         19 #define EN7581_NPU_RST                   8
 20 #define EN7581_I2S_RST                   9         20 #define EN7581_I2S_RST                   9
 21 #define EN7581_TRNG_RST                 10         21 #define EN7581_TRNG_RST                 10
 22 #define EN7581_TRNG_MSTART_RST          11         22 #define EN7581_TRNG_MSTART_RST          11
 23 #define EN7581_DUAL_HSI0_RST            12         23 #define EN7581_DUAL_HSI0_RST            12
 24 #define EN7581_DUAL_HSI1_RST            13         24 #define EN7581_DUAL_HSI1_RST            13
 25 #define EN7581_HSI_RST                  14         25 #define EN7581_HSI_RST                  14
 26 #define EN7581_DUAL_HSI0_MAC_RST        15         26 #define EN7581_DUAL_HSI0_MAC_RST        15
 27 #define EN7581_DUAL_HSI1_MAC_RST        16         27 #define EN7581_DUAL_HSI1_MAC_RST        16
 28 #define EN7581_HSI_MAC_RST              17         28 #define EN7581_HSI_MAC_RST              17
 29 #define EN7581_WDMA_RST                 18         29 #define EN7581_WDMA_RST                 18
 30 #define EN7581_WOE0_RST                 19         30 #define EN7581_WOE0_RST                 19
 31 #define EN7581_WOE1_RST                 20         31 #define EN7581_WOE1_RST                 20
 32 #define EN7581_HSDMA_RST                21         32 #define EN7581_HSDMA_RST                21
 33 #define EN7581_TDMA_RST                 22         33 #define EN7581_TDMA_RST                 22
 34 #define EN7581_EMMC_RST                 23         34 #define EN7581_EMMC_RST                 23
 35 #define EN7581_SOE_RST                  24         35 #define EN7581_SOE_RST                  24
 36 #define EN7581_PCIE2_RST                25         36 #define EN7581_PCIE2_RST                25
 37 #define EN7581_XFP_MAC_RST              26         37 #define EN7581_XFP_MAC_RST              26
 38 #define EN7581_USB_HOST_P1_RST          27         38 #define EN7581_USB_HOST_P1_RST          27
 39 #define EN7581_USB_HOST_P1_U3_PHY_RST   28         39 #define EN7581_USB_HOST_P1_U3_PHY_RST   28
 40 /* RST_CTRL1 */                                    40 /* RST_CTRL1 */
 41 #define EN7581_PCM1_ZSI_ISI_RST         29         41 #define EN7581_PCM1_ZSI_ISI_RST         29
 42 #define EN7581_FE_PDMA_RST              30         42 #define EN7581_FE_PDMA_RST              30
 43 #define EN7581_FE_QDMA_RST              31         43 #define EN7581_FE_QDMA_RST              31
 44 #define EN7581_PCM_SPIWP_RST            32         44 #define EN7581_PCM_SPIWP_RST            32
 45 #define EN7581_CRYPTO_RST               33         45 #define EN7581_CRYPTO_RST               33
 46 #define EN7581_TIMER_RST                34         46 #define EN7581_TIMER_RST                34
 47 #define EN7581_PCM1_RST                 35         47 #define EN7581_PCM1_RST                 35
 48 #define EN7581_UART_RST                 36         48 #define EN7581_UART_RST                 36
 49 #define EN7581_GPIO_RST                 37         49 #define EN7581_GPIO_RST                 37
 50 #define EN7581_GDMA_RST                 38         50 #define EN7581_GDMA_RST                 38
 51 #define EN7581_I2C_MASTER_RST           39         51 #define EN7581_I2C_MASTER_RST           39
 52 #define EN7581_PCM2_ZSI_ISI_RST         40         52 #define EN7581_PCM2_ZSI_ISI_RST         40
 53 #define EN7581_SFC_RST                  41         53 #define EN7581_SFC_RST                  41
 54 #define EN7581_UART2_RST                42         54 #define EN7581_UART2_RST                42
 55 #define EN7581_GDMP_RST                 43         55 #define EN7581_GDMP_RST                 43
 56 #define EN7581_FE_RST                   44         56 #define EN7581_FE_RST                   44
 57 #define EN7581_USB_HOST_P0_RST          45         57 #define EN7581_USB_HOST_P0_RST          45
 58 #define EN7581_GSW_RST                  46         58 #define EN7581_GSW_RST                  46
 59 #define EN7581_SFC2_PCM_RST             47         59 #define EN7581_SFC2_PCM_RST             47
 60 #define EN7581_PCIE0_RST                48         60 #define EN7581_PCIE0_RST                48
 61 #define EN7581_PCIE1_RST                49         61 #define EN7581_PCIE1_RST                49
 62 #define EN7581_CPU_TIMER_RST            50         62 #define EN7581_CPU_TIMER_RST            50
 63 #define EN7581_PCIE_HB_RST              51         63 #define EN7581_PCIE_HB_RST              51
 64 #define EN7581_XPON_MAC_RST             52         64 #define EN7581_XPON_MAC_RST             52
 65                                                    65 
 66 #endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROH     66 #endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
 67                                                    67 

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