1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (C) 2017 Impinj, Inc. 2 * Copyright (C) 2017 Impinj, Inc.
4 * 3 *
5 * Author: Andrey Smirnov <andrew.smirnov@gmai 4 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms and conditions of the GNU General Public License,
>> 8 * version 2, as published by the Free Software Foundation.
>> 9 *
>> 10 * This program is distributed in the hope it will be useful, but WITHOUT
>> 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> 13 * more details.
>> 14 *
>> 15 * You should have received a copy of the GNU General Public License
>> 16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
6 */ 17 */
7 18
8 #ifndef DT_BINDING_RESET_IMX7_H 19 #ifndef DT_BINDING_RESET_IMX7_H
9 #define DT_BINDING_RESET_IMX7_H 20 #define DT_BINDING_RESET_IMX7_H
10 21
11 #define IMX7_RESET_A7_CORE_POR_RESET0 0 22 #define IMX7_RESET_A7_CORE_POR_RESET0 0
12 #define IMX7_RESET_A7_CORE_POR_RESET1 1 23 #define IMX7_RESET_A7_CORE_POR_RESET1 1
13 #define IMX7_RESET_A7_CORE_RESET0 2 24 #define IMX7_RESET_A7_CORE_RESET0 2
14 #define IMX7_RESET_A7_CORE_RESET1 3 25 #define IMX7_RESET_A7_CORE_RESET1 3
15 #define IMX7_RESET_A7_DBG_RESET0 4 26 #define IMX7_RESET_A7_DBG_RESET0 4
16 #define IMX7_RESET_A7_DBG_RESET1 5 27 #define IMX7_RESET_A7_DBG_RESET1 5
17 #define IMX7_RESET_A7_ETM_RESET0 6 28 #define IMX7_RESET_A7_ETM_RESET0 6
18 #define IMX7_RESET_A7_ETM_RESET1 7 29 #define IMX7_RESET_A7_ETM_RESET1 7
19 #define IMX7_RESET_A7_SOC_DBG_RESET 8 30 #define IMX7_RESET_A7_SOC_DBG_RESET 8
20 #define IMX7_RESET_A7_L2RESET 9 31 #define IMX7_RESET_A7_L2RESET 9
21 #define IMX7_RESET_SW_M4C_RST 10 32 #define IMX7_RESET_SW_M4C_RST 10
22 #define IMX7_RESET_SW_M4P_RST 11 33 #define IMX7_RESET_SW_M4P_RST 11
23 #define IMX7_RESET_EIM_RST 12 34 #define IMX7_RESET_EIM_RST 12
24 #define IMX7_RESET_HSICPHY_PORT_RST 13 35 #define IMX7_RESET_HSICPHY_PORT_RST 13
25 #define IMX7_RESET_USBPHY1_POR 14 36 #define IMX7_RESET_USBPHY1_POR 14
26 #define IMX7_RESET_USBPHY1_PORT_RST 15 37 #define IMX7_RESET_USBPHY1_PORT_RST 15
27 #define IMX7_RESET_USBPHY2_POR 16 38 #define IMX7_RESET_USBPHY2_POR 16
28 #define IMX7_RESET_USBPHY2_PORT_RST 17 39 #define IMX7_RESET_USBPHY2_PORT_RST 17
29 #define IMX7_RESET_MIPI_PHY_MRST 18 40 #define IMX7_RESET_MIPI_PHY_MRST 18
30 #define IMX7_RESET_MIPI_PHY_SRST 19 41 #define IMX7_RESET_MIPI_PHY_SRST 19
31 42
32 /* 43 /*
33 * IMX7_RESET_PCIEPHY is a logical reset line 44 * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
34 * and PCIEPHY_G_RST 45 * and PCIEPHY_G_RST
35 */ 46 */
36 #define IMX7_RESET_PCIEPHY 20 47 #define IMX7_RESET_PCIEPHY 20
37 #define IMX7_RESET_PCIEPHY_PERST 21 48 #define IMX7_RESET_PCIEPHY_PERST 21
38 49
39 /* 50 /*
40 * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictl 51 * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
41 * can be used to inhibit PCIe LTTSM, so, in a 52 * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
42 * of as one 53 * of as one
43 */ 54 */
44 #define IMX7_RESET_PCIE_CTRL_APPS_EN 22 55 #define IMX7_RESET_PCIE_CTRL_APPS_EN 22
45 #define IMX7_RESET_DDRC_PRST 23 56 #define IMX7_RESET_DDRC_PRST 23
46 #define IMX7_RESET_DDRC_CORE_RST 24 57 #define IMX7_RESET_DDRC_CORE_RST 24
47 58
48 #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 !! 59 #define IMX7_RESET_NUM 25
49 <<
50 #define IMX7_RESET_NUM 26 <<
51 60
52 #endif 61 #endif
53 62
54 63
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