1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright (c) 2015, NVIDIA CORPORATION. Al 4 */ 5 6 #ifndef _ABI_MACH_T186_RESET_T186_H_ 7 #define _ABI_MACH_T186_RESET_T186_H_ 8 9 10 #define TEGRA186_RESET_ACTMON 11 #define TEGRA186_RESET_AFI 12 #define TEGRA186_RESET_CEC 13 #define TEGRA186_RESET_CSITE 14 #define TEGRA186_RESET_DP2 15 #define TEGRA186_RESET_DPAUX 16 #define TEGRA186_RESET_DSI 17 #define TEGRA186_RESET_DSIB 18 #define TEGRA186_RESET_DTV 19 #define TEGRA186_RESET_DVFS 20 #define TEGRA186_RESET_ENTROPY 21 #define TEGRA186_RESET_EXTPERIPH1 22 #define TEGRA186_RESET_EXTPERIPH2 23 #define TEGRA186_RESET_EXTPERIPH3 24 #define TEGRA186_RESET_GPU 25 #define TEGRA186_RESET_HDA 26 #define TEGRA186_RESET_HDA2CODEC_2X 27 #define TEGRA186_RESET_HDA2HDMICODEC 28 #define TEGRA186_RESET_HOST1X 29 #define TEGRA186_RESET_I2C1 30 #define TEGRA186_RESET_I2C2 31 #define TEGRA186_RESET_I2C3 32 #define TEGRA186_RESET_I2C4 33 #define TEGRA186_RESET_I2C5 34 #define TEGRA186_RESET_I2C6 35 #define TEGRA186_RESET_ISP 36 #define TEGRA186_RESET_KFUSE 37 #define TEGRA186_RESET_LA 38 #define TEGRA186_RESET_MIPI_CAL 39 #define TEGRA186_RESET_PCIE 40 #define TEGRA186_RESET_PCIEXCLK 41 #define TEGRA186_RESET_SATA 42 #define TEGRA186_RESET_SATACOLD 43 #define TEGRA186_RESET_SDMMC1 44 #define TEGRA186_RESET_SDMMC2 45 #define TEGRA186_RESET_SDMMC3 46 #define TEGRA186_RESET_SDMMC4 47 #define TEGRA186_RESET_SE 48 #define TEGRA186_RESET_SOC_THERM 49 #define TEGRA186_RESET_SOR0 50 #define TEGRA186_RESET_SPI1 51 #define TEGRA186_RESET_SPI2 52 #define TEGRA186_RESET_SPI3 53 #define TEGRA186_RESET_SPI4 54 #define TEGRA186_RESET_TMR 55 #define TEGRA186_RESET_TRIG_SYS 56 #define TEGRA186_RESET_TSEC 57 #define TEGRA186_RESET_UARTA 58 #define TEGRA186_RESET_UARTB 59 #define TEGRA186_RESET_UARTC 60 #define TEGRA186_RESET_UARTD 61 #define TEGRA186_RESET_VI 62 #define TEGRA186_RESET_VIC 63 #define TEGRA186_RESET_XUSB_DEV 64 #define TEGRA186_RESET_XUSB_HOST 65 #define TEGRA186_RESET_XUSB_PADCTL 66 #define TEGRA186_RESET_XUSB_SS 67 #define TEGRA186_RESET_AON_APB 68 #define TEGRA186_RESET_AXI_CBB 69 #define TEGRA186_RESET_BPMP_APB 70 #define TEGRA186_RESET_CAN1 71 #define TEGRA186_RESET_CAN2 72 #define TEGRA186_RESET_DMIC5 73 #define TEGRA186_RESET_DSIC 74 #define TEGRA186_RESET_DSID 75 #define TEGRA186_RESET_EMC_EMC 76 #define TEGRA186_RESET_EMC_MEM 77 #define TEGRA186_RESET_EMCSB_EMC 78 #define TEGRA186_RESET_EMCSB_MEM 79 #define TEGRA186_RESET_EQOS 80 #define TEGRA186_RESET_GPCDMA 81 #define TEGRA186_RESET_GPIO_CTL0 82 #define TEGRA186_RESET_GPIO_CTL1 83 #define TEGRA186_RESET_GPIO_CTL2 84 #define TEGRA186_RESET_GPIO_CTL3 85 #define TEGRA186_RESET_GPIO_CTL4 86 #define TEGRA186_RESET_GPIO_CTL5 87 #define TEGRA186_RESET_I2C10 88 #define TEGRA186_RESET_I2C12 89 #define TEGRA186_RESET_I2C13 90 #define TEGRA186_RESET_I2C14 91 #define TEGRA186_RESET_I2C7 92 #define TEGRA186_RESET_I2C8 93 #define TEGRA186_RESET_I2C9 94 #define TEGRA186_RESET_JTAG2AXI 95 #define TEGRA186_RESET_MPHY_IOBIST 96 #define TEGRA186_RESET_MPHY_L0_RX 97 #define TEGRA186_RESET_MPHY_L0_TX 98 #define TEGRA186_RESET_NVCSI 99 #define TEGRA186_RESET_NVDISPLAY0_HEAD0 100 #define TEGRA186_RESET_NVDISPLAY0_HEAD1 101 #define TEGRA186_RESET_NVDISPLAY0_HEAD2 102 #define TEGRA186_RESET_NVDISPLAY0_MISC 103 #define TEGRA186_RESET_NVDISPLAY0_WGRP0 104 #define TEGRA186_RESET_NVDISPLAY0_WGRP1 105 #define TEGRA186_RESET_NVDISPLAY0_WGRP2 106 #define TEGRA186_RESET_NVDISPLAY0_WGRP3 107 #define TEGRA186_RESET_NVDISPLAY0_WGRP4 108 #define TEGRA186_RESET_NVDISPLAY0_WGRP5 109 #define TEGRA186_RESET_PWM1 110 #define TEGRA186_RESET_PWM2 111 #define TEGRA186_RESET_PWM3 112 #define TEGRA186_RESET_PWM4 113 #define TEGRA186_RESET_PWM5 114 #define TEGRA186_RESET_PWM6 115 #define TEGRA186_RESET_PWM7 116 #define TEGRA186_RESET_PWM8 117 #define TEGRA186_RESET_SCE_APB 118 #define TEGRA186_RESET_SOR1 119 #define TEGRA186_RESET_TACH 120 #define TEGRA186_RESET_TSC 121 #define TEGRA186_RESET_UARTF 122 #define TEGRA186_RESET_UARTG 123 #define TEGRA186_RESET_UFSHC 124 #define TEGRA186_RESET_UFSHC_AXI_M 125 #define TEGRA186_RESET_UPHY 126 #define TEGRA186_RESET_ADSP 127 #define TEGRA186_RESET_ADSPDBG 128 #define TEGRA186_RESET_ADSPINTF 129 #define TEGRA186_RESET_ADSPNEON 130 #define TEGRA186_RESET_ADSPPERIPH 131 #define TEGRA186_RESET_ADSPSCU 132 #define TEGRA186_RESET_ADSPWDT 133 #define TEGRA186_RESET_APE 134 #define TEGRA186_RESET_DPAUX1 135 #define TEGRA186_RESET_NVDEC 136 #define TEGRA186_RESET_NVENC 137 #define TEGRA186_RESET_NVJPG 138 #define TEGRA186_RESET_PEX_USB_UPHY 139 #define TEGRA186_RESET_QSPI 140 #define TEGRA186_RESET_TSECB 141 #define TEGRA186_RESET_VI_I2C 142 #define TEGRA186_RESET_UARTE 143 #define TEGRA186_RESET_TOP_GTE 144 #define TEGRA186_RESET_SHSP 145 #define TEGRA186_RESET_PEX_USB_UPHY_L5 146 #define TEGRA186_RESET_PEX_USB_UPHY_L4 147 #define TEGRA186_RESET_PEX_USB_UPHY_L3 148 #define TEGRA186_RESET_PEX_USB_UPHY_L2 149 #define TEGRA186_RESET_PEX_USB_UPHY_L1 150 #define TEGRA186_RESET_PEX_USB_UPHY_L0 151 #define TEGRA186_RESET_PEX_USB_UPHY_PLL1 152 #define TEGRA186_RESET_PEX_USB_UPHY_PLL0 153 #define TEGRA186_RESET_TSCTNVI 154 #define TEGRA186_RESET_EXTPERIPH4 155 #define TEGRA186_RESET_DSIPADCTL 156 #define TEGRA186_RESET_AUD_MCLK 157 #define TEGRA186_RESET_MPHY_CLK_CTL 158 #define TEGRA186_RESET_MPHY_L1_RX 159 #define TEGRA186_RESET_MPHY_L1_TX 160 #define TEGRA186_RESET_UFSHC_LP 161 #define TEGRA186_RESET_BPMP_NIC 162 #define TEGRA186_RESET_BPMP_NSYSPORESET 163 #define TEGRA186_RESET_BPMP_NRESET 164 #define TEGRA186_RESET_BPMP_DBGRESETN 165 #define TEGRA186_RESET_BPMP_PRESETDBGN 166 #define TEGRA186_RESET_BPMP_PM 167 #define TEGRA186_RESET_BPMP_CVC 168 #define TEGRA186_RESET_BPMP_DMA 169 #define TEGRA186_RESET_BPMP_HSP 170 #define TEGRA186_RESET_TSCTNBPMP 171 #define TEGRA186_RESET_BPMP_TKE 172 #define TEGRA186_RESET_BPMP_GTE 173 #define TEGRA186_RESET_BPMP_PM_ACTMON 174 #define TEGRA186_RESET_AON_NIC 175 #define TEGRA186_RESET_AON_NSYSPORESET 176 #define TEGRA186_RESET_AON_NRESET 177 #define TEGRA186_RESET_AON_DBGRESETN 178 #define TEGRA186_RESET_AON_PRESETDBGN 179 #define TEGRA186_RESET_AON_ACTMON 180 #define TEGRA186_RESET_AOPM 181 #define TEGRA186_RESET_AOVC 182 #define TEGRA186_RESET_AON_DMA 183 #define TEGRA186_RESET_AON_GPIO 184 #define TEGRA186_RESET_AON_HSP 185 #define TEGRA186_RESET_TSCTNAON 186 #define TEGRA186_RESET_AON_TKE 187 #define TEGRA186_RESET_AON_GTE 188 #define TEGRA186_RESET_SCE_NIC 189 #define TEGRA186_RESET_SCE_NSYSPORESET 190 #define TEGRA186_RESET_SCE_NRESET 191 #define TEGRA186_RESET_SCE_DBGRESETN 192 #define TEGRA186_RESET_SCE_PRESETDBGN 193 #define TEGRA186_RESET_SCE_ACTMON 194 #define TEGRA186_RESET_SCE_PM 195 #define TEGRA186_RESET_SCE_DMA 196 #define TEGRA186_RESET_SCE_HSP 197 #define TEGRA186_RESET_TSCTNSCE 198 #define TEGRA186_RESET_SCE_TKE 199 #define TEGRA186_RESET_SCE_GTE 200 #define TEGRA186_RESET_SCE_CFG 201 #define TEGRA186_RESET_ADSP_ALL 202 /** @brief controls the power up/down sequence 203 #define TEGRA186_RESET_UFSHC_LP_SEQ 204 #define TEGRA186_RESET_SIZE 205 206 #endif 207
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