1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * Device Tree Generator version: 1.1 2 * Device Tree Generator version: 1.1
4 * 3 *
5 * (C) Copyright 2007-2008 Xilinx, Inc. 4 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek 5 * (C) Copyright 2007-2009 Michal Simek
7 * 6 *
8 * Michal SIMEK <monstr@monstr.eu> 7 * Michal SIMEK <monstr@monstr.eu>
9 * 8 *
>> 9 * This program is free software; you can redistribute it and/or
>> 10 * modify it under the terms of the GNU General Public License as
>> 11 * published by the Free Software Foundation; either version 2 of
>> 12 * the License, or (at your option) any later version.
>> 13 *
>> 14 * This program is distributed in the hope that it will be useful,
>> 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 17 * GNU General Public License for more details.
>> 18 *
>> 19 * You should have received a copy of the GNU General Public License
>> 20 * along with this program; if not, write to the Free Software
>> 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> 22 * MA 02111-1307 USA
>> 23 *
10 * CAUTION: This file is automatically generat 24 * CAUTION: This file is automatically generated by libgen.
11 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6 25 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
12 * 26 *
13 * XPS project directory: Xilinx-ML505-ll_tema 27 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
14 */ 28 */
15 29
16 /dts-v1/; 30 /dts-v1/;
17 / { 31 / {
18 #address-cells = <1>; 32 #address-cells = <1>;
19 #size-cells = <1>; 33 #size-cells = <1>;
20 compatible = "xlnx,microblaze"; 34 compatible = "xlnx,microblaze";
>> 35 hard-reset-gpios = <&LEDs_8Bit 2 1>;
21 model = "testing"; 36 model = "testing";
22 DDR2_SDRAM: memory@90000000 { 37 DDR2_SDRAM: memory@90000000 {
23 device_type = "memory"; 38 device_type = "memory";
24 reg = < 0x90000000 0x10000000 39 reg = < 0x90000000 0x10000000 >;
25 } ; 40 } ;
26 aliases { 41 aliases {
27 ethernet0 = &Hard_Ethernet_MAC 42 ethernet0 = &Hard_Ethernet_MAC;
28 serial0 = &RS232_Uart_1; 43 serial0 = &RS232_Uart_1;
29 } ; 44 } ;
30 chosen { 45 chosen {
31 bootargs = "console=ttyUL0,115 46 bootargs = "console=ttyUL0,115200 highres=on";
32 stdout-path = "/plb@0/serial@8 !! 47 linux,stdout-path = "/plb@0/serial@84000000";
33 } ; 48 } ;
34 cpus { 49 cpus {
35 #address-cells = <1>; 50 #address-cells = <1>;
36 #cpus = <0x1>; 51 #cpus = <0x1>;
37 #size-cells = <0>; 52 #size-cells = <0>;
38 microblaze_0: cpu@0 { 53 microblaze_0: cpu@0 {
39 clock-frequency = <125 54 clock-frequency = <125000000>;
40 compatible = "xlnx,mic 55 compatible = "xlnx,microblaze-7.10.d";
41 d-cache-baseaddr = <0x 56 d-cache-baseaddr = <0x90000000>;
42 d-cache-highaddr = <0x 57 d-cache-highaddr = <0x9fffffff>;
43 d-cache-line-size = <0 58 d-cache-line-size = <0x10>;
44 d-cache-size = <0x2000 59 d-cache-size = <0x2000>;
45 device_type = "cpu"; 60 device_type = "cpu";
46 i-cache-baseaddr = <0x 61 i-cache-baseaddr = <0x90000000>;
47 i-cache-highaddr = <0x 62 i-cache-highaddr = <0x9fffffff>;
48 i-cache-line-size = <0 63 i-cache-line-size = <0x10>;
49 i-cache-size = <0x2000 64 i-cache-size = <0x2000>;
50 model = "microblaze,7. 65 model = "microblaze,7.10.d";
51 reg = <0>; 66 reg = <0>;
52 timebase-frequency = < 67 timebase-frequency = <125000000>;
53 xlnx,addr-tag-bits = < 68 xlnx,addr-tag-bits = <0xf>;
54 xlnx,allow-dcache-wr = 69 xlnx,allow-dcache-wr = <0x1>;
55 xlnx,allow-icache-wr = 70 xlnx,allow-icache-wr = <0x1>;
56 xlnx,area-optimized = 71 xlnx,area-optimized = <0x0>;
57 xlnx,cache-byte-size = 72 xlnx,cache-byte-size = <0x2000>;
58 xlnx,d-lmb = <0x1>; 73 xlnx,d-lmb = <0x1>;
59 xlnx,d-opb = <0x0>; 74 xlnx,d-opb = <0x0>;
60 xlnx,d-plb = <0x1>; 75 xlnx,d-plb = <0x1>;
61 xlnx,data-size = <0x20 76 xlnx,data-size = <0x20>;
62 xlnx,dcache-addr-tag = 77 xlnx,dcache-addr-tag = <0xf>;
63 xlnx,dcache-always-use 78 xlnx,dcache-always-used = <0x1>;
64 xlnx,dcache-byte-size 79 xlnx,dcache-byte-size = <0x2000>;
65 xlnx,dcache-line-len = 80 xlnx,dcache-line-len = <0x4>;
66 xlnx,dcache-use-fsl = 81 xlnx,dcache-use-fsl = <0x1>;
67 xlnx,debug-enabled = < 82 xlnx,debug-enabled = <0x1>;
68 xlnx,div-zero-exceptio 83 xlnx,div-zero-exception = <0x1>;
69 xlnx,dopb-bus-exceptio 84 xlnx,dopb-bus-exception = <0x0>;
70 xlnx,dynamic-bus-sizin 85 xlnx,dynamic-bus-sizing = <0x1>;
71 xlnx,edge-is-positive 86 xlnx,edge-is-positive = <0x1>;
72 xlnx,family = "virtex5 87 xlnx,family = "virtex5";
73 xlnx,endianness = <0x1 88 xlnx,endianness = <0x1>;
74 xlnx,fpu-exception = < 89 xlnx,fpu-exception = <0x1>;
75 xlnx,fsl-data-size = < 90 xlnx,fsl-data-size = <0x20>;
76 xlnx,fsl-exception = < 91 xlnx,fsl-exception = <0x0>;
77 xlnx,fsl-links = <0x0> 92 xlnx,fsl-links = <0x0>;
78 xlnx,i-lmb = <0x1>; 93 xlnx,i-lmb = <0x1>;
79 xlnx,i-opb = <0x0>; 94 xlnx,i-opb = <0x0>;
80 xlnx,i-plb = <0x1>; 95 xlnx,i-plb = <0x1>;
81 xlnx,icache-always-use 96 xlnx,icache-always-used = <0x1>;
82 xlnx,icache-line-len = 97 xlnx,icache-line-len = <0x4>;
83 xlnx,icache-use-fsl = 98 xlnx,icache-use-fsl = <0x1>;
84 xlnx,ill-opcode-except 99 xlnx,ill-opcode-exception = <0x1>;
85 xlnx,instance = "micro 100 xlnx,instance = "microblaze_0";
86 xlnx,interconnect = <0 101 xlnx,interconnect = <0x1>;
87 xlnx,interrupt-is-edge 102 xlnx,interrupt-is-edge = <0x0>;
88 xlnx,iopb-bus-exceptio 103 xlnx,iopb-bus-exception = <0x0>;
89 xlnx,mmu-dtlb-size = < 104 xlnx,mmu-dtlb-size = <0x4>;
90 xlnx,mmu-itlb-size = < 105 xlnx,mmu-itlb-size = <0x2>;
91 xlnx,mmu-tlb-access = 106 xlnx,mmu-tlb-access = <0x3>;
92 xlnx,mmu-zones = <0x10 107 xlnx,mmu-zones = <0x10>;
93 xlnx,number-of-pc-brk 108 xlnx,number-of-pc-brk = <0x1>;
94 xlnx,number-of-rd-addr 109 xlnx,number-of-rd-addr-brk = <0x0>;
95 xlnx,number-of-wr-addr 110 xlnx,number-of-wr-addr-brk = <0x0>;
96 xlnx,opcode-0x0-illega 111 xlnx,opcode-0x0-illegal = <0x1>;
97 xlnx,pvr = <0x2>; 112 xlnx,pvr = <0x2>;
98 xlnx,pvr-user1 = <0x0> 113 xlnx,pvr-user1 = <0x0>;
99 xlnx,pvr-user2 = <0x0> 114 xlnx,pvr-user2 = <0x0>;
100 xlnx,reset-msr = <0x0> 115 xlnx,reset-msr = <0x0>;
101 xlnx,sco = <0x0>; 116 xlnx,sco = <0x0>;
102 xlnx,unaligned-excepti 117 xlnx,unaligned-exceptions = <0x1>;
103 xlnx,use-barrel = <0x1 118 xlnx,use-barrel = <0x1>;
104 xlnx,use-dcache = <0x1 119 xlnx,use-dcache = <0x1>;
105 xlnx,use-div = <0x1>; 120 xlnx,use-div = <0x1>;
106 xlnx,use-ext-brk = <0x 121 xlnx,use-ext-brk = <0x1>;
107 xlnx,use-ext-nm-brk = 122 xlnx,use-ext-nm-brk = <0x1>;
108 xlnx,use-extended-fsl- 123 xlnx,use-extended-fsl-instr = <0x0>;
109 xlnx,use-fpu = <0x2>; 124 xlnx,use-fpu = <0x2>;
110 xlnx,use-hw-mul = <0x2 125 xlnx,use-hw-mul = <0x2>;
111 xlnx,use-icache = <0x1 126 xlnx,use-icache = <0x1>;
112 xlnx,use-interrupt = < 127 xlnx,use-interrupt = <0x1>;
113 xlnx,use-mmu = <0x3>; 128 xlnx,use-mmu = <0x3>;
114 xlnx,use-msr-instr = < 129 xlnx,use-msr-instr = <0x1>;
115 xlnx,use-pcmp-instr = 130 xlnx,use-pcmp-instr = <0x1>;
116 } ; 131 } ;
117 } ; 132 } ;
118 mb_plb: plb@0 { 133 mb_plb: plb@0 {
119 #address-cells = <1>; 134 #address-cells = <1>;
120 #size-cells = <1>; 135 #size-cells = <1>;
121 compatible = "xlnx,plb-v46-1.0 136 compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
122 ranges ; 137 ranges ;
123 FLASH: flash@a0000000 { 138 FLASH: flash@a0000000 {
124 bank-width = <2>; 139 bank-width = <2>;
125 compatible = "xlnx,xps 140 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
126 reg = < 0xa0000000 0x2 141 reg = < 0xa0000000 0x2000000 >;
127 xlnx,family = "virtex5 142 xlnx,family = "virtex5";
128 xlnx,include-datawidth 143 xlnx,include-datawidth-matching-0 = <0x1>;
129 xlnx,include-datawidth 144 xlnx,include-datawidth-matching-1 = <0x0>;
130 xlnx,include-datawidth 145 xlnx,include-datawidth-matching-2 = <0x0>;
131 xlnx,include-datawidth 146 xlnx,include-datawidth-matching-3 = <0x0>;
132 xlnx,include-negedge-i 147 xlnx,include-negedge-ioregs = <0x0>;
133 xlnx,include-plb-ipif 148 xlnx,include-plb-ipif = <0x1>;
134 xlnx,include-wrbuf = < 149 xlnx,include-wrbuf = <0x1>;
135 xlnx,max-mem-width = < 150 xlnx,max-mem-width = <0x10>;
136 xlnx,mch-native-dwidth 151 xlnx,mch-native-dwidth = <0x20>;
137 xlnx,mch-plb-clk-perio 152 xlnx,mch-plb-clk-period-ps = <0x1f40>;
138 xlnx,mch-splb-awidth = 153 xlnx,mch-splb-awidth = <0x20>;
139 xlnx,mch0-accessbuf-de 154 xlnx,mch0-accessbuf-depth = <0x10>;
140 xlnx,mch0-protocol = < 155 xlnx,mch0-protocol = <0x0>;
141 xlnx,mch0-rddatabuf-de 156 xlnx,mch0-rddatabuf-depth = <0x10>;
142 xlnx,mch1-accessbuf-de 157 xlnx,mch1-accessbuf-depth = <0x10>;
143 xlnx,mch1-protocol = < 158 xlnx,mch1-protocol = <0x0>;
144 xlnx,mch1-rddatabuf-de 159 xlnx,mch1-rddatabuf-depth = <0x10>;
145 xlnx,mch2-accessbuf-de 160 xlnx,mch2-accessbuf-depth = <0x10>;
146 xlnx,mch2-protocol = < 161 xlnx,mch2-protocol = <0x0>;
147 xlnx,mch2-rddatabuf-de 162 xlnx,mch2-rddatabuf-depth = <0x10>;
148 xlnx,mch3-accessbuf-de 163 xlnx,mch3-accessbuf-depth = <0x10>;
149 xlnx,mch3-protocol = < 164 xlnx,mch3-protocol = <0x0>;
150 xlnx,mch3-rddatabuf-de 165 xlnx,mch3-rddatabuf-depth = <0x10>;
151 xlnx,mem0-width = <0x1 166 xlnx,mem0-width = <0x10>;
152 xlnx,mem1-width = <0x2 167 xlnx,mem1-width = <0x20>;
153 xlnx,mem2-width = <0x2 168 xlnx,mem2-width = <0x20>;
154 xlnx,mem3-width = <0x2 169 xlnx,mem3-width = <0x20>;
155 xlnx,num-banks-mem = < 170 xlnx,num-banks-mem = <0x1>;
156 xlnx,num-channels = <0 171 xlnx,num-channels = <0x0>;
157 xlnx,priority-mode = < 172 xlnx,priority-mode = <0x0>;
158 xlnx,synch-mem-0 = <0x 173 xlnx,synch-mem-0 = <0x0>;
159 xlnx,synch-mem-1 = <0x 174 xlnx,synch-mem-1 = <0x0>;
160 xlnx,synch-mem-2 = <0x 175 xlnx,synch-mem-2 = <0x0>;
161 xlnx,synch-mem-3 = <0x 176 xlnx,synch-mem-3 = <0x0>;
162 xlnx,synch-pipedelay-0 177 xlnx,synch-pipedelay-0 = <0x2>;
163 xlnx,synch-pipedelay-1 178 xlnx,synch-pipedelay-1 = <0x2>;
164 xlnx,synch-pipedelay-2 179 xlnx,synch-pipedelay-2 = <0x2>;
165 xlnx,synch-pipedelay-3 180 xlnx,synch-pipedelay-3 = <0x2>;
166 xlnx,tavdv-ps-mem-0 = 181 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
167 xlnx,tavdv-ps-mem-1 = 182 xlnx,tavdv-ps-mem-1 = <0x3a98>;
168 xlnx,tavdv-ps-mem-2 = 183 xlnx,tavdv-ps-mem-2 = <0x3a98>;
169 xlnx,tavdv-ps-mem-3 = 184 xlnx,tavdv-ps-mem-3 = <0x3a98>;
170 xlnx,tcedv-ps-mem-0 = 185 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
171 xlnx,tcedv-ps-mem-1 = 186 xlnx,tcedv-ps-mem-1 = <0x3a98>;
172 xlnx,tcedv-ps-mem-2 = 187 xlnx,tcedv-ps-mem-2 = <0x3a98>;
173 xlnx,tcedv-ps-mem-3 = 188 xlnx,tcedv-ps-mem-3 = <0x3a98>;
174 xlnx,thzce-ps-mem-0 = 189 xlnx,thzce-ps-mem-0 = <0x88b8>;
175 xlnx,thzce-ps-mem-1 = 190 xlnx,thzce-ps-mem-1 = <0x1b58>;
176 xlnx,thzce-ps-mem-2 = 191 xlnx,thzce-ps-mem-2 = <0x1b58>;
177 xlnx,thzce-ps-mem-3 = 192 xlnx,thzce-ps-mem-3 = <0x1b58>;
178 xlnx,thzoe-ps-mem-0 = 193 xlnx,thzoe-ps-mem-0 = <0x1b58>;
179 xlnx,thzoe-ps-mem-1 = 194 xlnx,thzoe-ps-mem-1 = <0x1b58>;
180 xlnx,thzoe-ps-mem-2 = 195 xlnx,thzoe-ps-mem-2 = <0x1b58>;
181 xlnx,thzoe-ps-mem-3 = 196 xlnx,thzoe-ps-mem-3 = <0x1b58>;
182 xlnx,tlzwe-ps-mem-0 = 197 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
183 xlnx,tlzwe-ps-mem-1 = 198 xlnx,tlzwe-ps-mem-1 = <0x0>;
184 xlnx,tlzwe-ps-mem-2 = 199 xlnx,tlzwe-ps-mem-2 = <0x0>;
185 xlnx,tlzwe-ps-mem-3 = 200 xlnx,tlzwe-ps-mem-3 = <0x0>;
186 xlnx,twc-ps-mem-0 = <0 201 xlnx,twc-ps-mem-0 = <0x2af8>;
187 xlnx,twc-ps-mem-1 = <0 202 xlnx,twc-ps-mem-1 = <0x3a98>;
188 xlnx,twc-ps-mem-2 = <0 203 xlnx,twc-ps-mem-2 = <0x3a98>;
189 xlnx,twc-ps-mem-3 = <0 204 xlnx,twc-ps-mem-3 = <0x3a98>;
190 xlnx,twp-ps-mem-0 = <0 205 xlnx,twp-ps-mem-0 = <0x11170>;
191 xlnx,twp-ps-mem-1 = <0 206 xlnx,twp-ps-mem-1 = <0x2ee0>;
192 xlnx,twp-ps-mem-2 = <0 207 xlnx,twp-ps-mem-2 = <0x2ee0>;
193 xlnx,twp-ps-mem-3 = <0 208 xlnx,twp-ps-mem-3 = <0x2ee0>;
194 xlnx,xcl0-linesize = < 209 xlnx,xcl0-linesize = <0x4>;
195 xlnx,xcl0-writexfer = 210 xlnx,xcl0-writexfer = <0x1>;
196 xlnx,xcl1-linesize = < 211 xlnx,xcl1-linesize = <0x4>;
197 xlnx,xcl1-writexfer = 212 xlnx,xcl1-writexfer = <0x1>;
198 xlnx,xcl2-linesize = < 213 xlnx,xcl2-linesize = <0x4>;
199 xlnx,xcl2-writexfer = 214 xlnx,xcl2-writexfer = <0x1>;
200 xlnx,xcl3-linesize = < 215 xlnx,xcl3-linesize = <0x4>;
201 xlnx,xcl3-writexfer = 216 xlnx,xcl3-writexfer = <0x1>;
202 } ; 217 } ;
203 Hard_Ethernet_MAC: xps-ll-tema 218 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
204 #address-cells = <1>; 219 #address-cells = <1>;
205 #size-cells = <1>; 220 #size-cells = <1>;
206 compatible = "xlnx,com 221 compatible = "xlnx,compound";
207 ranges ; 222 ranges ;
208 ethernet@81c00000 { 223 ethernet@81c00000 {
209 compatible = " 224 compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
210 interrupt-pare 225 interrupt-parent = <&xps_intc_0>;
211 interrupts = < 226 interrupts = < 5 2 >;
212 llink-connecte 227 llink-connected = <&PIM3>;
213 local-mac-addr 228 local-mac-address = [ 00 0a 35 00 00 00 ];
214 reg = < 0x81c0 229 reg = < 0x81c00000 0x40 >;
215 xlnx,bus2core- 230 xlnx,bus2core-clk-ratio = <0x1>;
216 xlnx,phy-type 231 xlnx,phy-type = <0x1>;
217 xlnx,phyaddr = 232 xlnx,phyaddr = <0x1>;
218 xlnx,rxcsum = 233 xlnx,rxcsum = <0x0>;
219 xlnx,rxfifo = 234 xlnx,rxfifo = <0x1000>;
220 xlnx,temac-typ 235 xlnx,temac-type = <0x0>;
221 xlnx,txcsum = 236 xlnx,txcsum = <0x0>;
222 xlnx,txfifo = 237 xlnx,txfifo = <0x1000>;
223 } ; 238 } ;
224 } ; 239 } ;
225 IIC_EEPROM: i2c@81600000 { 240 IIC_EEPROM: i2c@81600000 {
226 compatible = "xlnx,xps 241 compatible = "xlnx,xps-iic-2.00.a";
227 interrupt-parent = <&x 242 interrupt-parent = <&xps_intc_0>;
228 interrupts = < 6 2 >; 243 interrupts = < 6 2 >;
229 reg = < 0x81600000 0x1 244 reg = < 0x81600000 0x10000 >;
230 xlnx,clk-freq = <0x773 245 xlnx,clk-freq = <0x7735940>;
231 xlnx,family = "virtex5 246 xlnx,family = "virtex5";
232 xlnx,gpo-width = <0x1> 247 xlnx,gpo-width = <0x1>;
233 xlnx,iic-freq = <0x186 248 xlnx,iic-freq = <0x186a0>;
234 xlnx,scl-inertial-dela 249 xlnx,scl-inertial-delay = <0x0>;
235 xlnx,sda-inertial-dela 250 xlnx,sda-inertial-delay = <0x0>;
236 xlnx,ten-bit-adr = <0x 251 xlnx,ten-bit-adr = <0x0>;
237 } ; 252 } ;
238 LEDs_8Bit: gpio@81400000 { 253 LEDs_8Bit: gpio@81400000 {
239 compatible = "xlnx,xps 254 compatible = "xlnx,xps-gpio-1.00.a";
240 interrupt-parent = <&x 255 interrupt-parent = <&xps_intc_0>;
241 interrupts = < 7 2 >; 256 interrupts = < 7 2 >;
242 reg = < 0x81400000 0x1 257 reg = < 0x81400000 0x10000 >;
243 xlnx,all-inputs = <0x0 258 xlnx,all-inputs = <0x0>;
244 xlnx,all-inputs-2 = <0 259 xlnx,all-inputs-2 = <0x0>;
245 xlnx,dout-default = <0 260 xlnx,dout-default = <0x0>;
246 xlnx,dout-default-2 = 261 xlnx,dout-default-2 = <0x0>;
247 xlnx,family = "virtex5 262 xlnx,family = "virtex5";
248 xlnx,gpio-width = <0x8 263 xlnx,gpio-width = <0x8>;
249 xlnx,interrupt-present 264 xlnx,interrupt-present = <0x1>;
250 xlnx,is-bidir = <0x1>; 265 xlnx,is-bidir = <0x1>;
251 xlnx,is-bidir-2 = <0x1 266 xlnx,is-bidir-2 = <0x1>;
252 xlnx,is-dual = <0x0>; 267 xlnx,is-dual = <0x0>;
253 xlnx,tri-default = <0x 268 xlnx,tri-default = <0xffffffff>;
254 xlnx,tri-default-2 = < 269 xlnx,tri-default-2 = <0xffffffff>;
255 #gpio-cells = <2>; 270 #gpio-cells = <2>;
256 gpio-controller; 271 gpio-controller;
257 } ; 272 } ;
258 273
259 gpio-leds { 274 gpio-leds {
260 compatible = "gpio-led 275 compatible = "gpio-leds";
261 276
262 heartbeat { 277 heartbeat {
263 label = "Heart 278 label = "Heartbeat";
264 gpios = <&LEDs 279 gpios = <&LEDs_8Bit 4 1>;
265 linux,default- 280 linux,default-trigger = "heartbeat";
266 }; 281 };
267 282
268 yellow { 283 yellow {
269 label = "Yello 284 label = "Yellow";
270 gpios = <&LEDs 285 gpios = <&LEDs_8Bit 5 1>;
271 }; 286 };
272 287
273 red { 288 red {
274 label = "Red"; 289 label = "Red";
275 gpios = <&LEDs 290 gpios = <&LEDs_8Bit 6 1>;
276 }; 291 };
277 292
278 green { 293 green {
279 label = "Green 294 label = "Green";
280 gpios = <&LEDs 295 gpios = <&LEDs_8Bit 7 1>;
281 }; 296 };
282 } ; 297 } ;
283 <<
284 gpio-restart { <<
285 compatible = "gpio-res <<
286 /* <<
287 * FIXME: is this acti <<
288 * the current flag (1 <<
289 * delay measures are <<
290 * to datasheet or tri <<
291 */ <<
292 gpios = <&LEDs_8Bit 2 <<
293 active-delay = <100>; <<
294 inactive-delay = <10>; <<
295 wait-delay = <100>; <<
296 }; <<
297 <<
298 RS232_Uart_1: serial@84000000 298 RS232_Uart_1: serial@84000000 {
299 clock-frequency = <125 299 clock-frequency = <125000000>;
300 compatible = "xlnx,xps 300 compatible = "xlnx,xps-uartlite-1.00.a";
301 current-speed = <11520 301 current-speed = <115200>;
302 device_type = "serial" 302 device_type = "serial";
303 interrupt-parent = <&x 303 interrupt-parent = <&xps_intc_0>;
304 interrupts = < 8 0 >; 304 interrupts = < 8 0 >;
305 port-number = <0>; 305 port-number = <0>;
306 reg = < 0x84000000 0x1 306 reg = < 0x84000000 0x10000 >;
307 xlnx,baudrate = <0x1c2 307 xlnx,baudrate = <0x1c200>;
308 xlnx,data-bits = <0x8> 308 xlnx,data-bits = <0x8>;
309 xlnx,family = "virtex5 309 xlnx,family = "virtex5";
310 xlnx,odd-parity = <0x0 310 xlnx,odd-parity = <0x0>;
311 xlnx,use-parity = <0x0 311 xlnx,use-parity = <0x0>;
312 } ; 312 } ;
>> 313 SysACE_CompactFlash: sysace@83600000 {
>> 314 compatible = "xlnx,xps-sysace-1.00.a";
>> 315 interrupt-parent = <&xps_intc_0>;
>> 316 interrupts = < 4 2 >;
>> 317 reg = < 0x83600000 0x10000 >;
>> 318 xlnx,family = "virtex5";
>> 319 xlnx,mem-width = <0x10>;
>> 320 } ;
313 debug_module: debug@84400000 { 321 debug_module: debug@84400000 {
314 compatible = "xlnx,mdm 322 compatible = "xlnx,mdm-1.00.d";
315 reg = < 0x84400000 0x1 323 reg = < 0x84400000 0x10000 >;
316 xlnx,family = "virtex5 324 xlnx,family = "virtex5";
317 xlnx,interconnect = <0 325 xlnx,interconnect = <0x1>;
318 xlnx,jtag-chain = <0x2 326 xlnx,jtag-chain = <0x2>;
319 xlnx,mb-dbg-ports = <0 327 xlnx,mb-dbg-ports = <0x1>;
320 xlnx,uart-width = <0x8 328 xlnx,uart-width = <0x8>;
321 xlnx,use-uart = <0x1>; 329 xlnx,use-uart = <0x1>;
322 xlnx,write-fsl-ports = 330 xlnx,write-fsl-ports = <0x0>;
323 } ; 331 } ;
324 mpmc@90000000 { 332 mpmc@90000000 {
325 #address-cells = <1>; 333 #address-cells = <1>;
326 #size-cells = <1>; 334 #size-cells = <1>;
327 compatible = "xlnx,mpm 335 compatible = "xlnx,mpmc-4.02.a";
328 ranges ; 336 ranges ;
329 PIM3: sdma@84600180 { 337 PIM3: sdma@84600180 {
330 compatible = " 338 compatible = "xlnx,ll-dma-1.00.a";
331 interrupt-pare 339 interrupt-parent = <&xps_intc_0>;
332 interrupts = < 340 interrupts = < 2 2 1 2 >;
333 reg = < 0x8460 341 reg = < 0x84600180 0x80 >;
334 } ; 342 } ;
335 } ; 343 } ;
336 xps_intc_0: interrupt-controll 344 xps_intc_0: interrupt-controller@81800000 {
337 #interrupt-cells = <0x 345 #interrupt-cells = <0x2>;
338 compatible = "xlnx,xps 346 compatible = "xlnx,xps-intc-1.00.a";
339 interrupt-controller ; 347 interrupt-controller ;
340 reg = < 0x81800000 0x1 348 reg = < 0x81800000 0x10000 >;
341 xlnx,kind-of-intr = <0 349 xlnx,kind-of-intr = <0x100>;
342 xlnx,num-intr-inputs = 350 xlnx,num-intr-inputs = <0x9>;
343 } ; 351 } ;
344 xps_timer_1: timer@83c00000 { 352 xps_timer_1: timer@83c00000 {
345 compatible = "xlnx,xps 353 compatible = "xlnx,xps-timer-1.00.a";
346 interrupt-parent = <&x 354 interrupt-parent = <&xps_intc_0>;
347 interrupts = < 3 2 >; 355 interrupts = < 3 2 >;
348 reg = < 0x83c00000 0x1 356 reg = < 0x83c00000 0x10000 >;
349 xlnx,count-width = <0x 357 xlnx,count-width = <0x20>;
>> 358 xlnx,family = "virtex5";
>> 359 xlnx,gen0-assert = <0x1>;
>> 360 xlnx,gen1-assert = <0x1>;
350 xlnx,one-timer-only = 361 xlnx,one-timer-only = <0x0>;
>> 362 xlnx,trig0-assert = <0x1>;
>> 363 xlnx,trig1-assert = <0x1>;
351 } ; 364 } ;
352 } ; 365 } ;
353 } ; 366 } ;
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