1 // SPDX-License-Identifier: GPL-2.0 <<
2 <<
3 #include "dt-bindings/clock/bcm3368-clock.h" <<
4 <<
5 / { 1 / {
6 #address-cells = <1>; 2 #address-cells = <1>;
7 #size-cells = <1>; 3 #size-cells = <1>;
8 compatible = "brcm,bcm3368"; 4 compatible = "brcm,bcm3368";
9 5
10 cpus { 6 cpus {
11 #address-cells = <1>; 7 #address-cells = <1>;
12 #size-cells = <0>; 8 #size-cells = <0>;
13 9
14 mips-hpt-frequency = <15000000 10 mips-hpt-frequency = <150000000>;
15 11
16 cpu@0 { 12 cpu@0 {
17 compatible = "brcm,bmi 13 compatible = "brcm,bmips4350";
18 device_type = "cpu"; 14 device_type = "cpu";
19 reg = <0>; 15 reg = <0>;
20 }; 16 };
21 17
22 cpu@1 { 18 cpu@1 {
23 compatible = "brcm,bmi 19 compatible = "brcm,bmips4350";
24 device_type = "cpu"; 20 device_type = "cpu";
25 reg = <1>; 21 reg = <1>;
26 }; 22 };
27 }; 23 };
28 24
29 clocks { 25 clocks {
30 periph_clk: periph-clk { 26 periph_clk: periph-clk {
31 compatible = "fixed-cl 27 compatible = "fixed-clock";
32 #clock-cells = <0>; 28 #clock-cells = <0>;
33 clock-frequency = <500 29 clock-frequency = <50000000>;
34 }; 30 };
35 }; 31 };
36 32
37 aliases { 33 aliases {
38 serial0 = &uart0; 34 serial0 = &uart0;
39 serial1 = &uart1; 35 serial1 = &uart1;
40 }; 36 };
41 37
42 cpu_intc: interrupt-controller { 38 cpu_intc: interrupt-controller {
43 #address-cells = <0>; 39 #address-cells = <0>;
44 compatible = "mti,cpu-interrup 40 compatible = "mti,cpu-interrupt-controller";
45 41
46 interrupt-controller; 42 interrupt-controller;
47 #interrupt-cells = <1>; 43 #interrupt-cells = <1>;
48 }; 44 };
49 45
50 ubus { 46 ubus {
51 #address-cells = <1>; 47 #address-cells = <1>;
52 #size-cells = <1>; 48 #size-cells = <1>;
53 49
54 compatible = "simple-bus"; 50 compatible = "simple-bus";
55 ranges; 51 ranges;
56 52
57 clkctl: clock-controller@fff8c !! 53 periph_cntl: syscon@fff8c000 {
58 compatible = "brcm,bcm <<
59 reg = <0xfff8c004 0x4> <<
60 #clock-cells = <1>; <<
61 }; <<
62 <<
63 periph_cntl: syscon@fff8c008 { <<
64 compatible = "syscon"; 54 compatible = "syscon";
65 reg = <0xfff8c008 0x4> !! 55 reg = <0xfff8c000 0xc>;
66 native-endian; 56 native-endian;
67 }; 57 };
68 58
69 reboot: syscon-reboot@fff8c008 59 reboot: syscon-reboot@fff8c008 {
70 compatible = "syscon-r 60 compatible = "syscon-reboot";
71 regmap = <&periph_cntl 61 regmap = <&periph_cntl>;
72 offset = <0x0>; !! 62 offset = <0x8>;
73 mask = <0x1>; 63 mask = <0x1>;
74 }; 64 };
75 65
76 periph_intc: interrupt-control 66 periph_intc: interrupt-controller@fff8c00c {
77 compatible = "brcm,bcm 67 compatible = "brcm,bcm6345-l1-intc";
78 reg = <0xfff8c00c 0x8> 68 reg = <0xfff8c00c 0x8>;
79 69
80 interrupt-controller; 70 interrupt-controller;
81 #interrupt-cells = <1> 71 #interrupt-cells = <1>;
82 72
83 interrupt-parent = <&c 73 interrupt-parent = <&cpu_intc>;
84 interrupts = <2>; 74 interrupts = <2>;
85 }; 75 };
86 76
87 uart0: serial@fff8c100 { 77 uart0: serial@fff8c100 {
88 compatible = "brcm,bcm 78 compatible = "brcm,bcm6345-uart";
89 reg = <0xfff8c100 0x18 79 reg = <0xfff8c100 0x18>;
90 80
91 interrupt-parent = <&p 81 interrupt-parent = <&periph_intc>;
92 interrupts = <2>; 82 interrupts = <2>;
93 83
94 clocks = <&periph_clk> 84 clocks = <&periph_clk>;
95 clock-names = "refclk" <<
96 85
97 status = "disabled"; 86 status = "disabled";
98 }; 87 };
99 88
100 uart1: serial@fff8c120 { 89 uart1: serial@fff8c120 {
101 compatible = "brcm,bcm 90 compatible = "brcm,bcm6345-uart";
102 reg = <0xfff8c120 0x18 91 reg = <0xfff8c120 0x18>;
103 92
104 interrupt-parent = <&p 93 interrupt-parent = <&periph_intc>;
105 interrupts = <3>; 94 interrupts = <3>;
106 95
107 clocks = <&periph_clk> 96 clocks = <&periph_clk>;
108 clock-names = "refclk" <<
109 97
110 status = "disabled"; 98 status = "disabled";
111 }; 99 };
112 }; 100 };
113 }; 101 };
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