1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 <<
3 #include "dt-bindings/clock/bcm3368-clock.h" <<
4 <<
5 / { 2 / {
6 #address-cells = <1>; 3 #address-cells = <1>;
7 #size-cells = <1>; 4 #size-cells = <1>;
8 compatible = "brcm,bcm3368"; 5 compatible = "brcm,bcm3368";
9 6
10 cpus { 7 cpus {
11 #address-cells = <1>; 8 #address-cells = <1>;
12 #size-cells = <0>; 9 #size-cells = <0>;
13 10
14 mips-hpt-frequency = <15000000 11 mips-hpt-frequency = <150000000>;
15 12
16 cpu@0 { 13 cpu@0 {
17 compatible = "brcm,bmi 14 compatible = "brcm,bmips4350";
18 device_type = "cpu"; 15 device_type = "cpu";
19 reg = <0>; 16 reg = <0>;
20 }; 17 };
21 18
22 cpu@1 { 19 cpu@1 {
23 compatible = "brcm,bmi 20 compatible = "brcm,bmips4350";
24 device_type = "cpu"; 21 device_type = "cpu";
25 reg = <1>; 22 reg = <1>;
26 }; 23 };
27 }; 24 };
28 25
29 clocks { 26 clocks {
30 periph_clk: periph-clk { 27 periph_clk: periph-clk {
31 compatible = "fixed-cl 28 compatible = "fixed-clock";
32 #clock-cells = <0>; 29 #clock-cells = <0>;
33 clock-frequency = <500 30 clock-frequency = <50000000>;
34 }; 31 };
35 }; 32 };
36 33
37 aliases { 34 aliases {
38 serial0 = &uart0; 35 serial0 = &uart0;
39 serial1 = &uart1; 36 serial1 = &uart1;
40 }; 37 };
41 38
42 cpu_intc: interrupt-controller { 39 cpu_intc: interrupt-controller {
43 #address-cells = <0>; 40 #address-cells = <0>;
44 compatible = "mti,cpu-interrup 41 compatible = "mti,cpu-interrupt-controller";
45 42
46 interrupt-controller; 43 interrupt-controller;
47 #interrupt-cells = <1>; 44 #interrupt-cells = <1>;
48 }; 45 };
49 46
50 ubus { 47 ubus {
51 #address-cells = <1>; 48 #address-cells = <1>;
52 #size-cells = <1>; 49 #size-cells = <1>;
53 50
54 compatible = "simple-bus"; 51 compatible = "simple-bus";
55 ranges; 52 ranges;
56 53
57 clkctl: clock-controller@fff8c 54 clkctl: clock-controller@fff8c004 {
58 compatible = "brcm,bcm 55 compatible = "brcm,bcm3368-clocks";
59 reg = <0xfff8c004 0x4> 56 reg = <0xfff8c004 0x4>;
60 #clock-cells = <1>; 57 #clock-cells = <1>;
61 }; 58 };
62 59
63 periph_cntl: syscon@fff8c008 { 60 periph_cntl: syscon@fff8c008 {
64 compatible = "syscon"; 61 compatible = "syscon";
65 reg = <0xfff8c008 0x4> !! 62 reg = <0xfff8c000 0x4>;
66 native-endian; 63 native-endian;
67 }; 64 };
68 65
69 reboot: syscon-reboot@fff8c008 66 reboot: syscon-reboot@fff8c008 {
70 compatible = "syscon-r 67 compatible = "syscon-reboot";
71 regmap = <&periph_cntl 68 regmap = <&periph_cntl>;
72 offset = <0x0>; 69 offset = <0x0>;
73 mask = <0x1>; 70 mask = <0x1>;
74 }; 71 };
75 72
76 periph_intc: interrupt-control 73 periph_intc: interrupt-controller@fff8c00c {
77 compatible = "brcm,bcm 74 compatible = "brcm,bcm6345-l1-intc";
78 reg = <0xfff8c00c 0x8> 75 reg = <0xfff8c00c 0x8>;
79 76
80 interrupt-controller; 77 interrupt-controller;
81 #interrupt-cells = <1> 78 #interrupt-cells = <1>;
82 79
83 interrupt-parent = <&c 80 interrupt-parent = <&cpu_intc>;
84 interrupts = <2>; 81 interrupts = <2>;
85 }; 82 };
86 83
87 uart0: serial@fff8c100 { 84 uart0: serial@fff8c100 {
88 compatible = "brcm,bcm 85 compatible = "brcm,bcm6345-uart";
89 reg = <0xfff8c100 0x18 86 reg = <0xfff8c100 0x18>;
90 87
91 interrupt-parent = <&p 88 interrupt-parent = <&periph_intc>;
92 interrupts = <2>; 89 interrupts = <2>;
93 90
94 clocks = <&periph_clk> 91 clocks = <&periph_clk>;
95 clock-names = "refclk" 92 clock-names = "refclk";
96 93
97 status = "disabled"; 94 status = "disabled";
98 }; 95 };
99 96
100 uart1: serial@fff8c120 { 97 uart1: serial@fff8c120 {
101 compatible = "brcm,bcm 98 compatible = "brcm,bcm6345-uart";
102 reg = <0xfff8c120 0x18 99 reg = <0xfff8c120 0x18>;
103 100
104 interrupt-parent = <&p 101 interrupt-parent = <&periph_intc>;
105 interrupts = <3>; 102 interrupts = <3>;
106 103
107 clocks = <&periph_clk> 104 clocks = <&periph_clk>;
108 clock-names = "refclk" 105 clock-names = "refclk";
109 106
110 status = "disabled"; 107 status = "disabled";
111 }; 108 };
112 }; 109 };
113 }; 110 };
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