1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 2
3 #include "dt-bindings/clock/bcm6362-clock.h" 3 #include "dt-bindings/clock/bcm6362-clock.h"
4 #include "dt-bindings/reset/bcm6362-reset.h" 4 #include "dt-bindings/reset/bcm6362-reset.h"
5 #include "dt-bindings/soc/bcm6362-pm.h" 5 #include "dt-bindings/soc/bcm6362-pm.h"
6 6
7 / { 7 / {
8 #address-cells = <1>; 8 #address-cells = <1>;
9 #size-cells = <1>; 9 #size-cells = <1>;
10 compatible = "brcm,bcm6362"; 10 compatible = "brcm,bcm6362";
11 11
12 cpus { 12 cpus {
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <0>; 14 #size-cells = <0>;
15 15
16 mips-hpt-frequency = <20000000 16 mips-hpt-frequency = <200000000>;
17 17
18 cpu@0 { 18 cpu@0 {
19 compatible = "brcm,bmi 19 compatible = "brcm,bmips4350";
20 device_type = "cpu"; 20 device_type = "cpu";
21 reg = <0>; 21 reg = <0>;
22 }; 22 };
23 23
24 cpu@1 { 24 cpu@1 {
25 compatible = "brcm,bmi 25 compatible = "brcm,bmips4350";
26 device_type = "cpu"; 26 device_type = "cpu";
27 reg = <1>; 27 reg = <1>;
28 }; 28 };
29 }; 29 };
30 30
31 clocks { 31 clocks {
32 periph_osc: periph-osc { 32 periph_osc: periph-osc {
33 compatible = "fixed-cl 33 compatible = "fixed-clock";
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 clock-frequency = <500 35 clock-frequency = <50000000>;
36 clock-output-names = " 36 clock-output-names = "periph";
37 }; 37 };
38 38
39 hsspi_osc: hsspi-osc { 39 hsspi_osc: hsspi-osc {
40 compatible = "fixed-cl 40 compatible = "fixed-clock";
41 41
42 #clock-cells = <0>; 42 #clock-cells = <0>;
43 43
44 clock-frequency = <400 44 clock-frequency = <400000000>;
45 clock-output-names = " 45 clock-output-names = "hsspi_osc";
46 }; 46 };
47 }; 47 };
48 48
49 aliases { 49 aliases {
50 nflash = &nflash; 50 nflash = &nflash;
51 serial0 = &uart0; 51 serial0 = &uart0;
52 serial1 = &uart1; 52 serial1 = &uart1;
53 spi0 = &lsspi; 53 spi0 = &lsspi;
54 spi1 = &hsspi; 54 spi1 = &hsspi;
55 }; 55 };
56 56
57 cpu_intc: interrupt-controller { 57 cpu_intc: interrupt-controller {
58 #address-cells = <0>; 58 #address-cells = <0>;
59 compatible = "mti,cpu-interrup 59 compatible = "mti,cpu-interrupt-controller";
60 60
61 interrupt-controller; 61 interrupt-controller;
62 #interrupt-cells = <1>; 62 #interrupt-cells = <1>;
63 }; 63 };
64 64
65 ubus { 65 ubus {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <1>; 67 #size-cells = <1>;
68 68
69 compatible = "simple-bus"; 69 compatible = "simple-bus";
70 ranges; 70 ranges;
71 71
72 periph_clk: clock-controller@1 72 periph_clk: clock-controller@10000004 {
73 compatible = "brcm,bcm 73 compatible = "brcm,bcm6362-clocks";
74 reg = <0x10000004 0x4> 74 reg = <0x10000004 0x4>;
75 #clock-cells = <1>; 75 #clock-cells = <1>;
76 }; 76 };
77 77
78 pll_cntl: syscon@10000008 { 78 pll_cntl: syscon@10000008 {
79 compatible = "syscon"; 79 compatible = "syscon";
80 reg = <0x10000008 0x4> 80 reg = <0x10000008 0x4>;
81 native-endian; 81 native-endian;
82 82
83 reboot { 83 reboot {
84 compatible = " 84 compatible = "syscon-reboot";
85 offset = <0x0> 85 offset = <0x0>;
86 mask = <0x1>; 86 mask = <0x1>;
87 }; 87 };
88 }; 88 };
89 89
90 periph_rst: reset-controller@1 90 periph_rst: reset-controller@10000010 {
91 compatible = "brcm,bcm 91 compatible = "brcm,bcm6345-reset";
92 reg = <0x10000010 0x4> 92 reg = <0x10000010 0x4>;
93 #reset-cells = <1>; 93 #reset-cells = <1>;
94 }; 94 };
95 95
96 periph_intc: interrupt-control 96 periph_intc: interrupt-controller@10000020 {
97 compatible = "brcm,bcm 97 compatible = "brcm,bcm6345-l1-intc";
98 reg = <0x10000020 0x10 98 reg = <0x10000020 0x10>,
99 <0x10000030 0x10 99 <0x10000030 0x10>;
100 100
101 interrupt-controller; 101 interrupt-controller;
102 #interrupt-cells = <1> 102 #interrupt-cells = <1>;
103 103
104 interrupt-parent = <&c 104 interrupt-parent = <&cpu_intc>;
105 interrupts = <2>, <3>; 105 interrupts = <2>, <3>;
106 }; 106 };
107 107
108 wdt: watchdog@1000005c { 108 wdt: watchdog@1000005c {
109 compatible = "brcm,bcm 109 compatible = "brcm,bcm7038-wdt";
110 reg = <0x1000005c 0xc> 110 reg = <0x1000005c 0xc>;
111 111
112 clocks = <&periph_osc> 112 clocks = <&periph_osc>;
113 clock-names = "refclk" 113 clock-names = "refclk";
114 114
115 timeout-sec = <30>; 115 timeout-sec = <30>;
116 }; 116 };
117 117
118 uart0: serial@10000100 { 118 uart0: serial@10000100 {
119 compatible = "brcm,bcm 119 compatible = "brcm,bcm6345-uart";
120 reg = <0x10000100 0x18 120 reg = <0x10000100 0x18>;
121 121
122 interrupt-parent = <&p 122 interrupt-parent = <&periph_intc>;
123 interrupts = <3>; 123 interrupts = <3>;
124 124
125 clocks = <&periph_osc> 125 clocks = <&periph_osc>;
126 clock-names = "refclk" 126 clock-names = "refclk";
127 127
128 status = "disabled"; 128 status = "disabled";
129 }; 129 };
130 130
131 uart1: serial@10000120 { 131 uart1: serial@10000120 {
132 compatible = "brcm,bcm 132 compatible = "brcm,bcm6345-uart";
133 reg = <0x10000120 0x18 133 reg = <0x10000120 0x18>;
134 134
135 interrupt-parent = <&p 135 interrupt-parent = <&periph_intc>;
136 interrupts = <4>; 136 interrupts = <4>;
137 137
138 clocks = <&periph_osc> 138 clocks = <&periph_osc>;
139 clock-names = "refclk" 139 clock-names = "refclk";
140 140
141 status = "disabled"; 141 status = "disabled";
142 }; 142 };
143 143
144 nflash: nand@10000200 { 144 nflash: nand@10000200 {
145 #address-cells = <1>; 145 #address-cells = <1>;
146 #size-cells = <0>; 146 #size-cells = <0>;
147 compatible = "brcm,nan 147 compatible = "brcm,nand-bcm6368",
148 "brcm,brc 148 "brcm,brcmnand-v2.2",
149 "brcm,brc 149 "brcm,brcmnand";
150 reg = <0x10000200 0x18 150 reg = <0x10000200 0x180>,
151 <0x10000600 0x20 151 <0x10000600 0x200>,
152 <0x10000070 0x10 152 <0x10000070 0x10>;
153 reg-names = "nand", 153 reg-names = "nand",
154 "nand-cach 154 "nand-cache",
155 "nand-int- 155 "nand-int-base";
156 156
157 interrupt-parent = <&p 157 interrupt-parent = <&periph_intc>;
158 interrupts = <12>; 158 interrupts = <12>;
159 159
160 clocks = <&periph_clk 160 clocks = <&periph_clk BCM6362_CLK_NAND>;
161 clock-names = "nand"; 161 clock-names = "nand";
162 162
163 status = "disabled"; 163 status = "disabled";
164 }; 164 };
165 165
166 lsspi: spi@10000800 { 166 lsspi: spi@10000800 {
167 #address-cells = <1>; 167 #address-cells = <1>;
168 #size-cells = <0>; 168 #size-cells = <0>;
169 compatible = "brcm,bcm 169 compatible = "brcm,bcm6358-spi";
170 reg = <0x10000800 0x70 170 reg = <0x10000800 0x70c>;
171 171
172 interrupt-parent = <&p 172 interrupt-parent = <&periph_intc>;
173 interrupts = <2>; 173 interrupts = <2>;
174 174
175 clocks = <&periph_clk 175 clocks = <&periph_clk BCM6362_CLK_SPI>;
176 clock-names = "spi"; 176 clock-names = "spi";
177 177
178 resets = <&periph_rst 178 resets = <&periph_rst BCM6362_RST_SPI>;
179 reset-names = "spi"; 179 reset-names = "spi";
180 180
181 status = "disabled"; 181 status = "disabled";
182 }; 182 };
183 183
184 hsspi: spi@10001000 { 184 hsspi: spi@10001000 {
185 #address-cells = <1>; 185 #address-cells = <1>;
186 #size-cells = <0>; 186 #size-cells = <0>;
187 compatible = "brcm,bcm 187 compatible = "brcm,bcm6328-hsspi";
188 reg = <0x10001000 0x60 188 reg = <0x10001000 0x600>;
189 189
190 interrupt-parent = <&p 190 interrupt-parent = <&periph_intc>;
191 interrupts = <5>; 191 interrupts = <5>;
192 192
193 clocks = <&periph_clk 193 clocks = <&periph_clk BCM6362_CLK_HSSPI>,
194 <&hsspi_osc>; 194 <&hsspi_osc>;
195 clock-names = "hsspi", 195 clock-names = "hsspi",
196 "pll"; 196 "pll";
197 197
198 resets = <&periph_rst 198 resets = <&periph_rst BCM6362_RST_SPI>;
199 reset-names = "hsspi"; 199 reset-names = "hsspi";
200 200
201 status = "disabled"; 201 status = "disabled";
202 }; 202 };
203 203
204 periph_pwr: power-controller@1 204 periph_pwr: power-controller@10001848 {
205 compatible = "brcm,bcm 205 compatible = "brcm,bcm6362-power-controller";
206 reg = <0x10001848 0x4> 206 reg = <0x10001848 0x4>;
207 #power-domain-cells = 207 #power-domain-cells = <1>;
208 }; 208 };
209 209
210 leds0: led-controller@10001900 210 leds0: led-controller@10001900 {
211 #address-cells = <1>; 211 #address-cells = <1>;
212 #size-cells = <0>; 212 #size-cells = <0>;
213 compatible = "brcm,bcm 213 compatible = "brcm,bcm6328-leds";
214 reg = <0x10001900 0x24 214 reg = <0x10001900 0x24>;
215 215
216 status = "disabled"; 216 status = "disabled";
217 }; 217 };
218 218
219 ehci: usb@10002500 { 219 ehci: usb@10002500 {
220 compatible = "brcm,bcm 220 compatible = "brcm,bcm6362-ehci", "generic-ehci";
221 reg = <0x10002500 0x10 221 reg = <0x10002500 0x100>;
222 big-endian; 222 big-endian;
223 223
224 interrupt-parent = <&p 224 interrupt-parent = <&periph_intc>;
225 interrupts = <10>; 225 interrupts = <10>;
226 226
227 phys = <&usbh 0>; 227 phys = <&usbh 0>;
228 phy-names = "usb"; 228 phy-names = "usb";
229 229
230 status = "disabled"; 230 status = "disabled";
231 }; 231 };
232 232
233 ohci: usb@10002600 { 233 ohci: usb@10002600 {
234 compatible = "brcm,bcm 234 compatible = "brcm,bcm6362-ohci", "generic-ohci";
235 reg = <0x10002600 0x10 235 reg = <0x10002600 0x100>;
236 big-endian; 236 big-endian;
237 no-big-frame-no; 237 no-big-frame-no;
238 238
239 interrupt-parent = <&p 239 interrupt-parent = <&periph_intc>;
240 interrupts = <9>; 240 interrupts = <9>;
241 241
242 phys = <&usbh 0>; 242 phys = <&usbh 0>;
243 phy-names = "usb"; 243 phy-names = "usb";
244 244
245 status = "disabled"; 245 status = "disabled";
246 }; 246 };
247 247
248 usbh: usb-phy@10002700 { 248 usbh: usb-phy@10002700 {
249 compatible = "brcm,bcm 249 compatible = "brcm,bcm6362-usbh-phy";
250 reg = <0x10002700 0x38 250 reg = <0x10002700 0x38>;
251 251
252 #phy-cells = <1>; 252 #phy-cells = <1>;
253 253
254 clocks = <&periph_clk 254 clocks = <&periph_clk BCM6362_CLK_USBH>;
255 clock-names = "usbh"; 255 clock-names = "usbh";
256 256
257 power-domains = <&peri 257 power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>;
258 258
259 resets = <&periph_rst 259 resets = <&periph_rst BCM6362_RST_USBH>;
260 reset-names = "usbh"; 260 reset-names = "usbh";
261 261
262 status = "disabled"; 262 status = "disabled";
263 }; 263 };
264 }; 264 };
265 }; 265 };
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