1 // SPDX-License-Identifier: GPL-2.0 <<
2 / { 1 / {
3 #address-cells = <1>; 2 #address-cells = <1>;
4 #size-cells = <1>; 3 #size-cells = <1>;
5 compatible = "brcm,bcm7125"; 4 compatible = "brcm,bcm7125";
6 5
7 cpus { 6 cpus {
8 #address-cells = <1>; 7 #address-cells = <1>;
9 #size-cells = <0>; 8 #size-cells = <0>;
10 9
11 mips-hpt-frequency = <20250000 10 mips-hpt-frequency = <202500000>;
12 11
13 cpu@0 { 12 cpu@0 {
14 compatible = "brcm,bmi 13 compatible = "brcm,bmips4380";
15 device_type = "cpu"; 14 device_type = "cpu";
16 reg = <0>; 15 reg = <0>;
17 }; 16 };
18 17
19 cpu@1 { 18 cpu@1 {
20 compatible = "brcm,bmi 19 compatible = "brcm,bmips4380";
21 device_type = "cpu"; 20 device_type = "cpu";
22 reg = <1>; 21 reg = <1>;
23 }; 22 };
24 }; 23 };
25 24
26 aliases { 25 aliases {
27 uart0 = &uart0; 26 uart0 = &uart0;
28 }; 27 };
29 28
30 cpu_intc: interrupt-controller { 29 cpu_intc: interrupt-controller {
31 #address-cells = <0>; 30 #address-cells = <0>;
32 compatible = "mti,cpu-interrup 31 compatible = "mti,cpu-interrupt-controller";
33 32
34 interrupt-controller; 33 interrupt-controller;
35 #interrupt-cells = <1>; 34 #interrupt-cells = <1>;
36 }; 35 };
37 36
38 clocks { 37 clocks {
39 uart_clk: uart_clk { 38 uart_clk: uart_clk {
40 compatible = "fixed-cl 39 compatible = "fixed-clock";
41 #clock-cells = <0>; 40 #clock-cells = <0>;
42 clock-frequency = <810 41 clock-frequency = <81000000>;
43 }; 42 };
44 43
45 upg_clk: upg_clk { 44 upg_clk: upg_clk {
46 compatible = "fixed-cl 45 compatible = "fixed-clock";
47 #clock-cells = <0>; 46 #clock-cells = <0>;
48 clock-frequency = <270 47 clock-frequency = <27000000>;
49 }; 48 };
50 }; 49 };
51 50
52 rdb { 51 rdb {
53 #address-cells = <1>; 52 #address-cells = <1>;
54 #size-cells = <1>; 53 #size-cells = <1>;
55 54
56 compatible = "simple-bus"; 55 compatible = "simple-bus";
57 ranges = <0 0x10000000 0x01000 56 ranges = <0 0x10000000 0x01000000>;
58 57
59 periph_intc: interrupt-control 58 periph_intc: interrupt-controller@441400 {
60 compatible = "brcm,bcm 59 compatible = "brcm,bcm7038-l1-intc";
61 reg = <0x441400 0x30>, 60 reg = <0x441400 0x30>, <0x441600 0x30>;
62 61
63 interrupt-controller; 62 interrupt-controller;
64 #interrupt-cells = <1> 63 #interrupt-cells = <1>;
65 64
66 interrupt-parent = <&c 65 interrupt-parent = <&cpu_intc>;
67 interrupts = <2>, <3>; 66 interrupts = <2>, <3>;
68 }; 67 };
69 68
70 sun_l2_intc: interrupt-control 69 sun_l2_intc: interrupt-controller@401800 {
71 compatible = "brcm,l2- 70 compatible = "brcm,l2-intc";
72 reg = <0x401800 0x30>; 71 reg = <0x401800 0x30>;
73 interrupt-controller; 72 interrupt-controller;
74 #interrupt-cells = <1> 73 #interrupt-cells = <1>;
75 interrupt-parent = <&p 74 interrupt-parent = <&periph_intc>;
76 interrupts = <23>; 75 interrupts = <23>;
77 }; 76 };
78 77
79 gisb-arb@400000 { 78 gisb-arb@400000 {
80 compatible = "brcm,bcm 79 compatible = "brcm,bcm7400-gisb-arb";
81 reg = <0x400000 0xdc>; 80 reg = <0x400000 0xdc>;
82 native-endian; 81 native-endian;
83 interrupt-parent = <&s 82 interrupt-parent = <&sun_l2_intc>;
84 interrupts = <0>, <2>; 83 interrupts = <0>, <2>;
85 brcm,gisb-arb-master-m 84 brcm,gisb-arb-master-mask = <0x2f7>;
86 brcm,gisb-arb-master-n 85 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
87 86 "bsp_0", "rdc_0", "rptd_0",
88 87 "avd_0", "jtag_0";
89 }; 88 };
90 89
91 upg_irq0_intc: interrupt-contr 90 upg_irq0_intc: interrupt-controller@406780 {
92 compatible = "brcm,bcm 91 compatible = "brcm,bcm7120-l2-intc";
93 reg = <0x406780 0x8>; 92 reg = <0x406780 0x8>;
94 93
95 brcm,int-map-mask = <0 94 brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
96 brcm,int-fwd-mask = <0 95 brcm,int-fwd-mask = <0x70000>;
97 96
98 interrupt-controller; 97 interrupt-controller;
99 #interrupt-cells = <1> 98 #interrupt-cells = <1>;
100 99
101 interrupt-parent = <&p 100 interrupt-parent = <&periph_intc>;
102 interrupts = <18>, <19 101 interrupts = <18>, <19>, <20>;
103 interrupt-names = "upg 102 interrupt-names = "upg_main", "upg_bsc", "upg_spi";
104 }; 103 };
105 104
106 sun_top_ctrl: syscon@404000 { 105 sun_top_ctrl: syscon@404000 {
107 compatible = "brcm,bcm 106 compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
108 reg = <0x404000 0x60c> 107 reg = <0x404000 0x60c>;
109 native-endian; 108 native-endian;
110 }; 109 };
111 110
112 reboot { 111 reboot {
113 compatible = "brcm,bcm 112 compatible = "brcm,bcm7038-reboot";
114 syscon = <&sun_top_ctr 113 syscon = <&sun_top_ctrl 0x8 0x14>;
115 }; 114 };
116 115
117 uart0: serial@406b00 { 116 uart0: serial@406b00 {
118 compatible = "ns16550a 117 compatible = "ns16550a";
119 reg = <0x406b00 0x20>; 118 reg = <0x406b00 0x20>;
120 reg-io-width = <0x4>; 119 reg-io-width = <0x4>;
121 reg-shift = <0x2>; 120 reg-shift = <0x2>;
122 native-endian; 121 native-endian;
123 interrupt-parent = <&p 122 interrupt-parent = <&periph_intc>;
124 interrupts = <21>; 123 interrupts = <21>;
125 clocks = <&uart_clk>; 124 clocks = <&uart_clk>;
126 status = "disabled"; 125 status = "disabled";
127 }; 126 };
128 127
129 uart1: serial@406b40 { 128 uart1: serial@406b40 {
130 compatible = "ns16550a 129 compatible = "ns16550a";
131 reg = <0x406b40 0x20>; 130 reg = <0x406b40 0x20>;
132 reg-io-width = <0x4>; 131 reg-io-width = <0x4>;
133 reg-shift = <0x2>; 132 reg-shift = <0x2>;
134 native-endian; 133 native-endian;
135 interrupt-parent = <&p 134 interrupt-parent = <&periph_intc>;
136 interrupts = <64>; 135 interrupts = <64>;
137 clocks = <&uart_clk>; 136 clocks = <&uart_clk>;
138 status = "disabled"; 137 status = "disabled";
139 }; 138 };
140 139
141 uart2: serial@406b80 { 140 uart2: serial@406b80 {
142 compatible = "ns16550a 141 compatible = "ns16550a";
143 reg = <0x406b80 0x20>; 142 reg = <0x406b80 0x20>;
144 reg-io-width = <0x4>; 143 reg-io-width = <0x4>;
145 reg-shift = <0x2>; 144 reg-shift = <0x2>;
146 native-endian; 145 native-endian;
147 interrupt-parent = <&p 146 interrupt-parent = <&periph_intc>;
148 interrupts = <65>; 147 interrupts = <65>;
149 clocks = <&uart_clk>; 148 clocks = <&uart_clk>;
150 status = "disabled"; 149 status = "disabled";
151 }; 150 };
152 151
153 bsca: i2c@406200 { 152 bsca: i2c@406200 {
154 clock-frequency = <39000 153 clock-frequency = <390000>;
155 compatible = "brcm,brcms 154 compatible = "brcm,brcmstb-i2c";
156 interrupt-parent = <&upg 155 interrupt-parent = <&upg_irq0_intc>;
157 reg = <0x406200 0x58>; 156 reg = <0x406200 0x58>;
158 interrupts = <24>; 157 interrupts = <24>;
159 interrupt-names = "upg_b 158 interrupt-names = "upg_bsca";
160 status = "disabled"; 159 status = "disabled";
161 }; 160 };
162 161
163 bscb: i2c@406280 { 162 bscb: i2c@406280 {
164 clock-frequency = <39000 163 clock-frequency = <390000>;
165 compatible = "brcm,brcms 164 compatible = "brcm,brcmstb-i2c";
166 interrupt-parent = <&upg 165 interrupt-parent = <&upg_irq0_intc>;
167 reg = <0x406280 0x58>; 166 reg = <0x406280 0x58>;
168 interrupts = <25>; 167 interrupts = <25>;
169 interrupt-names = "upg_b 168 interrupt-names = "upg_bscb";
170 status = "disabled"; 169 status = "disabled";
171 }; 170 };
172 171
173 bscc: i2c@406300 { 172 bscc: i2c@406300 {
174 clock-frequency = <39000 173 clock-frequency = <390000>;
175 compatible = "brcm,brcms 174 compatible = "brcm,brcmstb-i2c";
176 interrupt-parent = <&upg 175 interrupt-parent = <&upg_irq0_intc>;
177 reg = <0x406300 0x58>; 176 reg = <0x406300 0x58>;
178 interrupts = <26>; 177 interrupts = <26>;
179 interrupt-names = "upg_b 178 interrupt-names = "upg_bscc";
180 status = "disabled"; 179 status = "disabled";
181 }; 180 };
182 181
183 bscd: i2c@406380 { 182 bscd: i2c@406380 {
184 clock-frequency = <39000 183 clock-frequency = <390000>;
185 compatible = "brcm,brcms 184 compatible = "brcm,brcmstb-i2c";
186 interrupt-parent = <&upg 185 interrupt-parent = <&upg_irq0_intc>;
187 reg = <0x406380 0x58>; 186 reg = <0x406380 0x58>;
188 interrupts = <27>; 187 interrupts = <27>;
189 interrupt-names = "upg_b 188 interrupt-names = "upg_bscd";
190 status = "disabled"; 189 status = "disabled";
191 }; 190 };
192 191
193 pwma: pwm@406580 { 192 pwma: pwm@406580 {
194 compatible = "brcm,bcm 193 compatible = "brcm,bcm7038-pwm";
195 reg = <0x406580 0x28>; 194 reg = <0x406580 0x28>;
196 #pwm-cells = <2>; 195 #pwm-cells = <2>;
197 clocks = <&upg_clk>; 196 clocks = <&upg_clk>;
198 status = "disabled"; <<
199 }; <<
200 <<
201 watchdog: watchdog@4067e8 { <<
202 clocks = <&upg_clk>; <<
203 compatible = "brcm,bcm <<
204 reg = <0x4067e8 0x14>; <<
205 status = "disabled"; 197 status = "disabled";
206 }; 198 };
207 199
208 upg_gio: gpio@406700 { 200 upg_gio: gpio@406700 {
209 compatible = "brcm,brc 201 compatible = "brcm,brcmstb-gpio";
210 reg = <0x406700 0x80>; 202 reg = <0x406700 0x80>;
211 #gpio-cells = <2>; 203 #gpio-cells = <2>;
212 #interrupt-cells = <2> 204 #interrupt-cells = <2>;
213 gpio-controller; 205 gpio-controller;
214 interrupt-controller; 206 interrupt-controller;
215 interrupt-parent = <&u 207 interrupt-parent = <&upg_irq0_intc>;
216 interrupts = <6>; 208 interrupts = <6>;
217 brcm,gpio-bank-widths 209 brcm,gpio-bank-widths = <32 32 32 18>;
218 }; 210 };
219 211
220 ehci0: usb@488300 { 212 ehci0: usb@488300 {
221 compatible = "brcm,bcm 213 compatible = "brcm,bcm7125-ehci", "generic-ehci";
222 reg = <0x488300 0x100> 214 reg = <0x488300 0x100>;
223 native-endian; 215 native-endian;
224 interrupt-parent = <&p 216 interrupt-parent = <&periph_intc>;
225 interrupts = <60>; 217 interrupts = <60>;
226 status = "disabled"; 218 status = "disabled";
227 }; 219 };
228 220
229 ohci0: usb@488400 { 221 ohci0: usb@488400 {
230 compatible = "brcm,bcm 222 compatible = "brcm,bcm7125-ohci", "generic-ohci";
231 reg = <0x488400 0x100> 223 reg = <0x488400 0x100>;
232 native-endian; 224 native-endian;
233 interrupt-parent = <&p 225 interrupt-parent = <&periph_intc>;
234 interrupts = <61>; 226 interrupts = <61>;
235 status = "disabled"; 227 status = "disabled";
236 }; 228 };
237 229
238 spi_l2_intc: interrupt-control 230 spi_l2_intc: interrupt-controller@411d00 {
239 compatible = "brcm,l2- 231 compatible = "brcm,l2-intc";
240 reg = <0x411d00 0x30>; 232 reg = <0x411d00 0x30>;
241 interrupt-controller; 233 interrupt-controller;
242 #interrupt-cells = <1> 234 #interrupt-cells = <1>;
243 interrupt-parent = <&p 235 interrupt-parent = <&periph_intc>;
244 interrupts = <79>; 236 interrupts = <79>;
245 }; 237 };
246 238
247 qspi: spi@443000 { 239 qspi: spi@443000 {
248 #address-cells = <0x1> 240 #address-cells = <0x1>;
249 #size-cells = <0x0>; 241 #size-cells = <0x0>;
250 compatible = "brcm,spi 242 compatible = "brcm,spi-bcm-qspi",
251 "brcm,spi 243 "brcm,spi-brcmstb-qspi";
252 clocks = <&upg_clk>; 244 clocks = <&upg_clk>;
253 reg = <0x440920 0x4 0x 245 reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
254 reg-names = "cs_reg", 246 reg-names = "cs_reg", "hif_mspi", "bspi";
255 interrupts = <0x0 0x1 247 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
256 interrupt-parent = <&s 248 interrupt-parent = <&spi_l2_intc>;
257 interrupt-names = "spi 249 interrupt-names = "spi_lr_fullness_reached",
258 "spi 250 "spi_lr_session_aborted",
259 "spi 251 "spi_lr_impatient",
260 "spi 252 "spi_lr_session_done",
261 "spi 253 "spi_lr_overread",
262 "msp 254 "mspi_done",
263 "msp 255 "mspi_halted";
264 status = "disabled"; 256 status = "disabled";
265 }; 257 };
266 258
267 mspi: spi@406400 { 259 mspi: spi@406400 {
268 #address-cells = <1>; 260 #address-cells = <1>;
269 #size-cells = <0>; 261 #size-cells = <0>;
270 compatible = "brcm,spi 262 compatible = "brcm,spi-bcm-qspi",
271 "brcm,spi 263 "brcm,spi-brcmstb-mspi";
272 clocks = <&upg_clk>; 264 clocks = <&upg_clk>;
273 reg = <0x406400 0x180> 265 reg = <0x406400 0x180>;
274 reg-names = "mspi"; 266 reg-names = "mspi";
275 interrupts = <0x14>; 267 interrupts = <0x14>;
276 interrupt-parent = <&u 268 interrupt-parent = <&upg_irq0_intc>;
277 interrupt-names = "msp 269 interrupt-names = "mspi_done";
278 status = "disabled"; 270 status = "disabled";
279 }; 271 };
280 }; 272 };
281 }; 273 };
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