1 // SPDX-License-Identifier: GPL-2.0
2 / {
3 #address-cells = <1>;
4 #size-cells = <1>;
5 compatible = "brcm,bcm7125";
6
7 cpus {
8 #address-cells = <1>;
9 #size-cells = <0>;
10
11 mips-hpt-frequency = <20250000
12
13 cpu@0 {
14 compatible = "brcm,bmi
15 device_type = "cpu";
16 reg = <0>;
17 };
18
19 cpu@1 {
20 compatible = "brcm,bmi
21 device_type = "cpu";
22 reg = <1>;
23 };
24 };
25
26 aliases {
27 uart0 = &uart0;
28 };
29
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrup
33
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 };
37
38 clocks {
39 uart_clk: uart_clk {
40 compatible = "fixed-cl
41 #clock-cells = <0>;
42 clock-frequency = <810
43 };
44
45 upg_clk: upg_clk {
46 compatible = "fixed-cl
47 #clock-cells = <0>;
48 clock-frequency = <270
49 };
50 };
51
52 rdb {
53 #address-cells = <1>;
54 #size-cells = <1>;
55
56 compatible = "simple-bus";
57 ranges = <0 0x10000000 0x01000
58
59 periph_intc: interrupt-control
60 compatible = "brcm,bcm
61 reg = <0x441400 0x30>,
62
63 interrupt-controller;
64 #interrupt-cells = <1>
65
66 interrupt-parent = <&c
67 interrupts = <2>, <3>;
68 };
69
70 sun_l2_intc: interrupt-control
71 compatible = "brcm,l2-
72 reg = <0x401800 0x30>;
73 interrupt-controller;
74 #interrupt-cells = <1>
75 interrupt-parent = <&p
76 interrupts = <23>;
77 };
78
79 gisb-arb@400000 {
80 compatible = "brcm,bcm
81 reg = <0x400000 0xdc>;
82 native-endian;
83 interrupt-parent = <&s
84 interrupts = <0>, <2>;
85 brcm,gisb-arb-master-m
86 brcm,gisb-arb-master-n
87
88
89 };
90
91 upg_irq0_intc: interrupt-contr
92 compatible = "brcm,bcm
93 reg = <0x406780 0x8>;
94
95 brcm,int-map-mask = <0
96 brcm,int-fwd-mask = <0
97
98 interrupt-controller;
99 #interrupt-cells = <1>
100
101 interrupt-parent = <&p
102 interrupts = <18>, <19
103 interrupt-names = "upg
104 };
105
106 sun_top_ctrl: syscon@404000 {
107 compatible = "brcm,bcm
108 reg = <0x404000 0x60c>
109 native-endian;
110 };
111
112 reboot {
113 compatible = "brcm,bcm
114 syscon = <&sun_top_ctr
115 };
116
117 uart0: serial@406b00 {
118 compatible = "ns16550a
119 reg = <0x406b00 0x20>;
120 reg-io-width = <0x4>;
121 reg-shift = <0x2>;
122 native-endian;
123 interrupt-parent = <&p
124 interrupts = <21>;
125 clocks = <&uart_clk>;
126 status = "disabled";
127 };
128
129 uart1: serial@406b40 {
130 compatible = "ns16550a
131 reg = <0x406b40 0x20>;
132 reg-io-width = <0x4>;
133 reg-shift = <0x2>;
134 native-endian;
135 interrupt-parent = <&p
136 interrupts = <64>;
137 clocks = <&uart_clk>;
138 status = "disabled";
139 };
140
141 uart2: serial@406b80 {
142 compatible = "ns16550a
143 reg = <0x406b80 0x20>;
144 reg-io-width = <0x4>;
145 reg-shift = <0x2>;
146 native-endian;
147 interrupt-parent = <&p
148 interrupts = <65>;
149 clocks = <&uart_clk>;
150 status = "disabled";
151 };
152
153 bsca: i2c@406200 {
154 clock-frequency = <39000
155 compatible = "brcm,brcms
156 interrupt-parent = <&upg
157 reg = <0x406200 0x58>;
158 interrupts = <24>;
159 interrupt-names = "upg_b
160 status = "disabled";
161 };
162
163 bscb: i2c@406280 {
164 clock-frequency = <39000
165 compatible = "brcm,brcms
166 interrupt-parent = <&upg
167 reg = <0x406280 0x58>;
168 interrupts = <25>;
169 interrupt-names = "upg_b
170 status = "disabled";
171 };
172
173 bscc: i2c@406300 {
174 clock-frequency = <39000
175 compatible = "brcm,brcms
176 interrupt-parent = <&upg
177 reg = <0x406300 0x58>;
178 interrupts = <26>;
179 interrupt-names = "upg_b
180 status = "disabled";
181 };
182
183 bscd: i2c@406380 {
184 clock-frequency = <39000
185 compatible = "brcm,brcms
186 interrupt-parent = <&upg
187 reg = <0x406380 0x58>;
188 interrupts = <27>;
189 interrupt-names = "upg_b
190 status = "disabled";
191 };
192
193 pwma: pwm@406580 {
194 compatible = "brcm,bcm
195 reg = <0x406580 0x28>;
196 #pwm-cells = <2>;
197 clocks = <&upg_clk>;
198 status = "disabled";
199 };
200
201 watchdog: watchdog@4067e8 {
202 clocks = <&upg_clk>;
203 compatible = "brcm,bcm
204 reg = <0x4067e8 0x14>;
205 status = "disabled";
206 };
207
208 upg_gio: gpio@406700 {
209 compatible = "brcm,brc
210 reg = <0x406700 0x80>;
211 #gpio-cells = <2>;
212 #interrupt-cells = <2>
213 gpio-controller;
214 interrupt-controller;
215 interrupt-parent = <&u
216 interrupts = <6>;
217 brcm,gpio-bank-widths
218 };
219
220 ehci0: usb@488300 {
221 compatible = "brcm,bcm
222 reg = <0x488300 0x100>
223 native-endian;
224 interrupt-parent = <&p
225 interrupts = <60>;
226 status = "disabled";
227 };
228
229 ohci0: usb@488400 {
230 compatible = "brcm,bcm
231 reg = <0x488400 0x100>
232 native-endian;
233 interrupt-parent = <&p
234 interrupts = <61>;
235 status = "disabled";
236 };
237
238 spi_l2_intc: interrupt-control
239 compatible = "brcm,l2-
240 reg = <0x411d00 0x30>;
241 interrupt-controller;
242 #interrupt-cells = <1>
243 interrupt-parent = <&p
244 interrupts = <79>;
245 };
246
247 qspi: spi@443000 {
248 #address-cells = <0x1>
249 #size-cells = <0x0>;
250 compatible = "brcm,spi
251 "brcm,spi
252 clocks = <&upg_clk>;
253 reg = <0x440920 0x4 0x
254 reg-names = "cs_reg",
255 interrupts = <0x0 0x1
256 interrupt-parent = <&s
257 interrupt-names = "spi
258 "spi
259 "spi
260 "spi
261 "spi
262 "msp
263 "msp
264 status = "disabled";
265 };
266
267 mspi: spi@406400 {
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "brcm,spi
271 "brcm,spi
272 clocks = <&upg_clk>;
273 reg = <0x406400 0x180>
274 reg-names = "mspi";
275 interrupts = <0x14>;
276 interrupt-parent = <&u
277 interrupt-names = "msp
278 status = "disabled";
279 };
280 };
281 };
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