1 // SPDX-License-Identifier: GPL-2.0
2 / {
3 #address-cells = <1>;
4 #size-cells = <1>;
5 compatible = "brcm,bcm7358";
6
7 cpus {
8 #address-cells = <1>;
9 #size-cells = <0>;
10
11 mips-hpt-frequency = <37500000
12
13 cpu@0 {
14 compatible = "brcm,bmi
15 device_type = "cpu";
16 reg = <0>;
17 };
18 };
19
20 aliases {
21 uart0 = &uart0;
22 };
23
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrup
27
28 interrupt-controller;
29 #interrupt-cells = <1>;
30 };
31
32 clocks {
33 uart_clk: uart_clk {
34 compatible = "fixed-cl
35 #clock-cells = <0>;
36 clock-frequency = <810
37 };
38
39 upg_clk: upg_clk {
40 compatible = "fixed-cl
41 #clock-cells = <0>;
42 clock-frequency = <270
43 };
44 };
45
46 rdb {
47 #address-cells = <1>;
48 #size-cells = <1>;
49
50 compatible = "simple-bus";
51 ranges = <0 0x10000000 0x01000
52
53 periph_intc: interrupt-control
54 compatible = "brcm,bcm
55 reg = <0x411400 0x30>;
56
57 interrupt-controller;
58 #interrupt-cells = <1>
59
60 interrupt-parent = <&c
61 interrupts = <2>;
62 };
63
64 sun_l2_intc: interrupt-control
65 compatible = "brcm,l2-
66 reg = <0x403000 0x30>;
67 interrupt-controller;
68 #interrupt-cells = <1>
69 interrupt-parent = <&p
70 interrupts = <48>;
71 };
72
73 gisb-arb@400000 {
74 compatible = "brcm,bcm
75 reg = <0x400000 0xdc>;
76 native-endian;
77 interrupt-parent = <&s
78 interrupts = <0>, <2>;
79 brcm,gisb-arb-master-m
80 brcm,gisb-arb-master-n
81
82
83 };
84
85 upg_irq0_intc: interrupt-contr
86 compatible = "brcm,bcm
87 reg = <0x406600 0x8>;
88
89 brcm,int-map-mask = <0
90 brcm,int-fwd-mask = <0
91
92 interrupt-controller;
93 #interrupt-cells = <1>
94
95 interrupt-parent = <&p
96 interrupts = <56>, <54
97 interrupt-names = "upg
98 };
99
100 upg_aon_irq0_intc: interrupt-c
101 compatible = "brcm,bcm
102 reg = <0x408b80 0x8>;
103
104 brcm,int-map-mask = <0
105 brcm,int-fwd-mask = <0
106 brcm,irq-can-wake;
107
108 interrupt-controller;
109 #interrupt-cells = <1>
110
111 interrupt-parent = <&p
112 interrupts = <57>, <55
113 interrupt-names = "upg
114 "upg
115 };
116
117 sun_top_ctrl: syscon@404000 {
118 compatible = "brcm,bcm
119 reg = <0x404000 0x51c>
120 native-endian;
121 };
122
123 reboot {
124 compatible = "brcm,brc
125 syscon = <&sun_top_ctr
126 };
127
128 uart0: serial@406800 {
129 compatible = "ns16550a
130 reg = <0x406800 0x20>;
131 reg-io-width = <0x4>;
132 reg-shift = <0x2>;
133 native-endian;
134 interrupt-parent = <&p
135 interrupts = <61>;
136 clocks = <&uart_clk>;
137 status = "disabled";
138 };
139
140 uart1: serial@406840 {
141 compatible = "ns16550a
142 reg = <0x406840 0x20>;
143 reg-io-width = <0x4>;
144 reg-shift = <0x2>;
145 native-endian;
146 interrupt-parent = <&p
147 interrupts = <62>;
148 clocks = <&uart_clk>;
149 status = "disabled";
150 };
151
152 uart2: serial@406880 {
153 compatible = "ns16550a
154 reg = <0x406880 0x20>;
155 reg-io-width = <0x4>;
156 reg-shift = <0x2>;
157 native-endian;
158 interrupt-parent = <&p
159 interrupts = <63>;
160 clocks = <&uart_clk>;
161 status = "disabled";
162 };
163
164 bsca: i2c@406200 {
165 clock-frequency = <39000
166 compatible = "brcm,brcms
167 interrupt-parent = <&upg
168 reg = <0x406200 0x58>;
169 interrupts = <24>;
170 interrupt-names = "upg_b
171 status = "disabled";
172 };
173
174 bscb: i2c@406280 {
175 clock-frequency = <39000
176 compatible = "brcm,brcms
177 interrupt-parent = <&upg
178 reg = <0x406280 0x58>;
179 interrupts = <25>;
180 interrupt-names = "upg_b
181 status = "disabled";
182 };
183
184 bscc: i2c@406300 {
185 clock-frequency = <39000
186 compatible = "brcm,brcms
187 interrupt-parent = <&upg
188 reg = <0x406300 0x58>;
189 interrupts = <26>;
190 interrupt-names = "upg_b
191 status = "disabled";
192 };
193
194 bscd: i2c@408980 {
195 clock-frequency = <39000
196 compatible = "brcm,brcms
197 interrupt-parent = <&upg
198 reg = <0x408980 0x58>;
199 interrupts = <27>;
200 interrupt-names = "upg_b
201 status = "disabled";
202 };
203
204 pwma: pwm@406400 {
205 compatible = "brcm,bcm
206 reg = <0x406400 0x28>;
207 #pwm-cells = <2>;
208 clocks = <&upg_clk>;
209 status = "disabled";
210 };
211
212 pwmb: pwm@406700 {
213 compatible = "brcm,bcm
214 reg = <0x406700 0x28>;
215 #pwm-cells = <2>;
216 clocks = <&upg_clk>;
217 status = "disabled";
218 };
219
220 watchdog: watchdog@4066a8 {
221 clocks = <&upg_clk>;
222 compatible = "brcm,bcm
223 reg = <0x4066a8 0x14>;
224 status = "disabled";
225 };
226
227 aon_pm_l2_intc: interrupt-cont
228 compatible = "brcm,l2-
229 reg = <0x408240 0x30>;
230 interrupt-controller;
231 #interrupt-cells = <1>
232 interrupt-parent = <&p
233 interrupts = <50>;
234 brcm,irq-can-wake;
235 };
236
237 upg_gio: gpio@406500 {
238 compatible = "brcm,brc
239 reg = <0x406500 0xa0>;
240 #gpio-cells = <2>;
241 #interrupt-cells = <2>
242 gpio-controller;
243 interrupt-controller;
244 interrupt-parent = <&u
245 interrupts = <6>;
246 brcm,gpio-bank-widths
247 };
248
249 upg_gio_aon: gpio@408c00 {
250 compatible = "brcm,brc
251 reg = <0x408c00 0x60>;
252 #gpio-cells = <2>;
253 #interrupt-cells = <2>
254 gpio-controller;
255 interrupt-controller;
256 interrupt-parent = <&u
257 interrupts = <6>;
258 interrupts-extended =
259
260 wakeup-source;
261 brcm,gpio-bank-widths
262 };
263
264 enet0: ethernet@430000 {
265 phy-mode = "internal";
266 phy-handle = <&phy1>;
267 mac-address = [ 00 10
268 compatible = "brcm,gen
269 #address-cells = <0x1>
270 #size-cells = <0x1>;
271 reg = <0x430000 0x4c8c
272 interrupts = <24>, <25
273 interrupt-parent = <&p
274 status = "disabled";
275
276 mdio@e14 {
277 compatible = "
278 #address-cells
279 #size-cells =
280 reg = <0xe14 0
281
282 phy1: ethernet
283 max-sp
284 reg =
285 compat
286
287 };
288 };
289 };
290
291 ehci0: usb@480300 {
292 compatible = "brcm,bcm
293 reg = <0x480300 0x100>
294 native-endian;
295 interrupt-parent = <&p
296 interrupts = <65>;
297 status = "disabled";
298 };
299
300 ohci0: usb@480400 {
301 compatible = "brcm,bcm
302 reg = <0x480400 0x100>
303 native-endian;
304 no-big-frame-no;
305 interrupt-parent = <&p
306 interrupts = <66>;
307 status = "disabled";
308 };
309
310 hif_l2_intc: interrupt-control
311 compatible = "brcm,l2-
312 reg = <0x411000 0x30>;
313 interrupt-controller;
314 #interrupt-cells = <1>
315 interrupt-parent = <&p
316 interrupts = <30>;
317 };
318
319 nand: nand@412800 {
320 compatible = "brcm,brc
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg-names = "nand";
324 reg = <0x412800 0x400>
325 interrupt-parent = <&h
326 interrupts = <24>;
327 status = "disabled";
328 };
329
330 spi_l2_intc: interrupt-control
331 compatible = "brcm,l2-
332 reg = <0x411d00 0x30>;
333 interrupt-controller;
334 #interrupt-cells = <1>
335 interrupt-parent = <&p
336 interrupts = <31>;
337 };
338
339 qspi: spi@413000 {
340 #address-cells = <0x1>
341 #size-cells = <0x0>;
342 compatible = "brcm,spi
343 "brcm,spi
344 clocks = <&upg_clk>;
345 reg = <0x410920 0x4 0x
346 reg-names = "cs_reg",
347 interrupts = <0x0 0x1
348 interrupt-parent = <&s
349 interrupt-names = "spi
350 "spi
351 "spi
352 "spi
353 "spi
354 "msp
355 "msp
356 status = "disabled";
357 };
358
359 mspi: spi@408a00 {
360 #address-cells = <1>;
361 #size-cells = <0>;
362 compatible = "brcm,spi
363 "brcm,spi
364 clocks = <&upg_clk>;
365 reg = <0x408a00 0x180>
366 reg-names = "mspi";
367 interrupts = <0x14>;
368 interrupt-parent = <&u
369 interrupt-names = "msp
370 status = "disabled";
371 };
372
373 waketimer: waketimer@408e80 {
374 compatible = "brcm,brc
375 reg = <0x408e80 0x14>;
376 interrupts = <0x3>;
377 interrupt-parent = <&a
378 interrupt-names = "tim
379 clocks = <&upg_clk>;
380 status = "disabled";
381 };
382 };
383 };
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