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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/mips/brcm/bcm7358.dtsi

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

Diff markup

Differences between /scripts/dtc/include-prefixes/mips/brcm/bcm7358.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/mips/brcm/bcm7358.dtsi (Version linux-6.1.116)


  1 // SPDX-License-Identifier: GPL-2.0                 1 // SPDX-License-Identifier: GPL-2.0
  2 / {                                                 2 / {
  3         #address-cells = <1>;                       3         #address-cells = <1>;
  4         #size-cells = <1>;                          4         #size-cells = <1>;
  5         compatible = "brcm,bcm7358";                5         compatible = "brcm,bcm7358";
  6                                                     6 
  7         cpus {                                      7         cpus {
  8                 #address-cells = <1>;               8                 #address-cells = <1>;
  9                 #size-cells = <0>;                  9                 #size-cells = <0>;
 10                                                    10 
 11                 mips-hpt-frequency = <37500000     11                 mips-hpt-frequency = <375000000>;
 12                                                    12 
 13                 cpu@0 {                            13                 cpu@0 {
 14                         compatible = "brcm,bmi     14                         compatible = "brcm,bmips3300";
 15                         device_type = "cpu";       15                         device_type = "cpu";
 16                         reg = <0>;                 16                         reg = <0>;
 17                 };                                 17                 };
 18         };                                         18         };
 19                                                    19 
 20         aliases {                                  20         aliases {
 21                 uart0 = &uart0;                    21                 uart0 = &uart0;
 22         };                                         22         };
 23                                                    23 
 24         cpu_intc: interrupt-controller {           24         cpu_intc: interrupt-controller {
 25                 #address-cells = <0>;              25                 #address-cells = <0>;
 26                 compatible = "mti,cpu-interrup     26                 compatible = "mti,cpu-interrupt-controller";
 27                                                    27 
 28                 interrupt-controller;              28                 interrupt-controller;
 29                 #interrupt-cells = <1>;            29                 #interrupt-cells = <1>;
 30         };                                         30         };
 31                                                    31 
 32         clocks {                                   32         clocks {
 33                 uart_clk: uart_clk {               33                 uart_clk: uart_clk {
 34                         compatible = "fixed-cl     34                         compatible = "fixed-clock";
 35                         #clock-cells = <0>;        35                         #clock-cells = <0>;
 36                         clock-frequency = <810     36                         clock-frequency = <81000000>;
 37                 };                                 37                 };
 38                                                    38 
 39                 upg_clk: upg_clk {                 39                 upg_clk: upg_clk {
 40                         compatible = "fixed-cl     40                         compatible = "fixed-clock";
 41                         #clock-cells = <0>;        41                         #clock-cells = <0>;
 42                         clock-frequency = <270     42                         clock-frequency = <27000000>;
 43                 };                                 43                 };
 44         };                                         44         };
 45                                                    45 
 46         rdb {                                      46         rdb {
 47                 #address-cells = <1>;              47                 #address-cells = <1>;
 48                 #size-cells = <1>;                 48                 #size-cells = <1>;
 49                                                    49 
 50                 compatible = "simple-bus";         50                 compatible = "simple-bus";
 51                 ranges = <0 0x10000000 0x01000     51                 ranges = <0 0x10000000 0x01000000>;
 52                                                    52 
 53                 periph_intc: interrupt-control     53                 periph_intc: interrupt-controller@411400 {
 54                         compatible = "brcm,bcm     54                         compatible = "brcm,bcm7038-l1-intc";
 55                         reg = <0x411400 0x30>;     55                         reg = <0x411400 0x30>;
 56                                                    56 
 57                         interrupt-controller;      57                         interrupt-controller;
 58                         #interrupt-cells = <1>     58                         #interrupt-cells = <1>;
 59                                                    59 
 60                         interrupt-parent = <&c     60                         interrupt-parent = <&cpu_intc>;
 61                         interrupts = <2>;          61                         interrupts = <2>;
 62                 };                                 62                 };
 63                                                    63 
 64                 sun_l2_intc: interrupt-control     64                 sun_l2_intc: interrupt-controller@403000 {
 65                         compatible = "brcm,l2-     65                         compatible = "brcm,l2-intc";
 66                         reg = <0x403000 0x30>;     66                         reg = <0x403000 0x30>;
 67                         interrupt-controller;      67                         interrupt-controller;
 68                         #interrupt-cells = <1>     68                         #interrupt-cells = <1>;
 69                         interrupt-parent = <&p     69                         interrupt-parent = <&periph_intc>;
 70                         interrupts = <48>;         70                         interrupts = <48>;
 71                 };                                 71                 };
 72                                                    72 
 73                 gisb-arb@400000 {                  73                 gisb-arb@400000 {
 74                         compatible = "brcm,bcm     74                         compatible = "brcm,bcm7400-gisb-arb";
 75                         reg = <0x400000 0xdc>;     75                         reg = <0x400000 0xdc>;
 76                         native-endian;             76                         native-endian;
 77                         interrupt-parent = <&s     77                         interrupt-parent = <&sun_l2_intc>;
 78                         interrupts = <0>, <2>;     78                         interrupts = <0>, <2>;
 79                         brcm,gisb-arb-master-m     79                         brcm,gisb-arb-master-mask = <0x2f3>;
 80                         brcm,gisb-arb-master-n     80                         brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
 81                                                    81                                                      "rdc_0", "raaga_0",
 82                                                    82                                                      "avd_0", "jtag_0";
 83                 };                                 83                 };
 84                                                    84 
 85                 upg_irq0_intc: interrupt-contr     85                 upg_irq0_intc: interrupt-controller@406600 {
 86                         compatible = "brcm,bcm     86                         compatible = "brcm,bcm7120-l2-intc";
 87                         reg = <0x406600 0x8>;      87                         reg = <0x406600 0x8>;
 88                                                    88 
 89                         brcm,int-map-mask = <0     89                         brcm,int-map-mask = <0x44>, <0x7000000>;
 90                         brcm,int-fwd-mask = <0     90                         brcm,int-fwd-mask = <0x70000>;
 91                                                    91 
 92                         interrupt-controller;      92                         interrupt-controller;
 93                         #interrupt-cells = <1>     93                         #interrupt-cells = <1>;
 94                                                    94 
 95                         interrupt-parent = <&p     95                         interrupt-parent = <&periph_intc>;
 96                         interrupts = <56>, <54     96                         interrupts = <56>, <54>;
 97                         interrupt-names = "upg     97                         interrupt-names = "upg_main", "upg_bsc";
 98                 };                                 98                 };
 99                                                    99 
100                 upg_aon_irq0_intc: interrupt-c    100                 upg_aon_irq0_intc: interrupt-controller@408b80 {
101                         compatible = "brcm,bcm    101                         compatible = "brcm,bcm7120-l2-intc";
102                         reg = <0x408b80 0x8>;     102                         reg = <0x408b80 0x8>;
103                                                   103 
104                         brcm,int-map-mask = <0    104                         brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
105                         brcm,int-fwd-mask = <0    105                         brcm,int-fwd-mask = <0>;
106                         brcm,irq-can-wake;        106                         brcm,irq-can-wake;
107                                                   107 
108                         interrupt-controller;     108                         interrupt-controller;
109                         #interrupt-cells = <1>    109                         #interrupt-cells = <1>;
110                                                   110 
111                         interrupt-parent = <&p    111                         interrupt-parent = <&periph_intc>;
112                         interrupts = <57>, <55    112                         interrupts = <57>, <55>, <59>;
113                         interrupt-names = "upg    113                         interrupt-names = "upg_main_aon", "upg_bsc_aon",
114                                           "upg    114                                           "upg_spi";
115                 };                                115                 };
116                                                   116 
117                 sun_top_ctrl: syscon@404000 {     117                 sun_top_ctrl: syscon@404000 {
118                         compatible = "brcm,bcm    118                         compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
119                         reg = <0x404000 0x51c>    119                         reg = <0x404000 0x51c>;
120                         native-endian;            120                         native-endian;
121                 };                                121                 };
122                                                   122 
123                 reboot {                          123                 reboot {
124                         compatible = "brcm,brc    124                         compatible = "brcm,brcmstb-reboot";
125                         syscon = <&sun_top_ctr    125                         syscon = <&sun_top_ctrl 0x304 0x308>;
126                 };                                126                 };
127                                                   127 
128                 uart0: serial@406800 {            128                 uart0: serial@406800 {
129                         compatible = "ns16550a    129                         compatible = "ns16550a";
130                         reg = <0x406800 0x20>;    130                         reg = <0x406800 0x20>;
131                         reg-io-width = <0x4>;     131                         reg-io-width = <0x4>;
132                         reg-shift = <0x2>;        132                         reg-shift = <0x2>;
133                         native-endian;            133                         native-endian;
134                         interrupt-parent = <&p    134                         interrupt-parent = <&periph_intc>;
135                         interrupts = <61>;        135                         interrupts = <61>;
136                         clocks = <&uart_clk>;     136                         clocks = <&uart_clk>;
137                         status = "disabled";      137                         status = "disabled";
138                 };                                138                 };
139                                                   139 
140                 uart1: serial@406840 {            140                 uart1: serial@406840 {
141                         compatible = "ns16550a    141                         compatible = "ns16550a";
142                         reg = <0x406840 0x20>;    142                         reg = <0x406840 0x20>;
143                         reg-io-width = <0x4>;     143                         reg-io-width = <0x4>;
144                         reg-shift = <0x2>;        144                         reg-shift = <0x2>;
145                         native-endian;            145                         native-endian;
146                         interrupt-parent = <&p    146                         interrupt-parent = <&periph_intc>;
147                         interrupts = <62>;        147                         interrupts = <62>;
148                         clocks = <&uart_clk>;     148                         clocks = <&uart_clk>;
149                         status = "disabled";      149                         status = "disabled";
150                 };                                150                 };
151                                                   151 
152                 uart2: serial@406880 {            152                 uart2: serial@406880 {
153                         compatible = "ns16550a    153                         compatible = "ns16550a";
154                         reg = <0x406880 0x20>;    154                         reg = <0x406880 0x20>;
155                         reg-io-width = <0x4>;     155                         reg-io-width = <0x4>;
156                         reg-shift = <0x2>;        156                         reg-shift = <0x2>;
157                         native-endian;            157                         native-endian;
158                         interrupt-parent = <&p    158                         interrupt-parent = <&periph_intc>;
159                         interrupts = <63>;        159                         interrupts = <63>;
160                         clocks = <&uart_clk>;     160                         clocks = <&uart_clk>;
161                         status = "disabled";      161                         status = "disabled";
162                 };                                162                 };
163                                                   163 
164                 bsca: i2c@406200 {                164                 bsca: i2c@406200 {
165                       clock-frequency = <39000    165                       clock-frequency = <390000>;
166                       compatible = "brcm,brcms    166                       compatible = "brcm,brcmstb-i2c";
167                       interrupt-parent = <&upg    167                       interrupt-parent = <&upg_irq0_intc>;
168                       reg = <0x406200 0x58>;      168                       reg = <0x406200 0x58>;
169                       interrupts = <24>;          169                       interrupts = <24>;
170                       interrupt-names = "upg_b    170                       interrupt-names = "upg_bsca";
171                       status = "disabled";        171                       status = "disabled";
172                 };                                172                 };
173                                                   173 
174                 bscb: i2c@406280 {                174                 bscb: i2c@406280 {
175                       clock-frequency = <39000    175                       clock-frequency = <390000>;
176                       compatible = "brcm,brcms    176                       compatible = "brcm,brcmstb-i2c";
177                       interrupt-parent = <&upg    177                       interrupt-parent = <&upg_irq0_intc>;
178                       reg = <0x406280 0x58>;      178                       reg = <0x406280 0x58>;
179                       interrupts = <25>;          179                       interrupts = <25>;
180                       interrupt-names = "upg_b    180                       interrupt-names = "upg_bscb";
181                       status = "disabled";        181                       status = "disabled";
182                 };                                182                 };
183                                                   183 
184                 bscc: i2c@406300 {                184                 bscc: i2c@406300 {
185                       clock-frequency = <39000    185                       clock-frequency = <390000>;
186                       compatible = "brcm,brcms    186                       compatible = "brcm,brcmstb-i2c";
187                       interrupt-parent = <&upg    187                       interrupt-parent = <&upg_irq0_intc>;
188                       reg = <0x406300 0x58>;      188                       reg = <0x406300 0x58>;
189                       interrupts = <26>;          189                       interrupts = <26>;
190                       interrupt-names = "upg_b    190                       interrupt-names = "upg_bscc";
191                       status = "disabled";        191                       status = "disabled";
192                 };                                192                 };
193                                                   193 
194                 bscd: i2c@408980 {                194                 bscd: i2c@408980 {
195                       clock-frequency = <39000    195                       clock-frequency = <390000>;
196                       compatible = "brcm,brcms    196                       compatible = "brcm,brcmstb-i2c";
197                       interrupt-parent = <&upg    197                       interrupt-parent = <&upg_aon_irq0_intc>;
198                       reg = <0x408980 0x58>;      198                       reg = <0x408980 0x58>;
199                       interrupts = <27>;          199                       interrupts = <27>;
200                       interrupt-names = "upg_b    200                       interrupt-names = "upg_bscd";
201                       status = "disabled";        201                       status = "disabled";
202                 };                                202                 };
203                                                   203 
204                 pwma: pwm@406400 {                204                 pwma: pwm@406400 {
205                         compatible = "brcm,bcm    205                         compatible = "brcm,bcm7038-pwm";
206                         reg = <0x406400 0x28>;    206                         reg = <0x406400 0x28>;
207                         #pwm-cells = <2>;         207                         #pwm-cells = <2>;
208                         clocks = <&upg_clk>;      208                         clocks = <&upg_clk>;
209                         status = "disabled";      209                         status = "disabled";
210                 };                                210                 };
211                                                   211 
212                 pwmb: pwm@406700 {                212                 pwmb: pwm@406700 {
213                         compatible = "brcm,bcm    213                         compatible = "brcm,bcm7038-pwm";
214                         reg = <0x406700 0x28>;    214                         reg = <0x406700 0x28>;
215                         #pwm-cells = <2>;         215                         #pwm-cells = <2>;
216                         clocks = <&upg_clk>;      216                         clocks = <&upg_clk>;
217                         status = "disabled";      217                         status = "disabled";
218                 };                                218                 };
219                                                   219 
220                 watchdog: watchdog@4066a8 {       220                 watchdog: watchdog@4066a8 {
221                         clocks = <&upg_clk>;      221                         clocks = <&upg_clk>;
222                         compatible = "brcm,bcm    222                         compatible = "brcm,bcm7038-wdt";
223                         reg = <0x4066a8 0x14>;    223                         reg = <0x4066a8 0x14>;
224                         status = "disabled";      224                         status = "disabled";
225                 };                                225                 };
226                                                   226 
227                 aon_pm_l2_intc: interrupt-cont    227                 aon_pm_l2_intc: interrupt-controller@408240 {
228                         compatible = "brcm,l2-    228                         compatible = "brcm,l2-intc";
229                         reg = <0x408240 0x30>;    229                         reg = <0x408240 0x30>;
230                         interrupt-controller;     230                         interrupt-controller;
231                         #interrupt-cells = <1>    231                         #interrupt-cells = <1>;
232                         interrupt-parent = <&p    232                         interrupt-parent = <&periph_intc>;
233                         interrupts = <50>;        233                         interrupts = <50>;
234                         brcm,irq-can-wake;        234                         brcm,irq-can-wake;
235                 };                                235                 };
236                                                   236 
237                 upg_gio: gpio@406500 {            237                 upg_gio: gpio@406500 {
238                         compatible = "brcm,brc    238                         compatible = "brcm,brcmstb-gpio";
239                         reg = <0x406500 0xa0>;    239                         reg = <0x406500 0xa0>;
240                         #gpio-cells = <2>;        240                         #gpio-cells = <2>;
241                         #interrupt-cells = <2>    241                         #interrupt-cells = <2>;
242                         gpio-controller;          242                         gpio-controller;
243                         interrupt-controller;     243                         interrupt-controller;
244                         interrupt-parent = <&u    244                         interrupt-parent = <&upg_irq0_intc>;
245                         interrupts = <6>;         245                         interrupts = <6>;
246                         brcm,gpio-bank-widths     246                         brcm,gpio-bank-widths = <32 32 32 29 4>;
247                 };                                247                 };
248                                                   248 
249                 upg_gio_aon: gpio@408c00 {        249                 upg_gio_aon: gpio@408c00 {
250                         compatible = "brcm,brc    250                         compatible = "brcm,brcmstb-gpio";
251                         reg = <0x408c00 0x60>;    251                         reg = <0x408c00 0x60>;
252                         #gpio-cells = <2>;        252                         #gpio-cells = <2>;
253                         #interrupt-cells = <2>    253                         #interrupt-cells = <2>;
254                         gpio-controller;          254                         gpio-controller;
255                         interrupt-controller;     255                         interrupt-controller;
256                         interrupt-parent = <&u    256                         interrupt-parent = <&upg_aon_irq0_intc>;
257                         interrupts = <6>;         257                         interrupts = <6>;
258                         interrupts-extended =     258                         interrupts-extended = <&upg_aon_irq0_intc 6>,
259                                                   259                                               <&aon_pm_l2_intc 5>;
260                         wakeup-source;            260                         wakeup-source;
261                         brcm,gpio-bank-widths     261                         brcm,gpio-bank-widths = <21 32 2>;
262                 };                                262                 };
263                                                   263 
264                 enet0: ethernet@430000 {          264                 enet0: ethernet@430000 {
265                         phy-mode = "internal";    265                         phy-mode = "internal";
266                         phy-handle = <&phy1>;     266                         phy-handle = <&phy1>;
267                         mac-address = [ 00 10     267                         mac-address = [ 00 10 18 36 23 1a ];
268                         compatible = "brcm,gen    268                         compatible = "brcm,genet-v2";
269                         #address-cells = <0x1>    269                         #address-cells = <0x1>;
270                         #size-cells = <0x1>;      270                         #size-cells = <0x1>;
271                         reg = <0x430000 0x4c8c    271                         reg = <0x430000 0x4c8c>;
272                         interrupts = <24>, <25    272                         interrupts = <24>, <25>;
273                         interrupt-parent = <&p    273                         interrupt-parent = <&periph_intc>;
274                         status = "disabled";      274                         status = "disabled";
275                                                   275 
276                         mdio@e14 {                276                         mdio@e14 {
277                                 compatible = "    277                                 compatible = "brcm,genet-mdio-v2";
278                                 #address-cells    278                                 #address-cells = <0x1>;
279                                 #size-cells =     279                                 #size-cells = <0x0>;
280                                 reg = <0xe14 0    280                                 reg = <0xe14 0x8>;
281                                                   281 
282                                 phy1: ethernet    282                                 phy1: ethernet-phy@1 {
283                                         max-sp    283                                         max-speed = <100>;
284                                         reg =     284                                         reg = <0x1>;
285                                         compat    285                                         compatible = "brcm,40nm-ephy",
286                                                   286                                                 "ethernet-phy-ieee802.3-c22";
287                                 };                287                                 };
288                         };                        288                         };
289                 };                                289                 };
290                                                   290 
291                 ehci0: usb@480300 {               291                 ehci0: usb@480300 {
292                         compatible = "brcm,bcm    292                         compatible = "brcm,bcm7358-ehci", "generic-ehci";
293                         reg = <0x480300 0x100>    293                         reg = <0x480300 0x100>;
294                         native-endian;            294                         native-endian;
295                         interrupt-parent = <&p    295                         interrupt-parent = <&periph_intc>;
296                         interrupts = <65>;        296                         interrupts = <65>;
297                         status = "disabled";      297                         status = "disabled";
298                 };                                298                 };
299                                                   299 
300                 ohci0: usb@480400 {               300                 ohci0: usb@480400 {
301                         compatible = "brcm,bcm    301                         compatible = "brcm,bcm7358-ohci", "generic-ohci";
302                         reg = <0x480400 0x100>    302                         reg = <0x480400 0x100>;
303                         native-endian;            303                         native-endian;
304                         no-big-frame-no;          304                         no-big-frame-no;
305                         interrupt-parent = <&p    305                         interrupt-parent = <&periph_intc>;
306                         interrupts = <66>;        306                         interrupts = <66>;
307                         status = "disabled";      307                         status = "disabled";
308                 };                                308                 };
309                                                   309 
310                 hif_l2_intc: interrupt-control    310                 hif_l2_intc: interrupt-controller@411000 {
311                         compatible = "brcm,l2-    311                         compatible = "brcm,l2-intc";
312                         reg = <0x411000 0x30>;    312                         reg = <0x411000 0x30>;
313                         interrupt-controller;     313                         interrupt-controller;
314                         #interrupt-cells = <1>    314                         #interrupt-cells = <1>;
315                         interrupt-parent = <&p    315                         interrupt-parent = <&periph_intc>;
316                         interrupts = <30>;        316                         interrupts = <30>;
317                 };                                317                 };
318                                                   318 
319                 nand: nand@412800 {               319                 nand: nand@412800 {
320                         compatible = "brcm,brc    320                         compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
321                         #address-cells = <1>;     321                         #address-cells = <1>;
322                         #size-cells = <0>;        322                         #size-cells = <0>;
323                         reg-names = "nand";       323                         reg-names = "nand";
324                         reg = <0x412800 0x400>    324                         reg = <0x412800 0x400>;
325                         interrupt-parent = <&h    325                         interrupt-parent = <&hif_l2_intc>;
326                         interrupts = <24>;        326                         interrupts = <24>;
327                         status = "disabled";      327                         status = "disabled";
328                 };                                328                 };
329                                                   329 
330                 spi_l2_intc: interrupt-control    330                 spi_l2_intc: interrupt-controller@411d00 {
331                         compatible = "brcm,l2-    331                         compatible = "brcm,l2-intc";
332                         reg = <0x411d00 0x30>;    332                         reg = <0x411d00 0x30>;
333                         interrupt-controller;     333                         interrupt-controller;
334                         #interrupt-cells = <1>    334                         #interrupt-cells = <1>;
335                         interrupt-parent = <&p    335                         interrupt-parent = <&periph_intc>;
336                         interrupts = <31>;        336                         interrupts = <31>;
337                 };                                337                 };
338                                                   338 
339                 qspi: spi@413000 {                339                 qspi: spi@413000 {
340                         #address-cells = <0x1>    340                         #address-cells = <0x1>;
341                         #size-cells = <0x0>;      341                         #size-cells = <0x0>;
342                         compatible = "brcm,spi    342                         compatible = "brcm,spi-bcm-qspi",
343                                      "brcm,spi    343                                      "brcm,spi-brcmstb-qspi";
344                         clocks = <&upg_clk>;      344                         clocks = <&upg_clk>;
345                         reg = <0x410920 0x4 0x    345                         reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
346                         reg-names = "cs_reg",     346                         reg-names = "cs_reg", "hif_mspi", "bspi";
347                         interrupts = <0x0 0x1     347                         interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
348                         interrupt-parent = <&s    348                         interrupt-parent = <&spi_l2_intc>;
349                         interrupt-names = "spi    349                         interrupt-names = "spi_lr_fullness_reached",
350                                           "spi    350                                           "spi_lr_session_aborted",
351                                           "spi    351                                           "spi_lr_impatient",
352                                           "spi    352                                           "spi_lr_session_done",
353                                           "spi    353                                           "spi_lr_overread",
354                                           "msp    354                                           "mspi_done",
355                                           "msp    355                                           "mspi_halted";
356                         status = "disabled";      356                         status = "disabled";
357                 };                                357                 };
358                                                   358 
359                 mspi: spi@408a00 {                359                 mspi: spi@408a00 {
360                         #address-cells = <1>;     360                         #address-cells = <1>;
361                         #size-cells = <0>;        361                         #size-cells = <0>;
362                         compatible = "brcm,spi    362                         compatible = "brcm,spi-bcm-qspi",
363                                      "brcm,spi    363                                      "brcm,spi-brcmstb-mspi";
364                         clocks = <&upg_clk>;      364                         clocks = <&upg_clk>;
365                         reg = <0x408a00 0x180>    365                         reg = <0x408a00 0x180>;
366                         reg-names = "mspi";       366                         reg-names = "mspi";
367                         interrupts = <0x14>;      367                         interrupts = <0x14>;
368                         interrupt-parent = <&u    368                         interrupt-parent = <&upg_aon_irq0_intc>;
369                         interrupt-names = "msp    369                         interrupt-names = "mspi_done";
370                         status = "disabled";      370                         status = "disabled";
371                 };                                371                 };
372                                                   372 
373                 waketimer: waketimer@408e80 {     373                 waketimer: waketimer@408e80 {
374                         compatible = "brcm,brc    374                         compatible = "brcm,brcmstb-waketimer";
375                         reg = <0x408e80 0x14>;    375                         reg = <0x408e80 0x14>;
376                         interrupts = <0x3>;       376                         interrupts = <0x3>;
377                         interrupt-parent = <&a    377                         interrupt-parent = <&aon_pm_l2_intc>;
378                         interrupt-names = "tim    378                         interrupt-names = "timer";
379                         clocks = <&upg_clk>;      379                         clocks = <&upg_clk>;
380                         status = "disabled";      380                         status = "disabled";
381                 };                                381                 };
382         };                                        382         };
383 };                                                383 };
                                                      

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