1 // SPDX-License-Identifier: GPL-2.0 <<
2 / { 1 / {
3 #address-cells = <1>; 2 #address-cells = <1>;
4 #size-cells = <1>; 3 #size-cells = <1>;
5 compatible = "brcm,bcm7425"; 4 compatible = "brcm,bcm7425";
6 5
7 cpus { 6 cpus {
8 #address-cells = <1>; 7 #address-cells = <1>;
9 #size-cells = <0>; 8 #size-cells = <0>;
10 9
11 mips-hpt-frequency = <16312500 10 mips-hpt-frequency = <163125000>;
12 11
13 cpu@0 { 12 cpu@0 {
14 compatible = "brcm,bmi 13 compatible = "brcm,bmips5000";
15 device_type = "cpu"; 14 device_type = "cpu";
16 reg = <0>; 15 reg = <0>;
17 }; 16 };
18 17
19 cpu@1 { 18 cpu@1 {
20 compatible = "brcm,bmi 19 compatible = "brcm,bmips5000";
21 device_type = "cpu"; 20 device_type = "cpu";
22 reg = <1>; 21 reg = <1>;
23 }; 22 };
24 }; 23 };
25 24
26 aliases { 25 aliases {
27 uart0 = &uart0; 26 uart0 = &uart0;
28 }; 27 };
29 28
30 cpu_intc: interrupt-controller { 29 cpu_intc: interrupt-controller {
31 #address-cells = <0>; 30 #address-cells = <0>;
32 compatible = "mti,cpu-interrup 31 compatible = "mti,cpu-interrupt-controller";
33 32
34 interrupt-controller; 33 interrupt-controller;
35 #interrupt-cells = <1>; 34 #interrupt-cells = <1>;
36 }; 35 };
37 36
38 clocks { 37 clocks {
39 uart_clk: uart_clk { 38 uart_clk: uart_clk {
40 compatible = "fixed-cl 39 compatible = "fixed-clock";
41 #clock-cells = <0>; 40 #clock-cells = <0>;
42 clock-frequency = <810 41 clock-frequency = <81000000>;
43 }; 42 };
44 43
45 upg_clk: upg_clk { 44 upg_clk: upg_clk {
46 compatible = "fixed-cl 45 compatible = "fixed-clock";
47 #clock-cells = <0>; 46 #clock-cells = <0>;
48 clock-frequency = <270 47 clock-frequency = <27000000>;
49 }; 48 };
50 }; 49 };
51 50
52 rdb { 51 rdb {
53 #address-cells = <1>; 52 #address-cells = <1>;
54 #size-cells = <1>; 53 #size-cells = <1>;
55 54
56 compatible = "simple-bus"; 55 compatible = "simple-bus";
57 ranges = <0 0x10000000 0x01000 56 ranges = <0 0x10000000 0x01000000>;
58 57
59 periph_intc: interrupt-control 58 periph_intc: interrupt-controller@41a400 {
60 compatible = "brcm,bcm 59 compatible = "brcm,bcm7038-l1-intc";
61 reg = <0x41a400 0x30>, 60 reg = <0x41a400 0x30>, <0x41a600 0x30>;
62 61
63 interrupt-controller; 62 interrupt-controller;
64 #interrupt-cells = <1> 63 #interrupt-cells = <1>;
65 64
66 interrupt-parent = <&c 65 interrupt-parent = <&cpu_intc>;
67 interrupts = <2>, <3>; 66 interrupts = <2>, <3>;
68 }; 67 };
69 68
70 sun_l2_intc: interrupt-control 69 sun_l2_intc: interrupt-controller@403000 {
71 compatible = "brcm,l2- 70 compatible = "brcm,l2-intc";
72 reg = <0x403000 0x30>; 71 reg = <0x403000 0x30>;
73 interrupt-controller; 72 interrupt-controller;
74 #interrupt-cells = <1> 73 #interrupt-cells = <1>;
75 interrupt-parent = <&p 74 interrupt-parent = <&periph_intc>;
76 interrupts = <47>; 75 interrupts = <47>;
77 }; 76 };
78 77
79 gisb-arb@400000 { 78 gisb-arb@400000 {
80 compatible = "brcm,bcm 79 compatible = "brcm,bcm7400-gisb-arb";
81 reg = <0x400000 0xdc>; 80 reg = <0x400000 0xdc>;
82 native-endian; 81 native-endian;
83 interrupt-parent = <&s 82 interrupt-parent = <&sun_l2_intc>;
84 interrupts = <0>, <2>; 83 interrupts = <0>, <2>;
85 brcm,gisb-arb-master-m 84 brcm,gisb-arb-master-mask = <0x177b>;
86 brcm,gisb-arb-master-n 85 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
87 86 "bsp_0", "rdc_0",
88 87 "raaga_0", "avd_1",
89 88 "jtag_0", "svd_0",
90 89 "vice_0";
91 }; 90 };
92 91
93 upg_irq0_intc: interrupt-contr 92 upg_irq0_intc: interrupt-controller@406780 {
94 compatible = "brcm,bcm 93 compatible = "brcm,bcm7120-l2-intc";
95 reg = <0x406780 0x8>; 94 reg = <0x406780 0x8>;
96 95
97 brcm,int-map-mask = <0 96 brcm,int-map-mask = <0x44>, <0x7000000>;
98 brcm,int-fwd-mask = <0 97 brcm,int-fwd-mask = <0x70000>;
99 98
100 interrupt-controller; 99 interrupt-controller;
101 #interrupt-cells = <1> 100 #interrupt-cells = <1>;
102 101
103 interrupt-parent = <&p 102 interrupt-parent = <&periph_intc>;
104 interrupts = <55>, <53 103 interrupts = <55>, <53>;
105 interrupt-names = "upg 104 interrupt-names = "upg_main", "upg_bsc";
106 }; 105 };
107 106
108 upg_aon_irq0_intc: interrupt-c 107 upg_aon_irq0_intc: interrupt-controller@409480 {
109 compatible = "brcm,bcm 108 compatible = "brcm,bcm7120-l2-intc";
110 reg = <0x409480 0x8>; 109 reg = <0x409480 0x8>;
111 110
112 brcm,int-map-mask = <0 111 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
113 brcm,int-fwd-mask = <0 112 brcm,int-fwd-mask = <0>;
114 brcm,irq-can-wake; 113 brcm,irq-can-wake;
115 114
116 interrupt-controller; 115 interrupt-controller;
117 #interrupt-cells = <1> 116 #interrupt-cells = <1>;
118 117
119 interrupt-parent = <&p 118 interrupt-parent = <&periph_intc>;
120 interrupts = <56>, <54 119 interrupts = <56>, <54>, <59>;
121 interrupt-names = "upg 120 interrupt-names = "upg_main_aon", "upg_bsc_aon",
122 "upg 121 "upg_spi";
123 }; 122 };
124 123
125 sun_top_ctrl: syscon@404000 { 124 sun_top_ctrl: syscon@404000 {
126 compatible = "brcm,bcm 125 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
127 reg = <0x404000 0x51c> 126 reg = <0x404000 0x51c>;
128 native-endian; 127 native-endian;
129 }; 128 };
130 129
131 reboot { 130 reboot {
132 compatible = "brcm,brc 131 compatible = "brcm,brcmstb-reboot";
133 syscon = <&sun_top_ctr 132 syscon = <&sun_top_ctrl 0x304 0x308>;
134 }; 133 };
135 134
136 uart0: serial@406b00 { 135 uart0: serial@406b00 {
137 compatible = "ns16550a 136 compatible = "ns16550a";
138 reg = <0x406b00 0x20>; 137 reg = <0x406b00 0x20>;
139 reg-io-width = <0x4>; 138 reg-io-width = <0x4>;
140 reg-shift = <0x2>; 139 reg-shift = <0x2>;
141 interrupt-parent = <&p 140 interrupt-parent = <&periph_intc>;
142 interrupts = <61>; 141 interrupts = <61>;
143 clocks = <&uart_clk>; 142 clocks = <&uart_clk>;
144 status = "disabled"; 143 status = "disabled";
145 }; 144 };
146 145
147 uart1: serial@406b40 { 146 uart1: serial@406b40 {
148 compatible = "ns16550a 147 compatible = "ns16550a";
149 reg = <0x406b40 0x20>; 148 reg = <0x406b40 0x20>;
150 reg-io-width = <0x4>; 149 reg-io-width = <0x4>;
151 reg-shift = <0x2>; 150 reg-shift = <0x2>;
152 interrupt-parent = <&p 151 interrupt-parent = <&periph_intc>;
153 interrupts = <62>; 152 interrupts = <62>;
154 clocks = <&uart_clk>; 153 clocks = <&uart_clk>;
155 status = "disabled"; 154 status = "disabled";
156 }; 155 };
157 156
158 uart2: serial@406b80 { 157 uart2: serial@406b80 {
159 compatible = "ns16550a 158 compatible = "ns16550a";
160 reg = <0x406b80 0x20>; 159 reg = <0x406b80 0x20>;
161 reg-io-width = <0x4>; 160 reg-io-width = <0x4>;
162 reg-shift = <0x2>; 161 reg-shift = <0x2>;
163 interrupt-parent = <&p 162 interrupt-parent = <&periph_intc>;
164 interrupts = <63>; 163 interrupts = <63>;
165 clocks = <&uart_clk>; 164 clocks = <&uart_clk>;
166 status = "disabled"; 165 status = "disabled";
167 }; 166 };
168 167
169 bsca: i2c@409180 { 168 bsca: i2c@409180 {
170 clock-frequency = <39000 169 clock-frequency = <390000>;
171 compatible = "brcm,brcms 170 compatible = "brcm,brcmstb-i2c";
172 interrupt-parent = <&upg 171 interrupt-parent = <&upg_aon_irq0_intc>;
173 reg = <0x409180 0x58>; 172 reg = <0x409180 0x58>;
174 interrupts = <27>; 173 interrupts = <27>;
175 interrupt-names = "upg_b 174 interrupt-names = "upg_bsca";
176 status = "disabled"; 175 status = "disabled";
177 }; 176 };
178 177
179 bscb: i2c@409400 { 178 bscb: i2c@409400 {
180 clock-frequency = <39000 179 clock-frequency = <390000>;
181 compatible = "brcm,brcms 180 compatible = "brcm,brcmstb-i2c";
182 interrupt-parent = <&upg 181 interrupt-parent = <&upg_aon_irq0_intc>;
183 reg = <0x409400 0x58>; 182 reg = <0x409400 0x58>;
184 interrupts = <28>; 183 interrupts = <28>;
185 interrupt-names = "upg_b 184 interrupt-names = "upg_bscb";
186 status = "disabled"; 185 status = "disabled";
187 }; 186 };
188 187
189 bscc: i2c@406200 { 188 bscc: i2c@406200 {
190 clock-frequency = <39000 189 clock-frequency = <390000>;
191 compatible = "brcm,brcms 190 compatible = "brcm,brcmstb-i2c";
192 interrupt-parent = <&upg 191 interrupt-parent = <&upg_irq0_intc>;
193 reg = <0x406200 0x58>; 192 reg = <0x406200 0x58>;
194 interrupts = <24>; 193 interrupts = <24>;
195 interrupt-names = "upg_b 194 interrupt-names = "upg_bscc";
196 status = "disabled"; 195 status = "disabled";
197 }; 196 };
198 197
199 bscd: i2c@406280 { 198 bscd: i2c@406280 {
200 clock-frequency = <39000 199 clock-frequency = <390000>;
201 compatible = "brcm,brcms 200 compatible = "brcm,brcmstb-i2c";
202 interrupt-parent = <&upg 201 interrupt-parent = <&upg_irq0_intc>;
203 reg = <0x406280 0x58>; 202 reg = <0x406280 0x58>;
204 interrupts = <25>; 203 interrupts = <25>;
205 interrupt-names = "upg_b 204 interrupt-names = "upg_bscd";
206 status = "disabled"; 205 status = "disabled";
207 }; 206 };
208 207
209 bsce: i2c@406300 { 208 bsce: i2c@406300 {
210 clock-frequency = <39000 209 clock-frequency = <390000>;
211 compatible = "brcm,brcms 210 compatible = "brcm,brcmstb-i2c";
212 interrupt-parent = <&upg 211 interrupt-parent = <&upg_irq0_intc>;
213 reg = <0x406300 0x58>; 212 reg = <0x406300 0x58>;
214 interrupts = <26>; 213 interrupts = <26>;
215 interrupt-names = "upg_b 214 interrupt-names = "upg_bsce";
216 status = "disabled"; 215 status = "disabled";
217 }; 216 };
218 217
219 pwma: pwm@406580 { 218 pwma: pwm@406580 {
220 compatible = "brcm,bcm 219 compatible = "brcm,bcm7038-pwm";
221 reg = <0x406580 0x28>; 220 reg = <0x406580 0x28>;
222 #pwm-cells = <2>; 221 #pwm-cells = <2>;
223 clocks = <&upg_clk>; 222 clocks = <&upg_clk>;
224 status = "disabled"; 223 status = "disabled";
225 }; 224 };
226 225
227 pwmb: pwm@406800 { 226 pwmb: pwm@406800 {
228 compatible = "brcm,bcm 227 compatible = "brcm,bcm7038-pwm";
229 reg = <0x406800 0x28>; 228 reg = <0x406800 0x28>;
230 #pwm-cells = <2>; 229 #pwm-cells = <2>;
231 clocks = <&upg_clk>; 230 clocks = <&upg_clk>;
232 status = "disabled"; 231 status = "disabled";
233 }; 232 };
234 233
235 watchdog: watchdog@4067e8 { <<
236 clocks = <&upg_clk>; <<
237 compatible = "brcm,bcm <<
238 reg = <0x4067e8 0x14>; <<
239 status = "disabled"; <<
240 }; <<
241 <<
242 aon_pm_l2_intc: interrupt-cont 234 aon_pm_l2_intc: interrupt-controller@408440 {
243 compatible = "brcm,l2- 235 compatible = "brcm,l2-intc";
244 reg = <0x408440 0x30>; 236 reg = <0x408440 0x30>;
245 interrupt-controller; 237 interrupt-controller;
246 #interrupt-cells = <1> 238 #interrupt-cells = <1>;
247 interrupt-parent = <&p 239 interrupt-parent = <&periph_intc>;
248 interrupts = <49>; 240 interrupts = <49>;
249 brcm,irq-can-wake; 241 brcm,irq-can-wake;
250 }; 242 };
251 243
252 aon_ctrl: syscon@408000 { <<
253 compatible = "brcm,brc <<
254 reg = <0x408000 0x100> <<
255 reg-names = "aon-ctrl" <<
256 }; <<
257 <<
258 timers: timer@4067c0 { <<
259 compatible = "brcm,brc <<
260 reg = <0x4067c0 0x40>; <<
261 }; <<
262 <<
263 upg_gio: gpio@406700 { 244 upg_gio: gpio@406700 {
264 compatible = "brcm,brc 245 compatible = "brcm,brcmstb-gpio";
265 reg = <0x406700 0x80>; 246 reg = <0x406700 0x80>;
266 #gpio-cells = <2>; 247 #gpio-cells = <2>;
267 #interrupt-cells = <2> 248 #interrupt-cells = <2>;
268 gpio-controller; 249 gpio-controller;
269 interrupt-controller; 250 interrupt-controller;
270 interrupt-parent = <&u 251 interrupt-parent = <&upg_irq0_intc>;
271 interrupts = <6>; 252 interrupts = <6>;
272 brcm,gpio-bank-widths 253 brcm,gpio-bank-widths = <32 32 32 21>;
273 }; 254 };
274 255
275 upg_gio_aon: gpio@4094c0 { 256 upg_gio_aon: gpio@4094c0 {
276 compatible = "brcm,brc 257 compatible = "brcm,brcmstb-gpio";
277 reg = <0x4094c0 0x40>; 258 reg = <0x4094c0 0x40>;
278 #gpio-cells = <2>; 259 #gpio-cells = <2>;
279 #interrupt-cells = <2> 260 #interrupt-cells = <2>;
280 gpio-controller; 261 gpio-controller;
281 interrupt-controller; 262 interrupt-controller;
282 interrupt-parent = <&u 263 interrupt-parent = <&upg_aon_irq0_intc>;
283 interrupts = <6>; 264 interrupts = <6>;
284 interrupts-extended = 265 interrupts-extended = <&upg_aon_irq0_intc 6>,
285 266 <&aon_pm_l2_intc 5>;
286 wakeup-source; 267 wakeup-source;
287 brcm,gpio-bank-widths 268 brcm,gpio-bank-widths = <18 4>;
288 }; 269 };
289 270
290 enet0: ethernet@b80000 { 271 enet0: ethernet@b80000 {
291 phy-mode = "internal"; 272 phy-mode = "internal";
292 phy-handle = <&phy1>; 273 phy-handle = <&phy1>;
293 mac-address = [ 00 10 274 mac-address = [ 00 10 18 36 23 1a ];
294 compatible = "brcm,gen 275 compatible = "brcm,genet-v3";
295 #address-cells = <0x1> 276 #address-cells = <0x1>;
296 #size-cells = <0x1>; 277 #size-cells = <0x1>;
297 reg = <0xb80000 0x11c8 278 reg = <0xb80000 0x11c88>;
298 interrupts = <17>, <18 279 interrupts = <17>, <18>;
299 interrupt-parent = <&p 280 interrupt-parent = <&periph_intc>;
300 status = "disabled"; 281 status = "disabled";
301 282
302 mdio@e14 { 283 mdio@e14 {
303 compatible = " 284 compatible = "brcm,genet-mdio-v3";
304 #address-cells 285 #address-cells = <0x1>;
305 #size-cells = 286 #size-cells = <0x0>;
306 reg = <0xe14 0 287 reg = <0xe14 0x8>;
307 288
308 phy1: ethernet 289 phy1: ethernet-phy@1 {
309 max-sp 290 max-speed = <100>;
310 reg = 291 reg = <0x1>;
311 compat 292 compatible = "brcm,40nm-ephy",
312 293 "ethernet-phy-ieee802.3-c22";
313 }; 294 };
314 }; 295 };
315 }; 296 };
316 297
317 ehci0: usb@480300 { 298 ehci0: usb@480300 {
318 compatible = "brcm,bcm 299 compatible = "brcm,bcm7425-ehci", "generic-ehci";
319 reg = <0x480300 0x100> 300 reg = <0x480300 0x100>;
320 native-endian; 301 native-endian;
321 interrupt-parent = <&p 302 interrupt-parent = <&periph_intc>;
322 interrupts = <65>; 303 interrupts = <65>;
323 status = "disabled"; 304 status = "disabled";
324 }; 305 };
325 306
326 ohci0: usb@480400 { 307 ohci0: usb@480400 {
327 compatible = "brcm,bcm 308 compatible = "brcm,bcm7425-ohci", "generic-ohci";
328 reg = <0x480400 0x100> 309 reg = <0x480400 0x100>;
329 native-endian; 310 native-endian;
330 no-big-frame-no; 311 no-big-frame-no;
331 interrupt-parent = <&p 312 interrupt-parent = <&periph_intc>;
332 interrupts = <67>; 313 interrupts = <67>;
333 status = "disabled"; 314 status = "disabled";
334 }; 315 };
335 316
336 ehci1: usb@480500 { 317 ehci1: usb@480500 {
337 compatible = "brcm,bcm 318 compatible = "brcm,bcm7425-ehci", "generic-ehci";
338 reg = <0x480500 0x100> 319 reg = <0x480500 0x100>;
339 native-endian; 320 native-endian;
340 interrupt-parent = <&p 321 interrupt-parent = <&periph_intc>;
341 interrupts = <66>; 322 interrupts = <66>;
342 status = "disabled"; 323 status = "disabled";
343 }; 324 };
344 325
345 ohci1: usb@480600 { 326 ohci1: usb@480600 {
346 compatible = "brcm,bcm 327 compatible = "brcm,bcm7425-ohci", "generic-ohci";
347 reg = <0x480600 0x100> 328 reg = <0x480600 0x100>;
348 native-endian; 329 native-endian;
349 no-big-frame-no; 330 no-big-frame-no;
350 interrupt-parent = <&p 331 interrupt-parent = <&periph_intc>;
351 interrupts = <68>; 332 interrupts = <68>;
352 status = "disabled"; 333 status = "disabled";
353 }; 334 };
354 335
355 ehci2: usb@490300 { 336 ehci2: usb@490300 {
356 compatible = "brcm,bcm 337 compatible = "brcm,bcm7425-ehci", "generic-ehci";
357 reg = <0x490300 0x100> 338 reg = <0x490300 0x100>;
358 native-endian; 339 native-endian;
359 interrupt-parent = <&p 340 interrupt-parent = <&periph_intc>;
360 interrupts = <70>; 341 interrupts = <70>;
361 status = "disabled"; 342 status = "disabled";
362 }; 343 };
363 344
364 ohci2: usb@490400 { 345 ohci2: usb@490400 {
365 compatible = "brcm,bcm 346 compatible = "brcm,bcm7425-ohci", "generic-ohci";
366 reg = <0x490400 0x100> 347 reg = <0x490400 0x100>;
367 native-endian; 348 native-endian;
368 no-big-frame-no; 349 no-big-frame-no;
369 interrupt-parent = <&p 350 interrupt-parent = <&periph_intc>;
370 interrupts = <72>; 351 interrupts = <72>;
371 status = "disabled"; 352 status = "disabled";
372 }; 353 };
373 354
374 ehci3: usb@490500 { 355 ehci3: usb@490500 {
375 compatible = "brcm,bcm 356 compatible = "brcm,bcm7425-ehci", "generic-ehci";
376 reg = <0x490500 0x100> 357 reg = <0x490500 0x100>;
377 native-endian; 358 native-endian;
378 interrupt-parent = <&p 359 interrupt-parent = <&periph_intc>;
379 interrupts = <71>; 360 interrupts = <71>;
380 status = "disabled"; 361 status = "disabled";
381 }; 362 };
382 363
383 ohci3: usb@490600 { 364 ohci3: usb@490600 {
384 compatible = "brcm,bcm 365 compatible = "brcm,bcm7425-ohci", "generic-ohci";
385 reg = <0x490600 0x100> 366 reg = <0x490600 0x100>;
386 native-endian; 367 native-endian;
387 no-big-frame-no; 368 no-big-frame-no;
388 interrupt-parent = <&p 369 interrupt-parent = <&periph_intc>;
389 interrupts = <73>; 370 interrupts = <73>;
390 status = "disabled"; 371 status = "disabled";
391 }; 372 };
392 373
393 hif_l2_intc: interrupt-control 374 hif_l2_intc: interrupt-controller@41a000 {
394 compatible = "brcm,l2- 375 compatible = "brcm,l2-intc";
395 reg = <0x41a000 0x30>; 376 reg = <0x41a000 0x30>;
396 interrupt-controller; 377 interrupt-controller;
397 #interrupt-cells = <1> 378 #interrupt-cells = <1>;
398 interrupt-parent = <&p 379 interrupt-parent = <&periph_intc>;
399 interrupts = <24>; 380 interrupts = <24>;
400 }; 381 };
401 382
402 nand: nand@41b800 { 383 nand: nand@41b800 {
403 compatible = "brcm,brc 384 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
404 #address-cells = <1>; 385 #address-cells = <1>;
405 #size-cells = <0>; 386 #size-cells = <0>;
406 reg-names = "nand", "f !! 387 reg-names = "nand";
407 reg = <0x41b800 0x400> !! 388 reg = <0x41b800 0x400>;
408 interrupt-parent = <&h 389 interrupt-parent = <&hif_l2_intc>;
409 interrupts = <24>; 390 interrupts = <24>;
410 status = "disabled"; 391 status = "disabled";
411 }; 392 };
412 393
413 sata: sata@181000 { 394 sata: sata@181000 {
414 compatible = "brcm,bcm 395 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
415 reg-names = "ahci", "t 396 reg-names = "ahci", "top-ctrl";
416 reg = <0x181000 0xa9c> 397 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
417 interrupt-parent = <&p 398 interrupt-parent = <&periph_intc>;
418 interrupts = <41>; 399 interrupts = <41>;
419 #address-cells = <1>; 400 #address-cells = <1>;
420 #size-cells = <0>; 401 #size-cells = <0>;
421 status = "disabled"; 402 status = "disabled";
422 403
423 sata0: sata-port@0 { 404 sata0: sata-port@0 {
424 reg = <0>; 405 reg = <0>;
425 phys = <&sata_ 406 phys = <&sata_phy0>;
426 }; 407 };
427 408
428 sata1: sata-port@1 { 409 sata1: sata-port@1 {
429 reg = <1>; 410 reg = <1>;
430 phys = <&sata_ 411 phys = <&sata_phy1>;
431 }; 412 };
432 }; 413 };
433 414
434 sata_phy: sata-phy@180100 { 415 sata_phy: sata-phy@180100 {
435 compatible = "brcm,bcm 416 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
436 reg = <0x180100 0x0eff 417 reg = <0x180100 0x0eff>;
437 reg-names = "phy"; 418 reg-names = "phy";
438 #address-cells = <1>; 419 #address-cells = <1>;
439 #size-cells = <0>; 420 #size-cells = <0>;
440 status = "disabled"; 421 status = "disabled";
441 422
442 sata_phy0: sata-phy@0 423 sata_phy0: sata-phy@0 {
443 reg = <0>; 424 reg = <0>;
444 #phy-cells = < 425 #phy-cells = <0>;
445 }; 426 };
446 427
447 sata_phy1: sata-phy@1 428 sata_phy1: sata-phy@1 {
448 reg = <1>; 429 reg = <1>;
449 #phy-cells = < 430 #phy-cells = <0>;
450 }; 431 };
451 }; 432 };
452 433
453 sdhci0: sdhci@419000 { 434 sdhci0: sdhci@419000 {
454 compatible = "brcm,bcm 435 compatible = "brcm,bcm7425-sdhci";
455 reg = <0x419000 0x100> 436 reg = <0x419000 0x100>;
456 interrupt-parent = <&p 437 interrupt-parent = <&periph_intc>;
457 interrupts = <43>; 438 interrupts = <43>;
458 sd-uhs-sdr50; 439 sd-uhs-sdr50;
459 mmc-hs200-1_8v; 440 mmc-hs200-1_8v;
460 status = "disabled"; 441 status = "disabled";
461 }; 442 };
462 443
463 sdhci1: sdhci@419200 { 444 sdhci1: sdhci@419200 {
464 compatible = "brcm,bcm 445 compatible = "brcm,bcm7425-sdhci";
465 reg = <0x419200 0x100> 446 reg = <0x419200 0x100>;
466 interrupt-parent = <&p 447 interrupt-parent = <&periph_intc>;
467 interrupts = <44>; 448 interrupts = <44>;
468 sd-uhs-sdr50; 449 sd-uhs-sdr50;
469 mmc-hs200-1_8v; 450 mmc-hs200-1_8v;
470 status = "disabled"; 451 status = "disabled";
471 }; 452 };
472 453
473 spi_l2_intc: interrupt-control 454 spi_l2_intc: interrupt-controller@41ad00 {
474 compatible = "brcm,l2- 455 compatible = "brcm,l2-intc";
475 reg = <0x41ad00 0x30>; 456 reg = <0x41ad00 0x30>;
476 interrupt-controller; 457 interrupt-controller;
477 #interrupt-cells = <1> 458 #interrupt-cells = <1>;
478 interrupt-parent = <&p 459 interrupt-parent = <&periph_intc>;
479 interrupts = <25>; 460 interrupts = <25>;
480 }; 461 };
481 462
482 qspi: spi@41c000 { 463 qspi: spi@41c000 {
483 #address-cells = <0x1> 464 #address-cells = <0x1>;
484 #size-cells = <0x0>; 465 #size-cells = <0x0>;
485 compatible = "brcm,spi 466 compatible = "brcm,spi-bcm-qspi",
486 "brcm,spi 467 "brcm,spi-brcmstb-qspi";
487 clocks = <&upg_clk>; 468 clocks = <&upg_clk>;
488 reg = <0x419920 0x4 0x 469 reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
489 reg-names = "cs_reg", 470 reg-names = "cs_reg", "hif_mspi", "bspi";
490 interrupts = <0x0 0x1 471 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
491 interrupt-parent = <&s 472 interrupt-parent = <&spi_l2_intc>;
492 interrupt-names = "spi 473 interrupt-names = "spi_lr_fullness_reached",
493 "spi 474 "spi_lr_session_aborted",
494 "spi 475 "spi_lr_impatient",
495 "spi 476 "spi_lr_session_done",
496 "spi 477 "spi_lr_overread",
497 "msp 478 "mspi_done",
498 "msp 479 "mspi_halted";
499 status = "disabled"; 480 status = "disabled";
500 }; 481 };
501 482
502 mspi: spi@409200 { 483 mspi: spi@409200 {
503 #address-cells = <1>; 484 #address-cells = <1>;
504 #size-cells = <0>; 485 #size-cells = <0>;
505 compatible = "brcm,spi 486 compatible = "brcm,spi-bcm-qspi",
506 "brcm,spi 487 "brcm,spi-brcmstb-mspi";
507 clocks = <&upg_clk>; 488 clocks = <&upg_clk>;
508 reg = <0x409200 0x180> 489 reg = <0x409200 0x180>;
509 reg-names = "mspi"; 490 reg-names = "mspi";
510 interrupts = <0x14>; 491 interrupts = <0x14>;
511 interrupt-parent = <&u 492 interrupt-parent = <&upg_aon_irq0_intc>;
512 interrupt-names = "msp 493 interrupt-names = "mspi_done";
513 status = "disabled"; 494 status = "disabled";
514 }; 495 };
515 <<
516 waketimer: waketimer@409580 { <<
517 compatible = "brcm,brc <<
518 reg = <0x409580 0x14>; <<
519 interrupts = <0x3>; <<
520 interrupt-parent = <&a <<
521 interrupt-names = "tim <<
522 clocks = <&upg_clk>; <<
523 status = "disabled"; <<
524 }; <<
525 }; <<
526 <<
527 memory_controllers { <<
528 compatible = "simple-bus"; <<
529 ranges = <0x0 0x103b0000 0x1a0 <<
530 #address-cells = <1>; <<
531 #size-cells = <1>; <<
532 <<
533 memory-controller@0 { <<
534 compatible = "brcm,brc <<
535 ranges = <0x0 0x0 0xa0 <<
536 #address-cells = <1>; <<
537 #size-cells = <1>; <<
538 <<
539 memc-arb@1000 { <<
540 compatible = " <<
541 reg = <0x1000 <<
542 }; <<
543 <<
544 memc-ddr@2000 { <<
545 compatible = " <<
546 reg = <0x2000 <<
547 }; <<
548 <<
549 ddr-phy@6000 { <<
550 compatible = " <<
551 reg = <0x6000 <<
552 }; <<
553 <<
554 shimphy@8000 { <<
555 compatible = " <<
556 reg = <0x8000 <<
557 }; <<
558 }; <<
559 <<
560 memory-controller@1 { <<
561 compatible = "brcm,brc <<
562 ranges = <0x0 0x10000 <<
563 #address-cells = <1>; <<
564 #size-cells = <1>; <<
565 <<
566 memc-arb@1000 { <<
567 compatible = " <<
568 reg = <0x1000 <<
569 }; <<
570 <<
571 memc-ddr@2000 { <<
572 compatible = " <<
573 reg = <0x2000 <<
574 }; <<
575 <<
576 ddr-phy@6000 { <<
577 compatible = " <<
578 reg = <0x6000 <<
579 }; <<
580 <<
581 shimphy@8000 { <<
582 compatible = " <<
583 reg = <0x8000 <<
584 }; <<
585 }; <<
586 }; <<
587 <<
588 pcie_0: pcie@8b20000 { <<
589 status = "disabled"; <<
590 compatible = "brcm,bcm7425-pci <<
591 <<
592 ranges = <0x02000000 0x0 0xd00 <<
593 0x02000000 0x0 0xd80 <<
594 0x02000000 0x0 0xe00 <<
595 0x02000000 0x0 0xe80 <<
596 <<
597 reg = <0x10410000 0x19310>; <<
598 aspm-no-l0s; <<
599 device_type = "pci"; <<
600 msi-controller; <<
601 msi-parent = <&pcie_0>; <<
602 #address-cells = <0x3>; <<
603 #size-cells = <0x2>; <<
604 bus-range = <0x0 0xff>; <<
605 interrupt-map-mask = <0x0 0x0 <<
606 linux,pci-domain = <0x0>; <<
607 <<
608 interrupt-parent = <&periph_in <<
609 interrupts = <37>, <37>; <<
610 interrupt-names = "pcie", "msi <<
611 #interrupt-cells = <0x1>; <<
612 interrupt-map = <0 0 0 1 &peri <<
613 0 0 0 1 &peri <<
614 0 0 0 1 &peri <<
615 0 0 0 1 &peri <<
616 }; 496 };
617 }; 497 };
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