1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 / { 2 / {
3 #address-cells = <1>; 3 #address-cells = <1>;
4 #size-cells = <1>; 4 #size-cells = <1>;
5 compatible = "brcm,bcm7425"; 5 compatible = "brcm,bcm7425";
6 6
7 cpus { 7 cpus {
8 #address-cells = <1>; 8 #address-cells = <1>;
9 #size-cells = <0>; 9 #size-cells = <0>;
10 10
11 mips-hpt-frequency = <16312500 11 mips-hpt-frequency = <163125000>;
12 12
13 cpu@0 { 13 cpu@0 {
14 compatible = "brcm,bmi 14 compatible = "brcm,bmips5000";
15 device_type = "cpu"; 15 device_type = "cpu";
16 reg = <0>; 16 reg = <0>;
17 }; 17 };
18 18
19 cpu@1 { 19 cpu@1 {
20 compatible = "brcm,bmi 20 compatible = "brcm,bmips5000";
21 device_type = "cpu"; 21 device_type = "cpu";
22 reg = <1>; 22 reg = <1>;
23 }; 23 };
24 }; 24 };
25 25
26 aliases { 26 aliases {
27 uart0 = &uart0; 27 uart0 = &uart0;
28 }; 28 };
29 29
30 cpu_intc: interrupt-controller { 30 cpu_intc: interrupt-controller {
31 #address-cells = <0>; 31 #address-cells = <0>;
32 compatible = "mti,cpu-interrup 32 compatible = "mti,cpu-interrupt-controller";
33 33
34 interrupt-controller; 34 interrupt-controller;
35 #interrupt-cells = <1>; 35 #interrupt-cells = <1>;
36 }; 36 };
37 37
38 clocks { 38 clocks {
39 uart_clk: uart_clk { 39 uart_clk: uart_clk {
40 compatible = "fixed-cl 40 compatible = "fixed-clock";
41 #clock-cells = <0>; 41 #clock-cells = <0>;
42 clock-frequency = <810 42 clock-frequency = <81000000>;
43 }; 43 };
44 44
45 upg_clk: upg_clk { 45 upg_clk: upg_clk {
46 compatible = "fixed-cl 46 compatible = "fixed-clock";
47 #clock-cells = <0>; 47 #clock-cells = <0>;
48 clock-frequency = <270 48 clock-frequency = <27000000>;
49 }; 49 };
50 }; 50 };
51 51
52 rdb { 52 rdb {
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <1>; 54 #size-cells = <1>;
55 55
56 compatible = "simple-bus"; 56 compatible = "simple-bus";
57 ranges = <0 0x10000000 0x01000 57 ranges = <0 0x10000000 0x01000000>;
58 58
59 periph_intc: interrupt-control 59 periph_intc: interrupt-controller@41a400 {
60 compatible = "brcm,bcm 60 compatible = "brcm,bcm7038-l1-intc";
61 reg = <0x41a400 0x30>, 61 reg = <0x41a400 0x30>, <0x41a600 0x30>;
62 62
63 interrupt-controller; 63 interrupt-controller;
64 #interrupt-cells = <1> 64 #interrupt-cells = <1>;
65 65
66 interrupt-parent = <&c 66 interrupt-parent = <&cpu_intc>;
67 interrupts = <2>, <3>; 67 interrupts = <2>, <3>;
68 }; 68 };
69 69
70 sun_l2_intc: interrupt-control 70 sun_l2_intc: interrupt-controller@403000 {
71 compatible = "brcm,l2- 71 compatible = "brcm,l2-intc";
72 reg = <0x403000 0x30>; 72 reg = <0x403000 0x30>;
73 interrupt-controller; 73 interrupt-controller;
74 #interrupt-cells = <1> 74 #interrupt-cells = <1>;
75 interrupt-parent = <&p 75 interrupt-parent = <&periph_intc>;
76 interrupts = <47>; 76 interrupts = <47>;
77 }; 77 };
78 78
79 gisb-arb@400000 { 79 gisb-arb@400000 {
80 compatible = "brcm,bcm 80 compatible = "brcm,bcm7400-gisb-arb";
81 reg = <0x400000 0xdc>; 81 reg = <0x400000 0xdc>;
82 native-endian; 82 native-endian;
83 interrupt-parent = <&s 83 interrupt-parent = <&sun_l2_intc>;
84 interrupts = <0>, <2>; 84 interrupts = <0>, <2>;
85 brcm,gisb-arb-master-m 85 brcm,gisb-arb-master-mask = <0x177b>;
86 brcm,gisb-arb-master-n 86 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
87 87 "bsp_0", "rdc_0",
88 88 "raaga_0", "avd_1",
89 89 "jtag_0", "svd_0",
90 90 "vice_0";
91 }; 91 };
92 92
93 upg_irq0_intc: interrupt-contr 93 upg_irq0_intc: interrupt-controller@406780 {
94 compatible = "brcm,bcm 94 compatible = "brcm,bcm7120-l2-intc";
95 reg = <0x406780 0x8>; 95 reg = <0x406780 0x8>;
96 96
97 brcm,int-map-mask = <0 97 brcm,int-map-mask = <0x44>, <0x7000000>;
98 brcm,int-fwd-mask = <0 98 brcm,int-fwd-mask = <0x70000>;
99 99
100 interrupt-controller; 100 interrupt-controller;
101 #interrupt-cells = <1> 101 #interrupt-cells = <1>;
102 102
103 interrupt-parent = <&p 103 interrupt-parent = <&periph_intc>;
104 interrupts = <55>, <53 104 interrupts = <55>, <53>;
105 interrupt-names = "upg 105 interrupt-names = "upg_main", "upg_bsc";
106 }; 106 };
107 107
108 upg_aon_irq0_intc: interrupt-c 108 upg_aon_irq0_intc: interrupt-controller@409480 {
109 compatible = "brcm,bcm 109 compatible = "brcm,bcm7120-l2-intc";
110 reg = <0x409480 0x8>; 110 reg = <0x409480 0x8>;
111 111
112 brcm,int-map-mask = <0 112 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
113 brcm,int-fwd-mask = <0 113 brcm,int-fwd-mask = <0>;
114 brcm,irq-can-wake; 114 brcm,irq-can-wake;
115 115
116 interrupt-controller; 116 interrupt-controller;
117 #interrupt-cells = <1> 117 #interrupt-cells = <1>;
118 118
119 interrupt-parent = <&p 119 interrupt-parent = <&periph_intc>;
120 interrupts = <56>, <54 120 interrupts = <56>, <54>, <59>;
121 interrupt-names = "upg 121 interrupt-names = "upg_main_aon", "upg_bsc_aon",
122 "upg 122 "upg_spi";
123 }; 123 };
124 124
125 sun_top_ctrl: syscon@404000 { 125 sun_top_ctrl: syscon@404000 {
126 compatible = "brcm,bcm 126 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
127 reg = <0x404000 0x51c> 127 reg = <0x404000 0x51c>;
128 native-endian; 128 native-endian;
129 }; 129 };
130 130
131 reboot { 131 reboot {
132 compatible = "brcm,brc 132 compatible = "brcm,brcmstb-reboot";
133 syscon = <&sun_top_ctr 133 syscon = <&sun_top_ctrl 0x304 0x308>;
134 }; 134 };
135 135
136 uart0: serial@406b00 { 136 uart0: serial@406b00 {
137 compatible = "ns16550a 137 compatible = "ns16550a";
138 reg = <0x406b00 0x20>; 138 reg = <0x406b00 0x20>;
139 reg-io-width = <0x4>; 139 reg-io-width = <0x4>;
140 reg-shift = <0x2>; 140 reg-shift = <0x2>;
141 interrupt-parent = <&p 141 interrupt-parent = <&periph_intc>;
142 interrupts = <61>; 142 interrupts = <61>;
143 clocks = <&uart_clk>; 143 clocks = <&uart_clk>;
144 status = "disabled"; 144 status = "disabled";
145 }; 145 };
146 146
147 uart1: serial@406b40 { 147 uart1: serial@406b40 {
148 compatible = "ns16550a 148 compatible = "ns16550a";
149 reg = <0x406b40 0x20>; 149 reg = <0x406b40 0x20>;
150 reg-io-width = <0x4>; 150 reg-io-width = <0x4>;
151 reg-shift = <0x2>; 151 reg-shift = <0x2>;
152 interrupt-parent = <&p 152 interrupt-parent = <&periph_intc>;
153 interrupts = <62>; 153 interrupts = <62>;
154 clocks = <&uart_clk>; 154 clocks = <&uart_clk>;
155 status = "disabled"; 155 status = "disabled";
156 }; 156 };
157 157
158 uart2: serial@406b80 { 158 uart2: serial@406b80 {
159 compatible = "ns16550a 159 compatible = "ns16550a";
160 reg = <0x406b80 0x20>; 160 reg = <0x406b80 0x20>;
161 reg-io-width = <0x4>; 161 reg-io-width = <0x4>;
162 reg-shift = <0x2>; 162 reg-shift = <0x2>;
163 interrupt-parent = <&p 163 interrupt-parent = <&periph_intc>;
164 interrupts = <63>; 164 interrupts = <63>;
165 clocks = <&uart_clk>; 165 clocks = <&uart_clk>;
166 status = "disabled"; 166 status = "disabled";
167 }; 167 };
168 168
169 bsca: i2c@409180 { 169 bsca: i2c@409180 {
170 clock-frequency = <39000 170 clock-frequency = <390000>;
171 compatible = "brcm,brcms 171 compatible = "brcm,brcmstb-i2c";
172 interrupt-parent = <&upg 172 interrupt-parent = <&upg_aon_irq0_intc>;
173 reg = <0x409180 0x58>; 173 reg = <0x409180 0x58>;
174 interrupts = <27>; 174 interrupts = <27>;
175 interrupt-names = "upg_b 175 interrupt-names = "upg_bsca";
176 status = "disabled"; 176 status = "disabled";
177 }; 177 };
178 178
179 bscb: i2c@409400 { 179 bscb: i2c@409400 {
180 clock-frequency = <39000 180 clock-frequency = <390000>;
181 compatible = "brcm,brcms 181 compatible = "brcm,brcmstb-i2c";
182 interrupt-parent = <&upg 182 interrupt-parent = <&upg_aon_irq0_intc>;
183 reg = <0x409400 0x58>; 183 reg = <0x409400 0x58>;
184 interrupts = <28>; 184 interrupts = <28>;
185 interrupt-names = "upg_b 185 interrupt-names = "upg_bscb";
186 status = "disabled"; 186 status = "disabled";
187 }; 187 };
188 188
189 bscc: i2c@406200 { 189 bscc: i2c@406200 {
190 clock-frequency = <39000 190 clock-frequency = <390000>;
191 compatible = "brcm,brcms 191 compatible = "brcm,brcmstb-i2c";
192 interrupt-parent = <&upg 192 interrupt-parent = <&upg_irq0_intc>;
193 reg = <0x406200 0x58>; 193 reg = <0x406200 0x58>;
194 interrupts = <24>; 194 interrupts = <24>;
195 interrupt-names = "upg_b 195 interrupt-names = "upg_bscc";
196 status = "disabled"; 196 status = "disabled";
197 }; 197 };
198 198
199 bscd: i2c@406280 { 199 bscd: i2c@406280 {
200 clock-frequency = <39000 200 clock-frequency = <390000>;
201 compatible = "brcm,brcms 201 compatible = "brcm,brcmstb-i2c";
202 interrupt-parent = <&upg 202 interrupt-parent = <&upg_irq0_intc>;
203 reg = <0x406280 0x58>; 203 reg = <0x406280 0x58>;
204 interrupts = <25>; 204 interrupts = <25>;
205 interrupt-names = "upg_b 205 interrupt-names = "upg_bscd";
206 status = "disabled"; 206 status = "disabled";
207 }; 207 };
208 208
209 bsce: i2c@406300 { 209 bsce: i2c@406300 {
210 clock-frequency = <39000 210 clock-frequency = <390000>;
211 compatible = "brcm,brcms 211 compatible = "brcm,brcmstb-i2c";
212 interrupt-parent = <&upg 212 interrupt-parent = <&upg_irq0_intc>;
213 reg = <0x406300 0x58>; 213 reg = <0x406300 0x58>;
214 interrupts = <26>; 214 interrupts = <26>;
215 interrupt-names = "upg_b 215 interrupt-names = "upg_bsce";
216 status = "disabled"; 216 status = "disabled";
217 }; 217 };
218 218
219 pwma: pwm@406580 { 219 pwma: pwm@406580 {
220 compatible = "brcm,bcm 220 compatible = "brcm,bcm7038-pwm";
221 reg = <0x406580 0x28>; 221 reg = <0x406580 0x28>;
222 #pwm-cells = <2>; 222 #pwm-cells = <2>;
223 clocks = <&upg_clk>; 223 clocks = <&upg_clk>;
224 status = "disabled"; 224 status = "disabled";
225 }; 225 };
226 226
227 pwmb: pwm@406800 { 227 pwmb: pwm@406800 {
228 compatible = "brcm,bcm 228 compatible = "brcm,bcm7038-pwm";
229 reg = <0x406800 0x28>; 229 reg = <0x406800 0x28>;
230 #pwm-cells = <2>; 230 #pwm-cells = <2>;
231 clocks = <&upg_clk>; 231 clocks = <&upg_clk>;
232 status = "disabled"; 232 status = "disabled";
233 }; 233 };
234 234
235 watchdog: watchdog@4067e8 { 235 watchdog: watchdog@4067e8 {
236 clocks = <&upg_clk>; 236 clocks = <&upg_clk>;
237 compatible = "brcm,bcm 237 compatible = "brcm,bcm7038-wdt";
238 reg = <0x4067e8 0x14>; 238 reg = <0x4067e8 0x14>;
239 status = "disabled"; 239 status = "disabled";
240 }; 240 };
241 241
242 aon_pm_l2_intc: interrupt-cont 242 aon_pm_l2_intc: interrupt-controller@408440 {
243 compatible = "brcm,l2- 243 compatible = "brcm,l2-intc";
244 reg = <0x408440 0x30>; 244 reg = <0x408440 0x30>;
245 interrupt-controller; 245 interrupt-controller;
246 #interrupt-cells = <1> 246 #interrupt-cells = <1>;
247 interrupt-parent = <&p 247 interrupt-parent = <&periph_intc>;
248 interrupts = <49>; 248 interrupts = <49>;
249 brcm,irq-can-wake; 249 brcm,irq-can-wake;
250 }; 250 };
251 251
252 aon_ctrl: syscon@408000 { 252 aon_ctrl: syscon@408000 {
253 compatible = "brcm,brc 253 compatible = "brcm,brcmstb-aon-ctrl";
254 reg = <0x408000 0x100> 254 reg = <0x408000 0x100>, <0x408200 0x200>;
255 reg-names = "aon-ctrl" 255 reg-names = "aon-ctrl", "aon-sram";
256 }; 256 };
257 257
258 timers: timer@4067c0 { 258 timers: timer@4067c0 {
259 compatible = "brcm,brc 259 compatible = "brcm,brcmstb-timers";
260 reg = <0x4067c0 0x40>; 260 reg = <0x4067c0 0x40>;
261 }; 261 };
262 262
263 upg_gio: gpio@406700 { 263 upg_gio: gpio@406700 {
264 compatible = "brcm,brc 264 compatible = "brcm,brcmstb-gpio";
265 reg = <0x406700 0x80>; 265 reg = <0x406700 0x80>;
266 #gpio-cells = <2>; 266 #gpio-cells = <2>;
267 #interrupt-cells = <2> 267 #interrupt-cells = <2>;
268 gpio-controller; 268 gpio-controller;
269 interrupt-controller; 269 interrupt-controller;
270 interrupt-parent = <&u 270 interrupt-parent = <&upg_irq0_intc>;
271 interrupts = <6>; 271 interrupts = <6>;
272 brcm,gpio-bank-widths 272 brcm,gpio-bank-widths = <32 32 32 21>;
273 }; 273 };
274 274
275 upg_gio_aon: gpio@4094c0 { 275 upg_gio_aon: gpio@4094c0 {
276 compatible = "brcm,brc 276 compatible = "brcm,brcmstb-gpio";
277 reg = <0x4094c0 0x40>; 277 reg = <0x4094c0 0x40>;
278 #gpio-cells = <2>; 278 #gpio-cells = <2>;
279 #interrupt-cells = <2> 279 #interrupt-cells = <2>;
280 gpio-controller; 280 gpio-controller;
281 interrupt-controller; 281 interrupt-controller;
282 interrupt-parent = <&u 282 interrupt-parent = <&upg_aon_irq0_intc>;
283 interrupts = <6>; 283 interrupts = <6>;
284 interrupts-extended = 284 interrupts-extended = <&upg_aon_irq0_intc 6>,
285 285 <&aon_pm_l2_intc 5>;
286 wakeup-source; 286 wakeup-source;
287 brcm,gpio-bank-widths 287 brcm,gpio-bank-widths = <18 4>;
288 }; 288 };
289 289
290 enet0: ethernet@b80000 { 290 enet0: ethernet@b80000 {
291 phy-mode = "internal"; 291 phy-mode = "internal";
292 phy-handle = <&phy1>; 292 phy-handle = <&phy1>;
293 mac-address = [ 00 10 293 mac-address = [ 00 10 18 36 23 1a ];
294 compatible = "brcm,gen 294 compatible = "brcm,genet-v3";
295 #address-cells = <0x1> 295 #address-cells = <0x1>;
296 #size-cells = <0x1>; 296 #size-cells = <0x1>;
297 reg = <0xb80000 0x11c8 297 reg = <0xb80000 0x11c88>;
298 interrupts = <17>, <18 298 interrupts = <17>, <18>;
299 interrupt-parent = <&p 299 interrupt-parent = <&periph_intc>;
300 status = "disabled"; 300 status = "disabled";
301 301
302 mdio@e14 { 302 mdio@e14 {
303 compatible = " 303 compatible = "brcm,genet-mdio-v3";
304 #address-cells 304 #address-cells = <0x1>;
305 #size-cells = 305 #size-cells = <0x0>;
306 reg = <0xe14 0 306 reg = <0xe14 0x8>;
307 307
308 phy1: ethernet 308 phy1: ethernet-phy@1 {
309 max-sp 309 max-speed = <100>;
310 reg = 310 reg = <0x1>;
311 compat 311 compatible = "brcm,40nm-ephy",
312 312 "ethernet-phy-ieee802.3-c22";
313 }; 313 };
314 }; 314 };
315 }; 315 };
316 316
317 ehci0: usb@480300 { 317 ehci0: usb@480300 {
318 compatible = "brcm,bcm 318 compatible = "brcm,bcm7425-ehci", "generic-ehci";
319 reg = <0x480300 0x100> 319 reg = <0x480300 0x100>;
320 native-endian; 320 native-endian;
321 interrupt-parent = <&p 321 interrupt-parent = <&periph_intc>;
322 interrupts = <65>; 322 interrupts = <65>;
323 status = "disabled"; 323 status = "disabled";
324 }; 324 };
325 325
326 ohci0: usb@480400 { 326 ohci0: usb@480400 {
327 compatible = "brcm,bcm 327 compatible = "brcm,bcm7425-ohci", "generic-ohci";
328 reg = <0x480400 0x100> 328 reg = <0x480400 0x100>;
329 native-endian; 329 native-endian;
330 no-big-frame-no; 330 no-big-frame-no;
331 interrupt-parent = <&p 331 interrupt-parent = <&periph_intc>;
332 interrupts = <67>; 332 interrupts = <67>;
333 status = "disabled"; 333 status = "disabled";
334 }; 334 };
335 335
336 ehci1: usb@480500 { 336 ehci1: usb@480500 {
337 compatible = "brcm,bcm 337 compatible = "brcm,bcm7425-ehci", "generic-ehci";
338 reg = <0x480500 0x100> 338 reg = <0x480500 0x100>;
339 native-endian; 339 native-endian;
340 interrupt-parent = <&p 340 interrupt-parent = <&periph_intc>;
341 interrupts = <66>; 341 interrupts = <66>;
342 status = "disabled"; 342 status = "disabled";
343 }; 343 };
344 344
345 ohci1: usb@480600 { 345 ohci1: usb@480600 {
346 compatible = "brcm,bcm 346 compatible = "brcm,bcm7425-ohci", "generic-ohci";
347 reg = <0x480600 0x100> 347 reg = <0x480600 0x100>;
348 native-endian; 348 native-endian;
349 no-big-frame-no; 349 no-big-frame-no;
350 interrupt-parent = <&p 350 interrupt-parent = <&periph_intc>;
351 interrupts = <68>; 351 interrupts = <68>;
352 status = "disabled"; 352 status = "disabled";
353 }; 353 };
354 354
355 ehci2: usb@490300 { 355 ehci2: usb@490300 {
356 compatible = "brcm,bcm 356 compatible = "brcm,bcm7425-ehci", "generic-ehci";
357 reg = <0x490300 0x100> 357 reg = <0x490300 0x100>;
358 native-endian; 358 native-endian;
359 interrupt-parent = <&p 359 interrupt-parent = <&periph_intc>;
360 interrupts = <70>; 360 interrupts = <70>;
361 status = "disabled"; 361 status = "disabled";
362 }; 362 };
363 363
364 ohci2: usb@490400 { 364 ohci2: usb@490400 {
365 compatible = "brcm,bcm 365 compatible = "brcm,bcm7425-ohci", "generic-ohci";
366 reg = <0x490400 0x100> 366 reg = <0x490400 0x100>;
367 native-endian; 367 native-endian;
368 no-big-frame-no; 368 no-big-frame-no;
369 interrupt-parent = <&p 369 interrupt-parent = <&periph_intc>;
370 interrupts = <72>; 370 interrupts = <72>;
371 status = "disabled"; 371 status = "disabled";
372 }; 372 };
373 373
374 ehci3: usb@490500 { 374 ehci3: usb@490500 {
375 compatible = "brcm,bcm 375 compatible = "brcm,bcm7425-ehci", "generic-ehci";
376 reg = <0x490500 0x100> 376 reg = <0x490500 0x100>;
377 native-endian; 377 native-endian;
378 interrupt-parent = <&p 378 interrupt-parent = <&periph_intc>;
379 interrupts = <71>; 379 interrupts = <71>;
380 status = "disabled"; 380 status = "disabled";
381 }; 381 };
382 382
383 ohci3: usb@490600 { 383 ohci3: usb@490600 {
384 compatible = "brcm,bcm 384 compatible = "brcm,bcm7425-ohci", "generic-ohci";
385 reg = <0x490600 0x100> 385 reg = <0x490600 0x100>;
386 native-endian; 386 native-endian;
387 no-big-frame-no; 387 no-big-frame-no;
388 interrupt-parent = <&p 388 interrupt-parent = <&periph_intc>;
389 interrupts = <73>; 389 interrupts = <73>;
390 status = "disabled"; 390 status = "disabled";
391 }; 391 };
392 392
393 hif_l2_intc: interrupt-control 393 hif_l2_intc: interrupt-controller@41a000 {
394 compatible = "brcm,l2- 394 compatible = "brcm,l2-intc";
395 reg = <0x41a000 0x30>; 395 reg = <0x41a000 0x30>;
396 interrupt-controller; 396 interrupt-controller;
397 #interrupt-cells = <1> 397 #interrupt-cells = <1>;
398 interrupt-parent = <&p 398 interrupt-parent = <&periph_intc>;
399 interrupts = <24>; 399 interrupts = <24>;
400 }; 400 };
401 401
402 nand: nand@41b800 { 402 nand: nand@41b800 {
403 compatible = "brcm,brc 403 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
404 #address-cells = <1>; 404 #address-cells = <1>;
405 #size-cells = <0>; 405 #size-cells = <0>;
406 reg-names = "nand", "f 406 reg-names = "nand", "flash-edu";
407 reg = <0x41b800 0x400> 407 reg = <0x41b800 0x400>, <0x41bc00 0x24>;
408 interrupt-parent = <&h 408 interrupt-parent = <&hif_l2_intc>;
409 interrupts = <24>; 409 interrupts = <24>;
410 status = "disabled"; 410 status = "disabled";
411 }; 411 };
412 412
413 sata: sata@181000 { 413 sata: sata@181000 {
414 compatible = "brcm,bcm 414 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
415 reg-names = "ahci", "t 415 reg-names = "ahci", "top-ctrl";
416 reg = <0x181000 0xa9c> 416 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
417 interrupt-parent = <&p 417 interrupt-parent = <&periph_intc>;
418 interrupts = <41>; 418 interrupts = <41>;
419 #address-cells = <1>; 419 #address-cells = <1>;
420 #size-cells = <0>; 420 #size-cells = <0>;
421 status = "disabled"; 421 status = "disabled";
422 422
423 sata0: sata-port@0 { 423 sata0: sata-port@0 {
424 reg = <0>; 424 reg = <0>;
425 phys = <&sata_ 425 phys = <&sata_phy0>;
426 }; 426 };
427 427
428 sata1: sata-port@1 { 428 sata1: sata-port@1 {
429 reg = <1>; 429 reg = <1>;
430 phys = <&sata_ 430 phys = <&sata_phy1>;
431 }; 431 };
432 }; 432 };
433 433
434 sata_phy: sata-phy@180100 { 434 sata_phy: sata-phy@180100 {
435 compatible = "brcm,bcm 435 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
436 reg = <0x180100 0x0eff 436 reg = <0x180100 0x0eff>;
437 reg-names = "phy"; 437 reg-names = "phy";
438 #address-cells = <1>; 438 #address-cells = <1>;
439 #size-cells = <0>; 439 #size-cells = <0>;
440 status = "disabled"; 440 status = "disabled";
441 441
442 sata_phy0: sata-phy@0 442 sata_phy0: sata-phy@0 {
443 reg = <0>; 443 reg = <0>;
444 #phy-cells = < 444 #phy-cells = <0>;
445 }; 445 };
446 446
447 sata_phy1: sata-phy@1 447 sata_phy1: sata-phy@1 {
448 reg = <1>; 448 reg = <1>;
449 #phy-cells = < 449 #phy-cells = <0>;
450 }; 450 };
451 }; 451 };
452 452
453 sdhci0: sdhci@419000 { 453 sdhci0: sdhci@419000 {
454 compatible = "brcm,bcm 454 compatible = "brcm,bcm7425-sdhci";
455 reg = <0x419000 0x100> 455 reg = <0x419000 0x100>;
456 interrupt-parent = <&p 456 interrupt-parent = <&periph_intc>;
457 interrupts = <43>; 457 interrupts = <43>;
458 sd-uhs-sdr50; 458 sd-uhs-sdr50;
459 mmc-hs200-1_8v; 459 mmc-hs200-1_8v;
460 status = "disabled"; 460 status = "disabled";
461 }; 461 };
462 462
463 sdhci1: sdhci@419200 { 463 sdhci1: sdhci@419200 {
464 compatible = "brcm,bcm 464 compatible = "brcm,bcm7425-sdhci";
465 reg = <0x419200 0x100> 465 reg = <0x419200 0x100>;
466 interrupt-parent = <&p 466 interrupt-parent = <&periph_intc>;
467 interrupts = <44>; 467 interrupts = <44>;
468 sd-uhs-sdr50; 468 sd-uhs-sdr50;
469 mmc-hs200-1_8v; 469 mmc-hs200-1_8v;
470 status = "disabled"; 470 status = "disabled";
471 }; 471 };
472 472
473 spi_l2_intc: interrupt-control 473 spi_l2_intc: interrupt-controller@41ad00 {
474 compatible = "brcm,l2- 474 compatible = "brcm,l2-intc";
475 reg = <0x41ad00 0x30>; 475 reg = <0x41ad00 0x30>;
476 interrupt-controller; 476 interrupt-controller;
477 #interrupt-cells = <1> 477 #interrupt-cells = <1>;
478 interrupt-parent = <&p 478 interrupt-parent = <&periph_intc>;
479 interrupts = <25>; 479 interrupts = <25>;
480 }; 480 };
481 481
482 qspi: spi@41c000 { 482 qspi: spi@41c000 {
483 #address-cells = <0x1> 483 #address-cells = <0x1>;
484 #size-cells = <0x0>; 484 #size-cells = <0x0>;
485 compatible = "brcm,spi 485 compatible = "brcm,spi-bcm-qspi",
486 "brcm,spi 486 "brcm,spi-brcmstb-qspi";
487 clocks = <&upg_clk>; 487 clocks = <&upg_clk>;
488 reg = <0x419920 0x4 0x 488 reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
489 reg-names = "cs_reg", 489 reg-names = "cs_reg", "hif_mspi", "bspi";
490 interrupts = <0x0 0x1 490 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
491 interrupt-parent = <&s 491 interrupt-parent = <&spi_l2_intc>;
492 interrupt-names = "spi 492 interrupt-names = "spi_lr_fullness_reached",
493 "spi 493 "spi_lr_session_aborted",
494 "spi 494 "spi_lr_impatient",
495 "spi 495 "spi_lr_session_done",
496 "spi 496 "spi_lr_overread",
497 "msp 497 "mspi_done",
498 "msp 498 "mspi_halted";
499 status = "disabled"; 499 status = "disabled";
500 }; 500 };
501 501
502 mspi: spi@409200 { 502 mspi: spi@409200 {
503 #address-cells = <1>; 503 #address-cells = <1>;
504 #size-cells = <0>; 504 #size-cells = <0>;
505 compatible = "brcm,spi 505 compatible = "brcm,spi-bcm-qspi",
506 "brcm,spi 506 "brcm,spi-brcmstb-mspi";
507 clocks = <&upg_clk>; 507 clocks = <&upg_clk>;
508 reg = <0x409200 0x180> 508 reg = <0x409200 0x180>;
509 reg-names = "mspi"; 509 reg-names = "mspi";
510 interrupts = <0x14>; 510 interrupts = <0x14>;
511 interrupt-parent = <&u 511 interrupt-parent = <&upg_aon_irq0_intc>;
512 interrupt-names = "msp 512 interrupt-names = "mspi_done";
513 status = "disabled"; 513 status = "disabled";
514 }; 514 };
515 515
516 waketimer: waketimer@409580 { 516 waketimer: waketimer@409580 {
517 compatible = "brcm,brc 517 compatible = "brcm,brcmstb-waketimer";
518 reg = <0x409580 0x14>; 518 reg = <0x409580 0x14>;
519 interrupts = <0x3>; 519 interrupts = <0x3>;
520 interrupt-parent = <&a 520 interrupt-parent = <&aon_pm_l2_intc>;
521 interrupt-names = "tim 521 interrupt-names = "timer";
522 clocks = <&upg_clk>; 522 clocks = <&upg_clk>;
523 status = "disabled"; 523 status = "disabled";
524 }; 524 };
525 }; 525 };
526 526
527 memory_controllers { 527 memory_controllers {
528 compatible = "simple-bus"; 528 compatible = "simple-bus";
529 ranges = <0x0 0x103b0000 0x1a0 529 ranges = <0x0 0x103b0000 0x1a000>;
530 #address-cells = <1>; 530 #address-cells = <1>;
531 #size-cells = <1>; 531 #size-cells = <1>;
532 532
533 memory-controller@0 { 533 memory-controller@0 {
534 compatible = "brcm,brc 534 compatible = "brcm,brcmstb-memc", "simple-bus";
535 ranges = <0x0 0x0 0xa0 535 ranges = <0x0 0x0 0xa000>;
536 #address-cells = <1>; 536 #address-cells = <1>;
537 #size-cells = <1>; 537 #size-cells = <1>;
538 538
539 memc-arb@1000 { 539 memc-arb@1000 {
540 compatible = " 540 compatible = "brcm,brcmstb-memc-arb";
541 reg = <0x1000 541 reg = <0x1000 0x248>;
542 }; 542 };
543 543
544 memc-ddr@2000 { 544 memc-ddr@2000 {
545 compatible = " 545 compatible = "brcm,brcmstb-memc-ddr";
546 reg = <0x2000 546 reg = <0x2000 0x300>;
547 }; 547 };
548 548
549 ddr-phy@6000 { 549 ddr-phy@6000 {
550 compatible = " 550 compatible = "brcm,brcmstb-ddr-phy";
551 reg = <0x6000 551 reg = <0x6000 0xc8>;
552 }; 552 };
553 553
554 shimphy@8000 { 554 shimphy@8000 {
555 compatible = " 555 compatible = "brcm,brcmstb-ddr-shimphy";
556 reg = <0x8000 556 reg = <0x8000 0x13c>;
557 }; 557 };
558 }; 558 };
559 559
560 memory-controller@1 { 560 memory-controller@1 {
561 compatible = "brcm,brc 561 compatible = "brcm,brcmstb-memc", "simple-bus";
562 ranges = <0x0 0x10000 562 ranges = <0x0 0x10000 0xa000>;
563 #address-cells = <1>; 563 #address-cells = <1>;
564 #size-cells = <1>; 564 #size-cells = <1>;
565 565
566 memc-arb@1000 { 566 memc-arb@1000 {
567 compatible = " 567 compatible = "brcm,brcmstb-memc-arb";
568 reg = <0x1000 568 reg = <0x1000 0x248>;
569 }; 569 };
570 570
571 memc-ddr@2000 { 571 memc-ddr@2000 {
572 compatible = " 572 compatible = "brcm,brcmstb-memc-ddr";
573 reg = <0x2000 573 reg = <0x2000 0x300>;
574 }; 574 };
575 575
576 ddr-phy@6000 { 576 ddr-phy@6000 {
577 compatible = " 577 compatible = "brcm,brcmstb-ddr-phy";
578 reg = <0x6000 578 reg = <0x6000 0xc8>;
579 }; 579 };
580 580
581 shimphy@8000 { 581 shimphy@8000 {
582 compatible = " 582 compatible = "brcm,brcmstb-ddr-shimphy";
583 reg = <0x8000 583 reg = <0x8000 0x13c>;
584 }; 584 };
585 }; 585 };
586 }; 586 };
587 587
588 pcie_0: pcie@8b20000 { 588 pcie_0: pcie@8b20000 {
589 status = "disabled"; 589 status = "disabled";
590 compatible = "brcm,bcm7425-pci 590 compatible = "brcm,bcm7425-pcie";
591 591
592 ranges = <0x02000000 0x0 0xd00 592 ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000
593 0x02000000 0x0 0xd80 593 0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000
594 0x02000000 0x0 0xe00 594 0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000
595 0x02000000 0x0 0xe80 595 0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>;
596 596
597 reg = <0x10410000 0x19310>; 597 reg = <0x10410000 0x19310>;
598 aspm-no-l0s; 598 aspm-no-l0s;
599 device_type = "pci"; 599 device_type = "pci";
600 msi-controller; 600 msi-controller;
601 msi-parent = <&pcie_0>; 601 msi-parent = <&pcie_0>;
602 #address-cells = <0x3>; 602 #address-cells = <0x3>;
603 #size-cells = <0x2>; 603 #size-cells = <0x2>;
604 bus-range = <0x0 0xff>; 604 bus-range = <0x0 0xff>;
605 interrupt-map-mask = <0x0 0x0 605 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
606 linux,pci-domain = <0x0>; 606 linux,pci-domain = <0x0>;
607 607
608 interrupt-parent = <&periph_in 608 interrupt-parent = <&periph_intc>;
609 interrupts = <37>, <37>; 609 interrupts = <37>, <37>;
610 interrupt-names = "pcie", "msi 610 interrupt-names = "pcie", "msi";
611 #interrupt-cells = <0x1>; 611 #interrupt-cells = <0x1>;
612 interrupt-map = <0 0 0 1 &peri 612 interrupt-map = <0 0 0 1 &periph_intc 0x21
613 0 0 0 1 &peri 613 0 0 0 1 &periph_intc 0x22
614 0 0 0 1 &peri 614 0 0 0 1 &periph_intc 0x23
615 0 0 0 1 &peri 615 0 0 0 1 &periph_intc 0x24>;
616 }; 616 };
617 }; 617 };
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