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Linux/scripts/dtc/include-prefixes/mips/brcm/bcm97360svmb.dts

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Diff markup

Differences between /scripts/dtc/include-prefixes/mips/brcm/bcm97360svmb.dts (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/mips/brcm/bcm97360svmb.dts (Version linux-6.6.60)


  1 // SPDX-License-Identifier: GPL-2.0                 1 // SPDX-License-Identifier: GPL-2.0
  2 /dts-v1/;                                           2 /dts-v1/;
  3                                                     3 
  4 #include "bcm7360.dtsi"                             4 #include "bcm7360.dtsi"
  5                                                     5 
  6 / {                                                 6 / {
  7         compatible = "brcm,bcm97360svmb", "brc      7         compatible = "brcm,bcm97360svmb", "brcm,bcm7360";
  8         model = "Broadcom BCM97360SVMB";            8         model = "Broadcom BCM97360SVMB";
  9                                                     9 
 10         memory@0 {                                 10         memory@0 {
 11                 device_type = "memory";            11                 device_type = "memory";
 12                 reg = <0x00000000 0x10000000>;     12                 reg = <0x00000000 0x10000000>;
 13         };                                         13         };
 14                                                    14 
 15         chosen {                                   15         chosen {
 16                 bootargs = "console=ttyS0,1152     16                 bootargs = "console=ttyS0,115200";
 17                 stdout-path = &uart0;              17                 stdout-path = &uart0;
 18         };                                         18         };
 19 };                                                 19 };
 20                                                    20 
 21 &uart0 {                                           21 &uart0 {
 22         status = "okay";                           22         status = "okay";
 23 };                                                 23 };
 24                                                    24 
 25 &uart1 {                                           25 &uart1 {
 26         status = "okay";                           26         status = "okay";
 27 };                                                 27 };
 28                                                    28 
 29 &uart2 {                                           29 &uart2 {
 30         status = "okay";                           30         status = "okay";
 31 };                                                 31 };
 32                                                    32 
 33 &bsca {                                            33 &bsca {
 34         status = "okay";                           34         status = "okay";
 35 };                                                 35 };
 36                                                    36 
 37 &bscb {                                            37 &bscb {
 38         status = "okay";                           38         status = "okay";
 39 };                                                 39 };
 40                                                    40 
 41 &bscc {                                            41 &bscc {
 42         status = "okay";                           42         status = "okay";
 43 };                                                 43 };
 44                                                    44 
 45 &bscd {                                            45 &bscd {
 46         status = "okay";                           46         status = "okay";
 47 };                                                 47 };
 48                                                    48 
 49 &pwma {                                            49 &pwma {
 50         status = "okay";                           50         status = "okay";
 51 };                                                 51 };
 52                                                    52 
 53 &watchdog {                                        53 &watchdog {
 54         status = "okay";                           54         status = "okay";
 55 };                                                 55 };
 56                                                    56 
 57 &enet0 {                                           57 &enet0 {
 58         status = "okay";                           58         status = "okay";
 59 };                                                 59 };
 60                                                    60 
 61 &ehci0 {                                           61 &ehci0 {
 62         status = "okay";                           62         status = "okay";
 63 };                                                 63 };
 64                                                    64 
 65 &ohci0 {                                           65 &ohci0 {
 66         status = "okay";                           66         status = "okay";
 67 };                                                 67 };
 68                                                    68 
 69 &sata {                                            69 &sata {
 70         status = "okay";                           70         status = "okay";
 71 };                                                 71 };
 72                                                    72 
 73 &sata_phy {                                        73 &sata_phy {
 74         status = "okay";                           74         status = "okay";
 75 };                                                 75 };
 76                                                    76 
 77 &sdhci0 {                                          77 &sdhci0 {
 78         status = "okay";                           78         status = "okay";
 79 };                                                 79 };
 80                                                    80 
 81 &qspi {                                            81 &qspi {
 82         status = "okay";                           82         status = "okay";
 83                                                    83 
 84         flash@0 {                                  84         flash@0 {
 85                 compatible = "m25p80";             85                 compatible = "m25p80";
 86                 reg = <0>;                         86                 reg = <0>;
 87                 spi-max-frequency = <40000000>     87                 spi-max-frequency = <40000000>;
 88                 spi-cpol;                          88                 spi-cpol;
 89                 spi-cpha;                          89                 spi-cpha;
 90                 use-bspi;                          90                 use-bspi;
 91                 m25p,fast-read;                    91                 m25p,fast-read;
 92                                                    92 
 93                 partitions {                       93                 partitions {
 94                         compatible = "fixed-pa     94                         compatible = "fixed-partitions";
 95                         #address-cells = <1>;      95                         #address-cells = <1>;
 96                         #size-cells = <1>;         96                         #size-cells = <1>;
 97                                                    97 
 98                         flash0.cfe@0 {             98                         flash0.cfe@0 {
 99                                 reg = <0x0 0x2     99                                 reg = <0x0 0x200000>;
100                         };                        100                         };
101                                                   101 
102                         flash0.mac@200000 {       102                         flash0.mac@200000 {
103                                 reg = <0x20000    103                                 reg = <0x200000 0x40000>;
104                         };                        104                         };
105                                                   105 
106                         flash0.nvram@240000 {     106                         flash0.nvram@240000 {
107                                 reg = <0x24000    107                                 reg = <0x240000 0x10000>;
108                         };                        108                         };
109                 };                                109                 };
110         };                                        110         };
111 };                                                111 };
112                                                   112 
113 &mspi {                                           113 &mspi {
114         status = "okay";                          114         status = "okay";
115 };                                                115 };
116                                                   116 
117 &waketimer {                                      117 &waketimer {
118         status = "okay";                          118         status = "okay";
119 };                                                119 };
                                                      

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