1 // SPDX-License-Identifier: GPL-2.0 <<
2 /dts-v1/; 1 /dts-v1/;
3 2
4 #include <dt-bindings/clock/boston-clock.h> 3 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h> 4 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq 5 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mip 6 #include <dt-bindings/interrupt-controller/mips-gic.h>
8 7
9 / { 8 / {
10 #address-cells = <1>; 9 #address-cells = <1>;
11 #size-cells = <1>; 10 #size-cells = <1>;
12 compatible = "img,boston"; 11 compatible = "img,boston";
13 12
14 chosen { 13 chosen {
15 stdout-path = "uart0:115200"; 14 stdout-path = "uart0:115200";
16 }; 15 };
17 16
18 aliases { 17 aliases {
19 uart0 = &uart0; 18 uart0 = &uart0;
20 }; 19 };
21 20
22 cpus { 21 cpus {
23 #address-cells = <1>; 22 #address-cells = <1>;
24 #size-cells = <0>; 23 #size-cells = <0>;
25 24
26 cpu@0 { 25 cpu@0 {
27 device_type = "cpu"; 26 device_type = "cpu";
28 compatible = "img,mips 27 compatible = "img,mips";
29 reg = <0>; 28 reg = <0>;
30 clocks = <&clk_boston 29 clocks = <&clk_boston BOSTON_CLK_CPU>;
31 }; 30 };
32 }; 31 };
33 32
34 memory@0 { 33 memory@0 {
35 device_type = "memory"; 34 device_type = "memory";
36 reg = <0x00000000 0x10000000>; 35 reg = <0x00000000 0x10000000>;
37 }; 36 };
38 37
39 pci0: pci@10000000 { 38 pci0: pci@10000000 {
40 compatible = "xlnx,axi-pcie-ho 39 compatible = "xlnx,axi-pcie-host-1.00.a";
41 device_type = "pci"; 40 device_type = "pci";
42 reg = <0x10000000 0x2000000>; 41 reg = <0x10000000 0x2000000>;
43 42
44 #address-cells = <3>; 43 #address-cells = <3>;
45 #size-cells = <2>; 44 #size-cells = <2>;
46 #interrupt-cells = <1>; 45 #interrupt-cells = <1>;
47 46
48 interrupt-parent = <&gic>; 47 interrupt-parent = <&gic>;
49 interrupts = <GIC_SHARED 2 IRQ 48 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
50 49
51 ranges = <0x02000000 0 0x40000 50 ranges = <0x02000000 0 0x40000000
52 0x40000000 0 0x40000 51 0x40000000 0 0x40000000>;
53 52
54 bus-range = <0x00 0xff>; <<
55 <<
56 interrupt-map-mask = <0 0 0 7> 53 interrupt-map-mask = <0 0 0 7>;
57 interrupt-map = <0 0 0 1 &pci0 54 interrupt-map = <0 0 0 1 &pci0_intc 1>,
58 <0 0 0 2 &pci0 55 <0 0 0 2 &pci0_intc 2>,
59 <0 0 0 3 &pci0 56 <0 0 0 3 &pci0_intc 3>,
60 <0 0 0 4 &pci0 57 <0 0 0 4 &pci0_intc 4>;
61 58
62 pci0_intc: interrupt-controlle 59 pci0_intc: interrupt-controller {
63 interrupt-controller; 60 interrupt-controller;
64 #address-cells = <0>; 61 #address-cells = <0>;
65 #interrupt-cells = <1> 62 #interrupt-cells = <1>;
66 }; 63 };
67 }; 64 };
68 65
69 pci1: pci@12000000 { 66 pci1: pci@12000000 {
70 compatible = "xlnx,axi-pcie-ho 67 compatible = "xlnx,axi-pcie-host-1.00.a";
71 device_type = "pci"; 68 device_type = "pci";
72 reg = <0x12000000 0x2000000>; 69 reg = <0x12000000 0x2000000>;
73 70
74 #address-cells = <3>; 71 #address-cells = <3>;
75 #size-cells = <2>; 72 #size-cells = <2>;
76 #interrupt-cells = <1>; 73 #interrupt-cells = <1>;
77 74
78 interrupt-parent = <&gic>; 75 interrupt-parent = <&gic>;
79 interrupts = <GIC_SHARED 1 IRQ 76 interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
80 77
81 ranges = <0x02000000 0 0x20000 78 ranges = <0x02000000 0 0x20000000
82 0x20000000 0 0x20000 79 0x20000000 0 0x20000000>;
83 80
84 bus-range = <0x00 0xff>; <<
85 <<
86 interrupt-map-mask = <0 0 0 7> 81 interrupt-map-mask = <0 0 0 7>;
87 interrupt-map = <0 0 0 1 &pci1 82 interrupt-map = <0 0 0 1 &pci1_intc 1>,
88 <0 0 0 2 &pci1 83 <0 0 0 2 &pci1_intc 2>,
89 <0 0 0 3 &pci1 84 <0 0 0 3 &pci1_intc 3>,
90 <0 0 0 4 &pci1 85 <0 0 0 4 &pci1_intc 4>;
91 86
92 pci1_intc: interrupt-controlle 87 pci1_intc: interrupt-controller {
93 interrupt-controller; 88 interrupt-controller;
94 #address-cells = <0>; 89 #address-cells = <0>;
95 #interrupt-cells = <1> 90 #interrupt-cells = <1>;
96 }; 91 };
97 }; 92 };
98 93
99 pci2: pci@14000000 { 94 pci2: pci@14000000 {
100 compatible = "xlnx,axi-pcie-ho 95 compatible = "xlnx,axi-pcie-host-1.00.a";
101 device_type = "pci"; 96 device_type = "pci";
102 reg = <0x14000000 0x2000000>; 97 reg = <0x14000000 0x2000000>;
103 98
104 #address-cells = <3>; 99 #address-cells = <3>;
105 #size-cells = <2>; 100 #size-cells = <2>;
106 #interrupt-cells = <1>; 101 #interrupt-cells = <1>;
107 102
108 interrupt-parent = <&gic>; 103 interrupt-parent = <&gic>;
109 interrupts = <GIC_SHARED 0 IRQ 104 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
110 105
111 ranges = <0x02000000 0 0x16000 106 ranges = <0x02000000 0 0x16000000
112 0x16000000 0 0x10000 107 0x16000000 0 0x100000>;
113 108
114 bus-range = <0x00 0xff>; <<
115 <<
116 interrupt-map-mask = <0 0 0 7> 109 interrupt-map-mask = <0 0 0 7>;
117 interrupt-map = <0 0 0 1 &pci2 110 interrupt-map = <0 0 0 1 &pci2_intc 1>,
118 <0 0 0 2 &pci2 111 <0 0 0 2 &pci2_intc 2>,
119 <0 0 0 3 &pci2 112 <0 0 0 3 &pci2_intc 3>,
120 <0 0 0 4 &pci2 113 <0 0 0 4 &pci2_intc 4>;
121 114
122 pci2_intc: interrupt-controlle 115 pci2_intc: interrupt-controller {
123 interrupt-controller; 116 interrupt-controller;
124 #address-cells = <0>; 117 #address-cells = <0>;
125 #interrupt-cells = <1> 118 #interrupt-cells = <1>;
126 }; 119 };
127 120
128 pci2_root@0,0 { !! 121 pci2_root@0,0,0 {
129 compatible = "pci10ee, 122 compatible = "pci10ee,7021";
130 reg = <0x00000000 0 0 123 reg = <0x00000000 0 0 0 0>;
131 124
132 #address-cells = <3>; 125 #address-cells = <3>;
133 #size-cells = <2>; 126 #size-cells = <2>;
134 #interrupt-cells = <1> 127 #interrupt-cells = <1>;
135 128
136 eg20t_bridge@1,0,0 { 129 eg20t_bridge@1,0,0 {
137 compatible = " 130 compatible = "pci8086,8800";
138 reg = <0x00010 131 reg = <0x00010000 0 0 0 0>;
139 132
140 #address-cells 133 #address-cells = <3>;
141 #size-cells = 134 #size-cells = <2>;
142 #interrupt-cel 135 #interrupt-cells = <1>;
143 136
144 eg20t_phub@2,0 <<
145 compat <<
146 reg = <<
147 intel, <<
148 }; <<
149 <<
150 eg20t_mac@2,0, 137 eg20t_mac@2,0,1 {
151 compat 138 compatible = "pci8086,8802";
152 reg = 139 reg = <0x00020100 0 0 0 0>;
153 phy-re 140 phy-reset-gpios = <&eg20t_gpio 6
154 141 GPIO_ACTIVE_LOW>;
155 }; 142 };
156 143
157 eg20t_gpio: eg 144 eg20t_gpio: eg20t_gpio@2,0,2 {
158 compat 145 compatible = "pci8086,8803";
159 reg = 146 reg = <0x00020200 0 0 0 0>;
160 147
161 gpio-c 148 gpio-controller;
162 #gpio- 149 #gpio-cells = <2>;
163 }; 150 };
164 151
165 eg20t_i2c@2,12 152 eg20t_i2c@2,12,2 {
166 compat 153 compatible = "pci8086,8817";
167 reg = 154 reg = <0x00026200 0 0 0 0>;
168 155
169 #addre 156 #address-cells = <1>;
170 #size- 157 #size-cells = <0>;
171 158
172 rtc@68 !! 159 rtc@0x68 {
173 160 compatible = "st,m41t81s";
174 161 reg = <0x68>;
175 }; 162 };
176 }; 163 };
177 }; 164 };
178 }; 165 };
179 }; 166 };
180 167
181 gic: interrupt-controller@16120000 { 168 gic: interrupt-controller@16120000 {
182 compatible = "mti,gic"; 169 compatible = "mti,gic";
183 reg = <0x16120000 0x20000>; 170 reg = <0x16120000 0x20000>;
184 171
185 interrupt-controller; 172 interrupt-controller;
186 #interrupt-cells = <3>; 173 #interrupt-cells = <3>;
187 174
188 timer { 175 timer {
189 compatible = "mti,gic- 176 compatible = "mti,gic-timer";
190 interrupts = <GIC_LOCA 177 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
191 clocks = <&clk_boston 178 clocks = <&clk_boston BOSTON_CLK_CPU>;
192 }; 179 };
193 }; 180 };
194 181
195 cdmm@16140000 { 182 cdmm@16140000 {
196 compatible = "mti,mips-cdmm"; 183 compatible = "mti,mips-cdmm";
197 reg = <0x16140000 0x8000>; 184 reg = <0x16140000 0x8000>;
198 }; 185 };
199 186
200 cpc@16200000 { 187 cpc@16200000 {
201 compatible = "mti,mips-cpc"; 188 compatible = "mti,mips-cpc";
202 reg = <0x16200000 0x8000>; 189 reg = <0x16200000 0x8000>;
203 }; 190 };
204 191
205 plat_regs: system-controller@17ffd000 192 plat_regs: system-controller@17ffd000 {
206 compatible = "img,boston-platf 193 compatible = "img,boston-platform-regs", "syscon";
207 reg = <0x17ffd000 0x1000>; 194 reg = <0x17ffd000 0x1000>;
208 195
209 clk_boston: clock { 196 clk_boston: clock {
210 compatible = "img,bost 197 compatible = "img,boston-clock";
211 #clock-cells = <1>; 198 #clock-cells = <1>;
212 }; 199 };
213 }; 200 };
214 201
215 reboot: syscon-reboot { 202 reboot: syscon-reboot {
216 compatible = "syscon-reboot"; 203 compatible = "syscon-reboot";
217 regmap = <&plat_regs>; 204 regmap = <&plat_regs>;
218 offset = <0x10>; 205 offset = <0x10>;
219 mask = <0x10>; 206 mask = <0x10>;
220 }; 207 };
221 208
222 uart0: uart@17ffe000 { 209 uart0: uart@17ffe000 {
223 compatible = "ns16550a"; 210 compatible = "ns16550a";
224 reg = <0x17ffe000 0x1000>; 211 reg = <0x17ffe000 0x1000>;
225 reg-shift = <2>; 212 reg-shift = <2>;
226 213
227 interrupt-parent = <&gic>; 214 interrupt-parent = <&gic>;
228 interrupts = <GIC_SHARED 3 IRQ 215 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
229 216
230 clocks = <&clk_boston BOSTON_C 217 clocks = <&clk_boston BOSTON_CLK_SYS>;
231 }; 218 };
232 219
233 lcd: lcd@17fff000 { 220 lcd: lcd@17fff000 {
234 compatible = "img,boston-lcd"; 221 compatible = "img,boston-lcd";
235 reg = <0x17fff000 0x8>; 222 reg = <0x17fff000 0x8>;
236 }; 223 };
237 }; 224 };
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