1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/clock/boston-clock.h> 4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h> 5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq 6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mip 7 #include <dt-bindings/interrupt-controller/mips-gic.h>
8 8
9 / { 9 / {
10 #address-cells = <1>; 10 #address-cells = <1>;
11 #size-cells = <1>; 11 #size-cells = <1>;
12 compatible = "img,boston"; 12 compatible = "img,boston";
13 13
14 chosen { 14 chosen {
15 stdout-path = "uart0:115200"; 15 stdout-path = "uart0:115200";
16 }; 16 };
17 17
18 aliases { 18 aliases {
19 uart0 = &uart0; 19 uart0 = &uart0;
20 }; 20 };
21 21
22 cpus { 22 cpus {
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <0>; 24 #size-cells = <0>;
25 25
26 cpu@0 { 26 cpu@0 {
27 device_type = "cpu"; 27 device_type = "cpu";
28 compatible = "img,mips 28 compatible = "img,mips";
29 reg = <0>; 29 reg = <0>;
30 clocks = <&clk_boston 30 clocks = <&clk_boston BOSTON_CLK_CPU>;
31 }; 31 };
32 }; 32 };
33 33
34 memory@0 { 34 memory@0 {
35 device_type = "memory"; 35 device_type = "memory";
36 reg = <0x00000000 0x10000000>; 36 reg = <0x00000000 0x10000000>;
37 }; 37 };
38 38
39 pci0: pci@10000000 { 39 pci0: pci@10000000 {
40 compatible = "xlnx,axi-pcie-ho 40 compatible = "xlnx,axi-pcie-host-1.00.a";
41 device_type = "pci"; 41 device_type = "pci";
42 reg = <0x10000000 0x2000000>; 42 reg = <0x10000000 0x2000000>;
43 43
44 #address-cells = <3>; 44 #address-cells = <3>;
45 #size-cells = <2>; 45 #size-cells = <2>;
46 #interrupt-cells = <1>; 46 #interrupt-cells = <1>;
47 47
48 interrupt-parent = <&gic>; 48 interrupt-parent = <&gic>;
49 interrupts = <GIC_SHARED 2 IRQ 49 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
50 50
51 ranges = <0x02000000 0 0x40000 51 ranges = <0x02000000 0 0x40000000
52 0x40000000 0 0x40000 52 0x40000000 0 0x40000000>;
53 53
54 bus-range = <0x00 0xff>; <<
55 <<
56 interrupt-map-mask = <0 0 0 7> 54 interrupt-map-mask = <0 0 0 7>;
57 interrupt-map = <0 0 0 1 &pci0 55 interrupt-map = <0 0 0 1 &pci0_intc 1>,
58 <0 0 0 2 &pci0 56 <0 0 0 2 &pci0_intc 2>,
59 <0 0 0 3 &pci0 57 <0 0 0 3 &pci0_intc 3>,
60 <0 0 0 4 &pci0 58 <0 0 0 4 &pci0_intc 4>;
61 59
62 pci0_intc: interrupt-controlle 60 pci0_intc: interrupt-controller {
63 interrupt-controller; 61 interrupt-controller;
64 #address-cells = <0>; 62 #address-cells = <0>;
65 #interrupt-cells = <1> 63 #interrupt-cells = <1>;
66 }; 64 };
67 }; 65 };
68 66
69 pci1: pci@12000000 { 67 pci1: pci@12000000 {
70 compatible = "xlnx,axi-pcie-ho 68 compatible = "xlnx,axi-pcie-host-1.00.a";
71 device_type = "pci"; 69 device_type = "pci";
72 reg = <0x12000000 0x2000000>; 70 reg = <0x12000000 0x2000000>;
73 71
74 #address-cells = <3>; 72 #address-cells = <3>;
75 #size-cells = <2>; 73 #size-cells = <2>;
76 #interrupt-cells = <1>; 74 #interrupt-cells = <1>;
77 75
78 interrupt-parent = <&gic>; 76 interrupt-parent = <&gic>;
79 interrupts = <GIC_SHARED 1 IRQ 77 interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
80 78
81 ranges = <0x02000000 0 0x20000 79 ranges = <0x02000000 0 0x20000000
82 0x20000000 0 0x20000 80 0x20000000 0 0x20000000>;
83 81
84 bus-range = <0x00 0xff>; <<
85 <<
86 interrupt-map-mask = <0 0 0 7> 82 interrupt-map-mask = <0 0 0 7>;
87 interrupt-map = <0 0 0 1 &pci1 83 interrupt-map = <0 0 0 1 &pci1_intc 1>,
88 <0 0 0 2 &pci1 84 <0 0 0 2 &pci1_intc 2>,
89 <0 0 0 3 &pci1 85 <0 0 0 3 &pci1_intc 3>,
90 <0 0 0 4 &pci1 86 <0 0 0 4 &pci1_intc 4>;
91 87
92 pci1_intc: interrupt-controlle 88 pci1_intc: interrupt-controller {
93 interrupt-controller; 89 interrupt-controller;
94 #address-cells = <0>; 90 #address-cells = <0>;
95 #interrupt-cells = <1> 91 #interrupt-cells = <1>;
96 }; 92 };
97 }; 93 };
98 94
99 pci2: pci@14000000 { 95 pci2: pci@14000000 {
100 compatible = "xlnx,axi-pcie-ho 96 compatible = "xlnx,axi-pcie-host-1.00.a";
101 device_type = "pci"; 97 device_type = "pci";
102 reg = <0x14000000 0x2000000>; 98 reg = <0x14000000 0x2000000>;
103 99
104 #address-cells = <3>; 100 #address-cells = <3>;
105 #size-cells = <2>; 101 #size-cells = <2>;
106 #interrupt-cells = <1>; 102 #interrupt-cells = <1>;
107 103
108 interrupt-parent = <&gic>; 104 interrupt-parent = <&gic>;
109 interrupts = <GIC_SHARED 0 IRQ 105 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
110 106
111 ranges = <0x02000000 0 0x16000 107 ranges = <0x02000000 0 0x16000000
112 0x16000000 0 0x10000 108 0x16000000 0 0x100000>;
113 109
114 bus-range = <0x00 0xff>; <<
115 <<
116 interrupt-map-mask = <0 0 0 7> 110 interrupt-map-mask = <0 0 0 7>;
117 interrupt-map = <0 0 0 1 &pci2 111 interrupt-map = <0 0 0 1 &pci2_intc 1>,
118 <0 0 0 2 &pci2 112 <0 0 0 2 &pci2_intc 2>,
119 <0 0 0 3 &pci2 113 <0 0 0 3 &pci2_intc 3>,
120 <0 0 0 4 &pci2 114 <0 0 0 4 &pci2_intc 4>;
121 115
122 pci2_intc: interrupt-controlle 116 pci2_intc: interrupt-controller {
123 interrupt-controller; 117 interrupt-controller;
124 #address-cells = <0>; 118 #address-cells = <0>;
125 #interrupt-cells = <1> 119 #interrupt-cells = <1>;
126 }; 120 };
127 121
128 pci2_root@0,0 { !! 122 pci2_root@0,0,0 {
129 compatible = "pci10ee, 123 compatible = "pci10ee,7021";
130 reg = <0x00000000 0 0 124 reg = <0x00000000 0 0 0 0>;
131 125
132 #address-cells = <3>; 126 #address-cells = <3>;
133 #size-cells = <2>; 127 #size-cells = <2>;
134 #interrupt-cells = <1> 128 #interrupt-cells = <1>;
135 129
136 eg20t_bridge@1,0,0 { 130 eg20t_bridge@1,0,0 {
137 compatible = " 131 compatible = "pci8086,8800";
138 reg = <0x00010 132 reg = <0x00010000 0 0 0 0>;
139 133
140 #address-cells 134 #address-cells = <3>;
141 #size-cells = 135 #size-cells = <2>;
142 #interrupt-cel 136 #interrupt-cells = <1>;
143 137
144 eg20t_phub@2,0 <<
145 compat <<
146 reg = <<
147 intel, <<
148 }; <<
149 <<
150 eg20t_mac@2,0, 138 eg20t_mac@2,0,1 {
151 compat 139 compatible = "pci8086,8802";
152 reg = 140 reg = <0x00020100 0 0 0 0>;
153 phy-re 141 phy-reset-gpios = <&eg20t_gpio 6
154 142 GPIO_ACTIVE_LOW>;
155 }; 143 };
156 144
157 eg20t_gpio: eg 145 eg20t_gpio: eg20t_gpio@2,0,2 {
158 compat 146 compatible = "pci8086,8803";
159 reg = 147 reg = <0x00020200 0 0 0 0>;
160 148
161 gpio-c 149 gpio-controller;
162 #gpio- 150 #gpio-cells = <2>;
163 }; 151 };
164 152
165 eg20t_i2c@2,12 153 eg20t_i2c@2,12,2 {
166 compat 154 compatible = "pci8086,8817";
167 reg = 155 reg = <0x00026200 0 0 0 0>;
168 156
169 #addre 157 #address-cells = <1>;
170 #size- 158 #size-cells = <0>;
171 159
172 rtc@68 !! 160 rtc@0x68 {
173 161 compatible = "st,m41t81s";
174 162 reg = <0x68>;
175 }; 163 };
176 }; 164 };
177 }; 165 };
178 }; 166 };
179 }; 167 };
180 168
181 gic: interrupt-controller@16120000 { 169 gic: interrupt-controller@16120000 {
182 compatible = "mti,gic"; 170 compatible = "mti,gic";
183 reg = <0x16120000 0x20000>; 171 reg = <0x16120000 0x20000>;
184 172
185 interrupt-controller; 173 interrupt-controller;
186 #interrupt-cells = <3>; 174 #interrupt-cells = <3>;
187 175
188 timer { 176 timer {
189 compatible = "mti,gic- 177 compatible = "mti,gic-timer";
190 interrupts = <GIC_LOCA 178 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
191 clocks = <&clk_boston 179 clocks = <&clk_boston BOSTON_CLK_CPU>;
192 }; 180 };
193 }; 181 };
194 182
195 cdmm@16140000 { 183 cdmm@16140000 {
196 compatible = "mti,mips-cdmm"; 184 compatible = "mti,mips-cdmm";
197 reg = <0x16140000 0x8000>; 185 reg = <0x16140000 0x8000>;
198 }; 186 };
199 187
200 cpc@16200000 { 188 cpc@16200000 {
201 compatible = "mti,mips-cpc"; 189 compatible = "mti,mips-cpc";
202 reg = <0x16200000 0x8000>; 190 reg = <0x16200000 0x8000>;
203 }; 191 };
204 192
205 plat_regs: system-controller@17ffd000 193 plat_regs: system-controller@17ffd000 {
206 compatible = "img,boston-platf 194 compatible = "img,boston-platform-regs", "syscon";
207 reg = <0x17ffd000 0x1000>; 195 reg = <0x17ffd000 0x1000>;
208 196
209 clk_boston: clock { 197 clk_boston: clock {
210 compatible = "img,bost 198 compatible = "img,boston-clock";
211 #clock-cells = <1>; 199 #clock-cells = <1>;
212 }; 200 };
213 }; 201 };
214 202
215 reboot: syscon-reboot { 203 reboot: syscon-reboot {
216 compatible = "syscon-reboot"; 204 compatible = "syscon-reboot";
217 regmap = <&plat_regs>; 205 regmap = <&plat_regs>;
218 offset = <0x10>; 206 offset = <0x10>;
219 mask = <0x10>; 207 mask = <0x10>;
220 }; 208 };
221 209
222 uart0: uart@17ffe000 { 210 uart0: uart@17ffe000 {
223 compatible = "ns16550a"; 211 compatible = "ns16550a";
224 reg = <0x17ffe000 0x1000>; 212 reg = <0x17ffe000 0x1000>;
225 reg-shift = <2>; 213 reg-shift = <2>;
226 214
227 interrupt-parent = <&gic>; 215 interrupt-parent = <&gic>;
228 interrupts = <GIC_SHARED 3 IRQ 216 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
229 217
230 clocks = <&clk_boston BOSTON_C 218 clocks = <&clk_boston BOSTON_CLK_SYS>;
231 }; 219 };
232 220
233 lcd: lcd@17fff000 { 221 lcd: lcd@17fff000 {
234 compatible = "img,boston-lcd"; 222 compatible = "img,boston-lcd";
235 reg = <0x17fff000 0x8>; 223 reg = <0x17fff000 0x8>;
236 }; 224 };
237 }; 225 };
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