1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h> 2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1830-cgu. !! 3 #include <dt-bindings/clock/x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h> 4 #include <dt-bindings/dma/x1830-dma.h>
5 5
6 / { 6 / {
7 #address-cells = <1>; 7 #address-cells = <1>;
8 #size-cells = <1>; 8 #size-cells = <1>;
9 compatible = "ingenic,x1830"; 9 compatible = "ingenic,x1830";
10 10
11 cpus { 11 cpus {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <0>; 13 #size-cells = <0>;
14 14
15 cpu0: cpu@0 { 15 cpu0: cpu@0 {
16 device_type = "cpu"; 16 device_type = "cpu";
17 compatible = "ingenic, 17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>; 18 reg = <0>;
19 19
20 clocks = <&cgu X1830_C 20 clocks = <&cgu X1830_CLK_CPU>;
21 clock-names = "cpu"; 21 clock-names = "cpu";
22 }; 22 };
23 }; 23 };
24 24
25 cpuintc: interrupt-controller { 25 cpuintc: interrupt-controller {
26 #address-cells = <0>; 26 #address-cells = <0>;
27 #interrupt-cells = <1>; 27 #interrupt-cells = <1>;
28 interrupt-controller; 28 interrupt-controller;
29 compatible = "mti,cpu-interrup 29 compatible = "mti,cpu-interrupt-controller";
30 }; 30 };
31 31
32 intc: interrupt-controller@10001000 { 32 intc: interrupt-controller@10001000 {
33 compatible = "ingenic,x1830-in 33 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
34 reg = <0x10001000 0x50>; 34 reg = <0x10001000 0x50>;
35 35
36 interrupt-controller; 36 interrupt-controller;
37 #interrupt-cells = <1>; 37 #interrupt-cells = <1>;
38 38
39 interrupt-parent = <&cpuintc>; 39 interrupt-parent = <&cpuintc>;
40 interrupts = <2>; 40 interrupts = <2>;
41 }; 41 };
42 42
43 exclk: ext { 43 exclk: ext {
44 compatible = "fixed-clock"; 44 compatible = "fixed-clock";
45 #clock-cells = <0>; 45 #clock-cells = <0>;
46 }; 46 };
47 47
48 rtclk: rtc { 48 rtclk: rtc {
49 compatible = "fixed-clock"; 49 compatible = "fixed-clock";
50 #clock-cells = <0>; 50 #clock-cells = <0>;
51 clock-frequency = <32768>; 51 clock-frequency = <32768>;
52 }; 52 };
53 53
54 cgu: x1830-cgu@10000000 { 54 cgu: x1830-cgu@10000000 {
55 compatible = "ingenic,x1830-cg 55 compatible = "ingenic,x1830-cgu", "simple-mfd";
56 reg = <0x10000000 0x100>; 56 reg = <0x10000000 0x100>;
57 #address-cells = <1>; 57 #address-cells = <1>;
58 #size-cells = <1>; 58 #size-cells = <1>;
59 ranges = <0x0 0x10000000 0x100 59 ranges = <0x0 0x10000000 0x100>;
60 60
61 #clock-cells = <1>; 61 #clock-cells = <1>;
62 62
63 clocks = <&exclk>, <&rtclk>; 63 clocks = <&exclk>, <&rtclk>;
64 clock-names = "ext", "rtc"; 64 clock-names = "ext", "rtc";
65 65
66 otg_phy: usb-phy@3c { 66 otg_phy: usb-phy@3c {
67 compatible = "ingenic, 67 compatible = "ingenic,x1830-phy";
68 reg = <0x3c 0x10>; 68 reg = <0x3c 0x10>;
69 69
70 clocks = <&cgu X1830_C 70 clocks = <&cgu X1830_CLK_OTGPHY>;
71 71
72 #phy-cells = <0>; 72 #phy-cells = <0>;
73 73
74 status = "disabled"; 74 status = "disabled";
75 }; 75 };
76 <<
77 mac_phy_ctrl: mac-phy-ctrl@e8 <<
78 compatible = "syscon"; <<
79 reg = <0xe8 0x4>; <<
80 }; <<
81 }; 76 };
82 77
83 ost: timer@12000000 { 78 ost: timer@12000000 {
84 compatible = "ingenic,x1830-os 79 compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
85 reg = <0x12000000 0x3c>; 80 reg = <0x12000000 0x3c>;
86 81
87 #clock-cells = <1>; 82 #clock-cells = <1>;
88 83
89 clocks = <&cgu X1830_CLK_OST>; 84 clocks = <&cgu X1830_CLK_OST>;
90 clock-names = "ost"; 85 clock-names = "ost";
91 86
92 interrupt-parent = <&cpuintc>; 87 interrupt-parent = <&cpuintc>;
93 interrupts = <4>; 88 interrupts = <4>;
94 }; 89 };
95 90
96 tcu: timer@10002000 { 91 tcu: timer@10002000 {
97 compatible = "ingenic,x1830-tc 92 compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
98 reg = <0x10002000 0x1000>; 93 reg = <0x10002000 0x1000>;
99 #address-cells = <1>; 94 #address-cells = <1>;
100 #size-cells = <1>; 95 #size-cells = <1>;
101 ranges = <0x0 0x10002000 0x100 96 ranges = <0x0 0x10002000 0x1000>;
102 97
103 #clock-cells = <1>; 98 #clock-cells = <1>;
104 99
105 clocks = <&cgu X1830_CLK_RTCLK !! 100 clocks = <&cgu X1830_CLK_RTCLK
106 <&cgu X1830_CLK_EXCLK !! 101 &cgu X1830_CLK_EXCLK
107 <&cgu X1830_CLK_PCLK> !! 102 &cgu X1830_CLK_PCLK>;
108 <&cgu X1830_CLK_TCU>; !! 103 clock-names = "rtc", "ext", "pclk";
109 clock-names = "rtc", "ext", "p <<
110 104
111 interrupt-controller; 105 interrupt-controller;
112 #interrupt-cells = <1>; 106 #interrupt-cells = <1>;
113 107
114 interrupt-parent = <&intc>; 108 interrupt-parent = <&intc>;
115 interrupts = <27 26 25>; 109 interrupts = <27 26 25>;
116 110
117 wdt: watchdog@0 { 111 wdt: watchdog@0 {
118 compatible = "ingenic, 112 compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
119 reg = <0x0 0x10>; 113 reg = <0x0 0x10>;
120 114
121 clocks = <&tcu TCU_CLK 115 clocks = <&tcu TCU_CLK_WDT>;
122 clock-names = "wdt"; 116 clock-names = "wdt";
123 }; 117 };
124 <<
125 pwm: pwm@40 { <<
126 compatible = "ingenic, <<
127 reg = <0x40 0x80>; <<
128 <<
129 #pwm-cells = <3>; <<
130 <<
131 clocks = <&tcu TCU_CLK <<
132 <&tcu TCU_CLK <<
133 <&tcu TCU_CLK <<
134 <&tcu TCU_CLK <<
135 clock-names = "timer0" <<
136 "timer4" <<
137 }; <<
138 }; 118 };
139 119
140 rtc: rtc@10003000 { 120 rtc: rtc@10003000 {
141 compatible = "ingenic,x1830-rt 121 compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
142 reg = <0x10003000 0x4c>; 122 reg = <0x10003000 0x4c>;
143 123
144 interrupt-parent = <&intc>; 124 interrupt-parent = <&intc>;
145 interrupts = <32>; 125 interrupts = <32>;
146 126
147 clocks = <&cgu X1830_CLK_RTCLK 127 clocks = <&cgu X1830_CLK_RTCLK>;
148 clock-names = "rtc"; 128 clock-names = "rtc";
149 }; 129 };
150 130
151 pinctrl: pin-controller@10010000 { 131 pinctrl: pin-controller@10010000 {
152 compatible = "ingenic,x1830-pi 132 compatible = "ingenic,x1830-pinctrl";
153 reg = <0x10010000 0x800>; 133 reg = <0x10010000 0x800>;
154 #address-cells = <1>; 134 #address-cells = <1>;
155 #size-cells = <0>; 135 #size-cells = <0>;
156 136
157 gpa: gpio@0 { 137 gpa: gpio@0 {
158 compatible = "ingenic, 138 compatible = "ingenic,x1830-gpio";
159 reg = <0>; 139 reg = <0>;
160 140
161 gpio-controller; 141 gpio-controller;
162 gpio-ranges = <&pinctr 142 gpio-ranges = <&pinctrl 0 0 32>;
163 #gpio-cells = <2>; 143 #gpio-cells = <2>;
164 144
165 interrupt-controller; 145 interrupt-controller;
166 #interrupt-cells = <2> 146 #interrupt-cells = <2>;
167 147
168 interrupt-parent = <&i 148 interrupt-parent = <&intc>;
169 interrupts = <17>; 149 interrupts = <17>;
170 }; 150 };
171 151
172 gpb: gpio@1 { 152 gpb: gpio@1 {
173 compatible = "ingenic, 153 compatible = "ingenic,x1830-gpio";
174 reg = <1>; 154 reg = <1>;
175 155
176 gpio-controller; 156 gpio-controller;
177 gpio-ranges = <&pinctr 157 gpio-ranges = <&pinctrl 0 32 32>;
178 #gpio-cells = <2>; 158 #gpio-cells = <2>;
179 159
180 interrupt-controller; 160 interrupt-controller;
181 #interrupt-cells = <2> 161 #interrupt-cells = <2>;
182 162
183 interrupt-parent = <&i 163 interrupt-parent = <&intc>;
184 interrupts = <16>; 164 interrupts = <16>;
185 }; 165 };
186 166
187 gpc: gpio@2 { 167 gpc: gpio@2 {
188 compatible = "ingenic, 168 compatible = "ingenic,x1830-gpio";
189 reg = <2>; 169 reg = <2>;
190 170
191 gpio-controller; 171 gpio-controller;
192 gpio-ranges = <&pinctr 172 gpio-ranges = <&pinctrl 0 64 32>;
193 #gpio-cells = <2>; 173 #gpio-cells = <2>;
194 174
195 interrupt-controller; 175 interrupt-controller;
196 #interrupt-cells = <2> 176 #interrupt-cells = <2>;
197 177
198 interrupt-parent = <&i 178 interrupt-parent = <&intc>;
199 interrupts = <15>; 179 interrupts = <15>;
200 }; 180 };
201 181
202 gpd: gpio@3 { 182 gpd: gpio@3 {
203 compatible = "ingenic, 183 compatible = "ingenic,x1830-gpio";
204 reg = <3>; 184 reg = <3>;
205 185
206 gpio-controller; 186 gpio-controller;
207 gpio-ranges = <&pinctr 187 gpio-ranges = <&pinctrl 0 96 32>;
208 #gpio-cells = <2>; 188 #gpio-cells = <2>;
209 189
210 interrupt-controller; 190 interrupt-controller;
211 #interrupt-cells = <2> 191 #interrupt-cells = <2>;
212 192
213 interrupt-parent = <&i 193 interrupt-parent = <&intc>;
214 interrupts = <14>; 194 interrupts = <14>;
215 }; 195 };
216 }; 196 };
217 197
218 uart0: serial@10030000 { 198 uart0: serial@10030000 {
219 compatible = "ingenic,x1830-ua 199 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
220 reg = <0x10030000 0x100>; 200 reg = <0x10030000 0x100>;
221 201
222 interrupt-parent = <&intc>; 202 interrupt-parent = <&intc>;
223 interrupts = <51>; 203 interrupts = <51>;
224 204
225 clocks = <&exclk>, <&cgu X1830 205 clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
226 clock-names = "baud", "module" 206 clock-names = "baud", "module";
227 207
228 status = "disabled"; 208 status = "disabled";
229 }; 209 };
230 210
231 uart1: serial@10031000 { 211 uart1: serial@10031000 {
232 compatible = "ingenic,x1830-ua 212 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
233 reg = <0x10031000 0x100>; 213 reg = <0x10031000 0x100>;
234 214
235 interrupt-parent = <&intc>; 215 interrupt-parent = <&intc>;
236 interrupts = <50>; 216 interrupts = <50>;
237 217
238 clocks = <&exclk>, <&cgu X1830 218 clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
239 clock-names = "baud", "module" 219 clock-names = "baud", "module";
240 220
241 status = "disabled"; 221 status = "disabled";
242 }; 222 };
243 223
244 ssi0: spi@10043000 { <<
245 compatible = "ingenic,x1830-sp <<
246 reg = <0x10043000 0x20>; <<
247 #address-cells = <1>; <<
248 #size-cells = <0>; <<
249 <<
250 interrupt-parent = <&intc>; <<
251 interrupts = <9>; <<
252 <<
253 clocks = <&cgu X1830_CLK_SSI0> <<
254 clock-names = "spi"; <<
255 <<
256 dmas = <&pdma X1830_DMA_SSI0_R <<
257 <&pdma X1830_DMA_SS <<
258 dma-names = "rx", "tx"; <<
259 <<
260 status = "disabled"; <<
261 }; <<
262 <<
263 ssi1: spi@10044000 { <<
264 compatible = "ingenic,x1830-sp <<
265 reg = <0x10044000 0x20>; <<
266 #address-cells = <1>; <<
267 #size-cells = <0>; <<
268 <<
269 interrupt-parent = <&intc>; <<
270 interrupts = <8>; <<
271 <<
272 clocks = <&cgu X1830_CLK_SSI1> <<
273 clock-names = "spi"; <<
274 <<
275 dmas = <&pdma X1830_DMA_SSI1_R <<
276 <&pdma X1830_DMA_SS <<
277 dma-names = "rx", "tx"; <<
278 <<
279 status = "disabled"; <<
280 }; <<
281 <<
282 i2c0: i2c-controller@10050000 { 224 i2c0: i2c-controller@10050000 {
283 compatible = "ingenic,x1830-i2 225 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
284 reg = <0x10050000 0x1000>; 226 reg = <0x10050000 0x1000>;
285 #address-cells = <1>; 227 #address-cells = <1>;
286 #size-cells = <0>; 228 #size-cells = <0>;
287 229
288 interrupt-parent = <&intc>; 230 interrupt-parent = <&intc>;
289 interrupts = <60>; 231 interrupts = <60>;
290 232
291 clocks = <&cgu X1830_CLK_SMB0> 233 clocks = <&cgu X1830_CLK_SMB0>;
292 234
293 status = "disabled"; 235 status = "disabled";
294 }; 236 };
295 237
296 i2c1: i2c-controller@10051000 { 238 i2c1: i2c-controller@10051000 {
297 compatible = "ingenic,x1830-i2 239 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
298 reg = <0x10051000 0x1000>; 240 reg = <0x10051000 0x1000>;
299 #address-cells = <1>; 241 #address-cells = <1>;
300 #size-cells = <0>; 242 #size-cells = <0>;
301 243
302 interrupt-parent = <&intc>; 244 interrupt-parent = <&intc>;
303 interrupts = <59>; 245 interrupts = <59>;
304 246
305 clocks = <&cgu X1830_CLK_SMB1> 247 clocks = <&cgu X1830_CLK_SMB1>;
306 248
307 status = "disabled"; 249 status = "disabled";
308 }; 250 };
309 251
310 i2c2: i2c-controller@10052000 { 252 i2c2: i2c-controller@10052000 {
311 compatible = "ingenic,x1830-i2 253 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
312 reg = <0x10052000 0x1000>; 254 reg = <0x10052000 0x1000>;
313 #address-cells = <1>; 255 #address-cells = <1>;
314 #size-cells = <0>; 256 #size-cells = <0>;
315 257
316 interrupt-parent = <&intc>; 258 interrupt-parent = <&intc>;
317 interrupts = <58>; 259 interrupts = <58>;
318 260
319 clocks = <&cgu X1830_CLK_SMB2> 261 clocks = <&cgu X1830_CLK_SMB2>;
320 262
321 status = "disabled"; 263 status = "disabled";
322 }; 264 };
323 265
324 dtrng: trng@10072000 { 266 dtrng: trng@10072000 {
325 compatible = "ingenic,x1830-dt 267 compatible = "ingenic,x1830-dtrng";
326 reg = <0x10072000 0xc>; 268 reg = <0x10072000 0xc>;
327 269
328 clocks = <&cgu X1830_CLK_DTRNG 270 clocks = <&cgu X1830_CLK_DTRNG>;
329 271
330 status = "disabled"; 272 status = "disabled";
331 }; 273 };
332 274
333 pdma: dma-controller@13420000 { 275 pdma: dma-controller@13420000 {
334 compatible = "ingenic,x1830-dm 276 compatible = "ingenic,x1830-dma";
335 reg = <0x13420000 0x400>, <0x1 !! 277 reg = <0x13420000 0x400
336 !! 278 0x13421000 0x40>;
337 #dma-cells = <2>; 279 #dma-cells = <2>;
338 280
339 interrupt-parent = <&intc>; 281 interrupt-parent = <&intc>;
340 interrupts = <10>; 282 interrupts = <10>;
341 283
342 clocks = <&cgu X1830_CLK_PDMA> 284 clocks = <&cgu X1830_CLK_PDMA>;
343 }; 285 };
344 286
345 msc0: mmc@13450000 { 287 msc0: mmc@13450000 {
346 compatible = "ingenic,x1830-mm 288 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
347 reg = <0x13450000 0x1000>; 289 reg = <0x13450000 0x1000>;
348 290
349 interrupt-parent = <&intc>; 291 interrupt-parent = <&intc>;
350 interrupts = <37>; 292 interrupts = <37>;
351 293
352 clocks = <&cgu X1830_CLK_MSC0> 294 clocks = <&cgu X1830_CLK_MSC0>;
353 clock-names = "mmc"; 295 clock-names = "mmc";
354 296
355 cap-sd-highspeed; 297 cap-sd-highspeed;
356 cap-mmc-highspeed; 298 cap-mmc-highspeed;
357 cap-sdio-irq; 299 cap-sdio-irq;
358 300
359 dmas = <&pdma X1830_DMA_MSC0_R 301 dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
360 <&pdma X1830_DMA_MS 302 <&pdma X1830_DMA_MSC0_TX 0xffffffff>;
361 dma-names = "rx", "tx"; 303 dma-names = "rx", "tx";
362 304
363 status = "disabled"; 305 status = "disabled";
364 }; 306 };
365 307
366 msc1: mmc@13460000 { 308 msc1: mmc@13460000 {
367 compatible = "ingenic,x1830-mm 309 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
368 reg = <0x13460000 0x1000>; 310 reg = <0x13460000 0x1000>;
369 311
370 interrupt-parent = <&intc>; 312 interrupt-parent = <&intc>;
371 interrupts = <36>; 313 interrupts = <36>;
372 314
373 clocks = <&cgu X1830_CLK_MSC1> 315 clocks = <&cgu X1830_CLK_MSC1>;
374 clock-names = "mmc"; 316 clock-names = "mmc";
375 317
376 cap-sd-highspeed; 318 cap-sd-highspeed;
377 cap-mmc-highspeed; 319 cap-mmc-highspeed;
378 cap-sdio-irq; 320 cap-sdio-irq;
379 321
380 dmas = <&pdma X1830_DMA_MSC1_R 322 dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
381 <&pdma X1830_DMA_MS 323 <&pdma X1830_DMA_MSC1_TX 0xffffffff>;
382 dma-names = "rx", "tx"; 324 dma-names = "rx", "tx";
383 325
384 status = "disabled"; 326 status = "disabled";
385 }; 327 };
386 328
387 mac: ethernet@134b0000 { 329 mac: ethernet@134b0000 {
388 compatible = "ingenic,x1830-ma 330 compatible = "ingenic,x1830-mac", "snps,dwmac";
389 reg = <0x134b0000 0x2000>; 331 reg = <0x134b0000 0x2000>;
390 332
391 interrupt-parent = <&intc>; 333 interrupt-parent = <&intc>;
392 interrupts = <55>; 334 interrupts = <55>;
393 interrupt-names = "macirq"; 335 interrupt-names = "macirq";
394 336
395 clocks = <&cgu X1830_CLK_MAC>; 337 clocks = <&cgu X1830_CLK_MAC>;
396 clock-names = "stmmaceth"; 338 clock-names = "stmmaceth";
397 339
398 mode-reg = <&mac_phy_ctrl>; <<
399 <<
400 status = "disabled"; 340 status = "disabled";
401 341
402 mdio: mdio { 342 mdio: mdio {
403 compatible = "snps,dwm 343 compatible = "snps,dwmac-mdio";
404 #address-cells = <1>; 344 #address-cells = <1>;
405 #size-cells = <0>; 345 #size-cells = <0>;
406 346
407 status = "disabled"; 347 status = "disabled";
408 }; 348 };
409 }; 349 };
410 350
411 otg: usb@13500000 { 351 otg: usb@13500000 {
412 compatible = "ingenic,x1830-ot !! 352 compatible = "ingenic,x1830-otg", "snps,dwc2";
413 reg = <0x13500000 0x40000>; 353 reg = <0x13500000 0x40000>;
414 354
415 interrupt-parent = <&intc>; 355 interrupt-parent = <&intc>;
416 interrupts = <21>; 356 interrupts = <21>;
417 357
418 clocks = <&cgu X1830_CLK_OTG>; 358 clocks = <&cgu X1830_CLK_OTG>;
419 clock-names = "otg"; 359 clock-names = "otg";
420 360
421 phys = <&otg_phy>; 361 phys = <&otg_phy>;
422 phy-names = "usb2-phy"; 362 phy-names = "usb2-phy";
423 363
424 g-rx-fifo-size = <768>; 364 g-rx-fifo-size = <768>;
425 g-np-tx-fifo-size = <256>; 365 g-np-tx-fifo-size = <256>;
426 g-tx-fifo-size = <256 256 256 366 g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
427 367
428 status = "disabled"; 368 status = "disabled";
429 }; 369 };
430 }; 370 };
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