1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h> 2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1830-cgu. !! 3 #include <dt-bindings/clock/x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h> 4 #include <dt-bindings/dma/x1830-dma.h>
5 5
6 / { 6 / {
7 #address-cells = <1>; 7 #address-cells = <1>;
8 #size-cells = <1>; 8 #size-cells = <1>;
9 compatible = "ingenic,x1830"; 9 compatible = "ingenic,x1830";
10 10
11 cpus { <<
12 #address-cells = <1>; <<
13 #size-cells = <0>; <<
14 <<
15 cpu0: cpu@0 { <<
16 device_type = "cpu"; <<
17 compatible = "ingenic, <<
18 reg = <0>; <<
19 <<
20 clocks = <&cgu X1830_C <<
21 clock-names = "cpu"; <<
22 }; <<
23 }; <<
24 <<
25 cpuintc: interrupt-controller { 11 cpuintc: interrupt-controller {
26 #address-cells = <0>; 12 #address-cells = <0>;
27 #interrupt-cells = <1>; 13 #interrupt-cells = <1>;
28 interrupt-controller; 14 interrupt-controller;
29 compatible = "mti,cpu-interrup 15 compatible = "mti,cpu-interrupt-controller";
30 }; 16 };
31 17
32 intc: interrupt-controller@10001000 { 18 intc: interrupt-controller@10001000 {
33 compatible = "ingenic,x1830-in 19 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
34 reg = <0x10001000 0x50>; 20 reg = <0x10001000 0x50>;
35 21
36 interrupt-controller; 22 interrupt-controller;
37 #interrupt-cells = <1>; 23 #interrupt-cells = <1>;
38 24
39 interrupt-parent = <&cpuintc>; 25 interrupt-parent = <&cpuintc>;
40 interrupts = <2>; 26 interrupts = <2>;
41 }; 27 };
42 28
43 exclk: ext { 29 exclk: ext {
44 compatible = "fixed-clock"; 30 compatible = "fixed-clock";
45 #clock-cells = <0>; 31 #clock-cells = <0>;
46 }; 32 };
47 33
48 rtclk: rtc { 34 rtclk: rtc {
49 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
50 #clock-cells = <0>; 36 #clock-cells = <0>;
51 clock-frequency = <32768>; 37 clock-frequency = <32768>;
52 }; 38 };
53 39
54 cgu: x1830-cgu@10000000 { 40 cgu: x1830-cgu@10000000 {
55 compatible = "ingenic,x1830-cg !! 41 compatible = "ingenic,x1830-cgu";
56 reg = <0x10000000 0x100>; 42 reg = <0x10000000 0x100>;
57 #address-cells = <1>; <<
58 #size-cells = <1>; <<
59 ranges = <0x0 0x10000000 0x100 <<
60 43
61 #clock-cells = <1>; 44 #clock-cells = <1>;
62 45
63 clocks = <&exclk>, <&rtclk>; 46 clocks = <&exclk>, <&rtclk>;
64 clock-names = "ext", "rtc"; 47 clock-names = "ext", "rtc";
65 <<
66 otg_phy: usb-phy@3c { <<
67 compatible = "ingenic, <<
68 reg = <0x3c 0x10>; <<
69 <<
70 clocks = <&cgu X1830_C <<
71 <<
72 #phy-cells = <0>; <<
73 <<
74 status = "disabled"; <<
75 }; <<
76 <<
77 mac_phy_ctrl: mac-phy-ctrl@e8 <<
78 compatible = "syscon"; <<
79 reg = <0xe8 0x4>; <<
80 }; <<
81 }; <<
82 <<
83 ost: timer@12000000 { <<
84 compatible = "ingenic,x1830-os <<
85 reg = <0x12000000 0x3c>; <<
86 <<
87 #clock-cells = <1>; <<
88 <<
89 clocks = <&cgu X1830_CLK_OST>; <<
90 clock-names = "ost"; <<
91 <<
92 interrupt-parent = <&cpuintc>; <<
93 interrupts = <4>; <<
94 }; 48 };
95 49
96 tcu: timer@10002000 { 50 tcu: timer@10002000 {
97 compatible = "ingenic,x1830-tc 51 compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
98 reg = <0x10002000 0x1000>; 52 reg = <0x10002000 0x1000>;
99 #address-cells = <1>; 53 #address-cells = <1>;
100 #size-cells = <1>; 54 #size-cells = <1>;
101 ranges = <0x0 0x10002000 0x100 55 ranges = <0x0 0x10002000 0x1000>;
102 56
103 #clock-cells = <1>; 57 #clock-cells = <1>;
104 58
105 clocks = <&cgu X1830_CLK_RTCLK !! 59 clocks = <&cgu X1830_CLK_RTCLK
106 <&cgu X1830_CLK_EXCLK !! 60 &cgu X1830_CLK_EXCLK
107 <&cgu X1830_CLK_PCLK> !! 61 &cgu X1830_CLK_PCLK>;
108 <&cgu X1830_CLK_TCU>; !! 62 clock-names = "rtc", "ext", "pclk";
109 clock-names = "rtc", "ext", "p <<
110 63
111 interrupt-controller; 64 interrupt-controller;
112 #interrupt-cells = <1>; 65 #interrupt-cells = <1>;
113 66
114 interrupt-parent = <&intc>; 67 interrupt-parent = <&intc>;
115 interrupts = <27 26 25>; 68 interrupts = <27 26 25>;
116 69
117 wdt: watchdog@0 { 70 wdt: watchdog@0 {
118 compatible = "ingenic, 71 compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
119 reg = <0x0 0x10>; 72 reg = <0x0 0x10>;
120 73
121 clocks = <&tcu TCU_CLK 74 clocks = <&tcu TCU_CLK_WDT>;
122 clock-names = "wdt"; 75 clock-names = "wdt";
123 }; 76 };
124 <<
125 pwm: pwm@40 { <<
126 compatible = "ingenic, <<
127 reg = <0x40 0x80>; <<
128 <<
129 #pwm-cells = <3>; <<
130 <<
131 clocks = <&tcu TCU_CLK <<
132 <&tcu TCU_CLK <<
133 <&tcu TCU_CLK <<
134 <&tcu TCU_CLK <<
135 clock-names = "timer0" <<
136 "timer4" <<
137 }; <<
138 }; 77 };
139 78
140 rtc: rtc@10003000 { 79 rtc: rtc@10003000 {
141 compatible = "ingenic,x1830-rt 80 compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
142 reg = <0x10003000 0x4c>; 81 reg = <0x10003000 0x4c>;
143 82
144 interrupt-parent = <&intc>; 83 interrupt-parent = <&intc>;
145 interrupts = <32>; 84 interrupts = <32>;
146 85
147 clocks = <&cgu X1830_CLK_RTCLK 86 clocks = <&cgu X1830_CLK_RTCLK>;
148 clock-names = "rtc"; 87 clock-names = "rtc";
149 }; 88 };
150 89
151 pinctrl: pin-controller@10010000 { 90 pinctrl: pin-controller@10010000 {
152 compatible = "ingenic,x1830-pi 91 compatible = "ingenic,x1830-pinctrl";
153 reg = <0x10010000 0x800>; 92 reg = <0x10010000 0x800>;
154 #address-cells = <1>; 93 #address-cells = <1>;
155 #size-cells = <0>; 94 #size-cells = <0>;
156 95
157 gpa: gpio@0 { 96 gpa: gpio@0 {
158 compatible = "ingenic, 97 compatible = "ingenic,x1830-gpio";
159 reg = <0>; 98 reg = <0>;
160 99
161 gpio-controller; 100 gpio-controller;
162 gpio-ranges = <&pinctr 101 gpio-ranges = <&pinctrl 0 0 32>;
163 #gpio-cells = <2>; 102 #gpio-cells = <2>;
164 103
165 interrupt-controller; 104 interrupt-controller;
166 #interrupt-cells = <2> 105 #interrupt-cells = <2>;
167 106
168 interrupt-parent = <&i 107 interrupt-parent = <&intc>;
169 interrupts = <17>; 108 interrupts = <17>;
170 }; 109 };
171 110
172 gpb: gpio@1 { 111 gpb: gpio@1 {
173 compatible = "ingenic, 112 compatible = "ingenic,x1830-gpio";
174 reg = <1>; 113 reg = <1>;
175 114
176 gpio-controller; 115 gpio-controller;
177 gpio-ranges = <&pinctr 116 gpio-ranges = <&pinctrl 0 32 32>;
178 #gpio-cells = <2>; 117 #gpio-cells = <2>;
179 118
180 interrupt-controller; 119 interrupt-controller;
181 #interrupt-cells = <2> 120 #interrupt-cells = <2>;
182 121
183 interrupt-parent = <&i 122 interrupt-parent = <&intc>;
184 interrupts = <16>; 123 interrupts = <16>;
185 }; 124 };
186 125
187 gpc: gpio@2 { 126 gpc: gpio@2 {
188 compatible = "ingenic, 127 compatible = "ingenic,x1830-gpio";
189 reg = <2>; 128 reg = <2>;
190 129
191 gpio-controller; 130 gpio-controller;
192 gpio-ranges = <&pinctr 131 gpio-ranges = <&pinctrl 0 64 32>;
193 #gpio-cells = <2>; 132 #gpio-cells = <2>;
194 133
195 interrupt-controller; 134 interrupt-controller;
196 #interrupt-cells = <2> 135 #interrupt-cells = <2>;
197 136
198 interrupt-parent = <&i 137 interrupt-parent = <&intc>;
199 interrupts = <15>; 138 interrupts = <15>;
200 }; 139 };
201 140
202 gpd: gpio@3 { 141 gpd: gpio@3 {
203 compatible = "ingenic, 142 compatible = "ingenic,x1830-gpio";
204 reg = <3>; 143 reg = <3>;
205 144
206 gpio-controller; 145 gpio-controller;
207 gpio-ranges = <&pinctr 146 gpio-ranges = <&pinctrl 0 96 32>;
208 #gpio-cells = <2>; 147 #gpio-cells = <2>;
209 148
210 interrupt-controller; 149 interrupt-controller;
211 #interrupt-cells = <2> 150 #interrupt-cells = <2>;
212 151
213 interrupt-parent = <&i 152 interrupt-parent = <&intc>;
214 interrupts = <14>; 153 interrupts = <14>;
215 }; 154 };
216 }; 155 };
217 156
218 uart0: serial@10030000 { 157 uart0: serial@10030000 {
219 compatible = "ingenic,x1830-ua 158 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
220 reg = <0x10030000 0x100>; 159 reg = <0x10030000 0x100>;
221 160
222 interrupt-parent = <&intc>; 161 interrupt-parent = <&intc>;
223 interrupts = <51>; 162 interrupts = <51>;
224 163
225 clocks = <&exclk>, <&cgu X1830 164 clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
226 clock-names = "baud", "module" 165 clock-names = "baud", "module";
227 166
228 status = "disabled"; 167 status = "disabled";
229 }; 168 };
230 169
231 uart1: serial@10031000 { 170 uart1: serial@10031000 {
232 compatible = "ingenic,x1830-ua 171 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
233 reg = <0x10031000 0x100>; 172 reg = <0x10031000 0x100>;
234 173
235 interrupt-parent = <&intc>; 174 interrupt-parent = <&intc>;
236 interrupts = <50>; 175 interrupts = <50>;
237 176
238 clocks = <&exclk>, <&cgu X1830 177 clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
239 clock-names = "baud", "module" 178 clock-names = "baud", "module";
240 179
241 status = "disabled"; 180 status = "disabled";
242 }; 181 };
243 182
244 ssi0: spi@10043000 { <<
245 compatible = "ingenic,x1830-sp <<
246 reg = <0x10043000 0x20>; <<
247 #address-cells = <1>; <<
248 #size-cells = <0>; <<
249 <<
250 interrupt-parent = <&intc>; <<
251 interrupts = <9>; <<
252 <<
253 clocks = <&cgu X1830_CLK_SSI0> <<
254 clock-names = "spi"; <<
255 <<
256 dmas = <&pdma X1830_DMA_SSI0_R <<
257 <&pdma X1830_DMA_SS <<
258 dma-names = "rx", "tx"; <<
259 <<
260 status = "disabled"; <<
261 }; <<
262 <<
263 ssi1: spi@10044000 { <<
264 compatible = "ingenic,x1830-sp <<
265 reg = <0x10044000 0x20>; <<
266 #address-cells = <1>; <<
267 #size-cells = <0>; <<
268 <<
269 interrupt-parent = <&intc>; <<
270 interrupts = <8>; <<
271 <<
272 clocks = <&cgu X1830_CLK_SSI1> <<
273 clock-names = "spi"; <<
274 <<
275 dmas = <&pdma X1830_DMA_SSI1_R <<
276 <&pdma X1830_DMA_SS <<
277 dma-names = "rx", "tx"; <<
278 <<
279 status = "disabled"; <<
280 }; <<
281 <<
282 i2c0: i2c-controller@10050000 { 183 i2c0: i2c-controller@10050000 {
283 compatible = "ingenic,x1830-i2 184 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
284 reg = <0x10050000 0x1000>; 185 reg = <0x10050000 0x1000>;
285 #address-cells = <1>; 186 #address-cells = <1>;
286 #size-cells = <0>; 187 #size-cells = <0>;
287 188
288 interrupt-parent = <&intc>; 189 interrupt-parent = <&intc>;
289 interrupts = <60>; 190 interrupts = <60>;
290 191
291 clocks = <&cgu X1830_CLK_SMB0> 192 clocks = <&cgu X1830_CLK_SMB0>;
292 193
293 status = "disabled"; 194 status = "disabled";
294 }; 195 };
295 196
296 i2c1: i2c-controller@10051000 { 197 i2c1: i2c-controller@10051000 {
297 compatible = "ingenic,x1830-i2 198 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
298 reg = <0x10051000 0x1000>; 199 reg = <0x10051000 0x1000>;
299 #address-cells = <1>; 200 #address-cells = <1>;
300 #size-cells = <0>; 201 #size-cells = <0>;
301 202
302 interrupt-parent = <&intc>; 203 interrupt-parent = <&intc>;
303 interrupts = <59>; 204 interrupts = <59>;
304 205
305 clocks = <&cgu X1830_CLK_SMB1> 206 clocks = <&cgu X1830_CLK_SMB1>;
306 207
307 status = "disabled"; 208 status = "disabled";
308 }; 209 };
309 210
310 i2c2: i2c-controller@10052000 { 211 i2c2: i2c-controller@10052000 {
311 compatible = "ingenic,x1830-i2 212 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
312 reg = <0x10052000 0x1000>; 213 reg = <0x10052000 0x1000>;
313 #address-cells = <1>; 214 #address-cells = <1>;
314 #size-cells = <0>; 215 #size-cells = <0>;
315 216
316 interrupt-parent = <&intc>; 217 interrupt-parent = <&intc>;
317 interrupts = <58>; 218 interrupts = <58>;
318 219
319 clocks = <&cgu X1830_CLK_SMB2> 220 clocks = <&cgu X1830_CLK_SMB2>;
320 221
321 status = "disabled"; 222 status = "disabled";
322 }; 223 };
323 224
324 dtrng: trng@10072000 { <<
325 compatible = "ingenic,x1830-dt <<
326 reg = <0x10072000 0xc>; <<
327 <<
328 clocks = <&cgu X1830_CLK_DTRNG <<
329 <<
330 status = "disabled"; <<
331 }; <<
332 <<
333 pdma: dma-controller@13420000 { 225 pdma: dma-controller@13420000 {
334 compatible = "ingenic,x1830-dm 226 compatible = "ingenic,x1830-dma";
335 reg = <0x13420000 0x400>, <0x1 !! 227 reg = <0x13420000 0x400
336 !! 228 0x13421000 0x40>;
337 #dma-cells = <2>; 229 #dma-cells = <2>;
338 230
339 interrupt-parent = <&intc>; 231 interrupt-parent = <&intc>;
340 interrupts = <10>; 232 interrupts = <10>;
341 233
342 clocks = <&cgu X1830_CLK_PDMA> 234 clocks = <&cgu X1830_CLK_PDMA>;
343 }; 235 };
344 236
345 msc0: mmc@13450000 { 237 msc0: mmc@13450000 {
346 compatible = "ingenic,x1830-mm 238 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
347 reg = <0x13450000 0x1000>; 239 reg = <0x13450000 0x1000>;
348 240
349 interrupt-parent = <&intc>; 241 interrupt-parent = <&intc>;
350 interrupts = <37>; 242 interrupts = <37>;
351 243
352 clocks = <&cgu X1830_CLK_MSC0> 244 clocks = <&cgu X1830_CLK_MSC0>;
353 clock-names = "mmc"; 245 clock-names = "mmc";
354 246
355 cap-sd-highspeed; 247 cap-sd-highspeed;
356 cap-mmc-highspeed; 248 cap-mmc-highspeed;
357 cap-sdio-irq; 249 cap-sdio-irq;
358 250
359 dmas = <&pdma X1830_DMA_MSC0_R 251 dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
360 <&pdma X1830_DMA_MS 252 <&pdma X1830_DMA_MSC0_TX 0xffffffff>;
361 dma-names = "rx", "tx"; 253 dma-names = "rx", "tx";
362 254
363 status = "disabled"; 255 status = "disabled";
364 }; 256 };
365 257
366 msc1: mmc@13460000 { 258 msc1: mmc@13460000 {
367 compatible = "ingenic,x1830-mm 259 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
368 reg = <0x13460000 0x1000>; 260 reg = <0x13460000 0x1000>;
369 261
370 interrupt-parent = <&intc>; 262 interrupt-parent = <&intc>;
371 interrupts = <36>; 263 interrupts = <36>;
372 264
373 clocks = <&cgu X1830_CLK_MSC1> 265 clocks = <&cgu X1830_CLK_MSC1>;
374 clock-names = "mmc"; 266 clock-names = "mmc";
375 267
376 cap-sd-highspeed; 268 cap-sd-highspeed;
377 cap-mmc-highspeed; 269 cap-mmc-highspeed;
378 cap-sdio-irq; 270 cap-sdio-irq;
379 271
380 dmas = <&pdma X1830_DMA_MSC1_R 272 dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
381 <&pdma X1830_DMA_MS 273 <&pdma X1830_DMA_MSC1_TX 0xffffffff>;
382 dma-names = "rx", "tx"; 274 dma-names = "rx", "tx";
383 275
384 status = "disabled"; 276 status = "disabled";
385 }; 277 };
386 278
387 mac: ethernet@134b0000 { 279 mac: ethernet@134b0000 {
388 compatible = "ingenic,x1830-ma 280 compatible = "ingenic,x1830-mac", "snps,dwmac";
389 reg = <0x134b0000 0x2000>; 281 reg = <0x134b0000 0x2000>;
390 282
391 interrupt-parent = <&intc>; 283 interrupt-parent = <&intc>;
392 interrupts = <55>; 284 interrupts = <55>;
393 interrupt-names = "macirq"; 285 interrupt-names = "macirq";
394 286
395 clocks = <&cgu X1830_CLK_MAC>; 287 clocks = <&cgu X1830_CLK_MAC>;
396 clock-names = "stmmaceth"; 288 clock-names = "stmmaceth";
397 289
398 mode-reg = <&mac_phy_ctrl>; <<
399 <<
400 status = "disabled"; 290 status = "disabled";
401 291
402 mdio: mdio { 292 mdio: mdio {
403 compatible = "snps,dwm 293 compatible = "snps,dwmac-mdio";
404 #address-cells = <1>; 294 #address-cells = <1>;
405 #size-cells = <0>; 295 #size-cells = <0>;
406 296
407 status = "disabled"; 297 status = "disabled";
408 }; 298 };
409 }; <<
410 <<
411 otg: usb@13500000 { <<
412 compatible = "ingenic,x1830-ot <<
413 reg = <0x13500000 0x40000>; <<
414 <<
415 interrupt-parent = <&intc>; <<
416 interrupts = <21>; <<
417 <<
418 clocks = <&cgu X1830_CLK_OTG>; <<
419 clock-names = "otg"; <<
420 <<
421 phys = <&otg_phy>; <<
422 phy-names = "usb2-phy"; <<
423 <<
424 g-rx-fifo-size = <768>; <<
425 g-np-tx-fifo-size = <256>; <<
426 g-tx-fifo-size = <256 256 256 <<
427 <<
428 status = "disabled"; <<
429 }; 299 };
430 }; 300 };
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