1 // SPDX-License-Identifier: GPL-2.0
2
3 / {
4 pch: bus@10000000 {
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
8 ranges = <0 0x10000000 0 0x100
9 0 0x20000000 0
10 0 0x40000000 0
11 0xe00 0x000000
12
13 pic: interrupt-controller@1000
14 compatible = "loongson
15 reg = <0 0x10000000 0
16 interrupt-controller;
17 interrupt-parent = <&h
18 loongson,pic-base-vec
19 #interrupt-cells = <2>
20 };
21
22 rtc0: rtc@100d0100 {
23 compatible = "loongson
24 reg = <0 0x100d0100 0
25 interrupt-parent = <&p
26 interrupts = <52 IRQ_T
27 };
28
29 ls7a_uart0: serial@10080000 {
30 compatible = "ns16550a
31 reg = <0 0x10080000 0
32 clock-frequency = <500
33 interrupt-parent = <&p
34 interrupts = <8 IRQ_TY
35 no-loopback-test;
36 };
37
38 ls7a_uart1: serial@10080100 {
39 status = "disabled";
40 compatible = "ns16550a
41 reg = <0 0x10080100 0
42 clock-frequency = <500
43 interrupt-parent = <&p
44 interrupts = <8 IRQ_TY
45 no-loopback-test;
46 };
47
48 ls7a_uart2: serial@10080200 {
49 status = "disabled";
50 compatible = "ns16550a
51 reg = <0 0x10080200 0
52 clock-frequency = <500
53 interrupt-parent = <&p
54 interrupts = <8 IRQ_TY
55 no-loopback-test;
56 };
57
58 ls7a_uart3: serial@10080300 {
59 status = "disabled";
60 compatible = "ns16550a
61 reg = <0 0x10080300 0
62 clock-frequency = <500
63 interrupt-parent = <&p
64 interrupts = <8 IRQ_TY
65 no-loopback-test;
66 };
67
68 pci@1a000000 {
69 compatible = "loongson
70 device_type = "pci";
71 #address-cells = <3>;
72 #size-cells = <2>;
73 #interrupt-cells = <2>
74 msi-parent = <&msi>;
75
76 reg = <0 0x1a000000 0
77 <0xefe 0x00000
78
79 ranges = <0x01000000 0
80 <0x02000000 0
81
82 ohci@4,0 {
83 compatible = "
84
85
86
87
88 reg = <0x2000
89 interrupts = <
90 interrupt-pare
91 };
92
93 ehci@4,1 {
94 compatible = "
95
96
97
98
99 reg = <0x2100
100 interrupts = <
101 interrupt-pare
102 };
103
104 ohci@5,0 {
105 compatible = "
106
107
108
109
110 reg = <0x2800
111 interrupts = <
112 interrupt-pare
113 };
114
115 ehci@5,1 {
116 compatible = "
117
118
119
120
121 reg = <0x2900
122 interrupts = <
123 interrupt-pare
124 };
125
126 sata@8,0 {
127 compatible = "
128
129
130
131
132 reg = <0x4000
133 interrupts = <
134 interrupt-pare
135 };
136
137 sata@8,1 {
138 compatible = "
139
140
141
142
143 reg = <0x4100
144 interrupts = <
145 interrupt-pare
146 };
147
148 sata@8,2 {
149 compatible = "
150
151
152
153
154 reg = <0x4200
155 interrupts = <
156 interrupt-pare
157 };
158
159 gpu@6,0 {
160 compatible = "
161
162
163
164
165 reg = <0x3000
166 interrupts = <
167 interrupt-pare
168 };
169
170 dc@6,1 {
171 compatible = "
172
173
174
175
176 reg = <0x3100
177 interrupts = <
178 interrupt-pare
179 };
180
181 hda@7,0 {
182 compatible = "
183
184
185
186
187 reg = <0x3800
188 interrupts = <
189 interrupt-pare
190 };
191
192 gmac@3,0 {
193 compatible = "
194
195
196
197
198 reg = <0x1800
199 interrupts = <
200 <
201 interrupt-name
202 interrupt-pare
203 phy-mode = "rg
204 mdio {
205 #addre
206 #size-
207 compat
208 phy0:
209
210 };
211 };
212 };
213
214 gmac@3,1 {
215 compatible = "
216
217
218
219
220
221 reg = <0x1900
222 interrupts = <
223 <
224 interrupt-name
225 interrupt-pare
226 phy-mode = "rg
227 mdio {
228 #addre
229 #size-
230 compat
231 phy1:
232
233 };
234 };
235 };
236
237 pci_bridge@9,0 {
238 compatible = "
239
240
241
242
243 reg = <0x4800
244 interrupts = <
245 interrupt-pare
246
247 #interrupt-cel
248 interrupt-map-
249 interrupt-map
250 };
251
252 pci_bridge@a,0 {
253 compatible = "
254
255
256
257
258 reg = <0x5000
259 interrupts = <
260 interrupt-pare
261
262 #interrupt-cel
263 interrupt-map-
264 interrupt-map
265 };
266
267 pci_bridge@b,0 {
268 compatible = "
269
270
271
272
273 reg = <0x5800
274 interrupts = <
275 interrupt-pare
276
277 #interrupt-cel
278 interrupt-map-
279 interrupt-map
280 };
281
282 pci_bridge@c,0 {
283 compatible = "
284
285
286
287
288 reg = <0x6000
289 interrupts = <
290 interrupt-pare
291
292 #interrupt-cel
293 interrupt-map-
294 interrupt-map
295 };
296
297 pci_bridge@d,0 {
298 compatible = "
299
300
301
302
303 reg = <0x6800
304 interrupts = <
305 interrupt-pare
306
307 #interrupt-cel
308 interrupt-map-
309 interrupt-map
310 };
311
312 pci_bridge@e,0 {
313 compatible = "
314
315
316
317
318 reg = <0x7000
319 interrupts = <
320 interrupt-pare
321
322 #interrupt-cel
323 interrupt-map-
324 interrupt-map
325 };
326
327 pci_bridge@f,0 {
328 compatible = "
329
330
331
332
333 reg = <0x7800
334 interrupts = <
335 interrupt-pare
336
337 #interrupt-cel
338 interrupt-map-
339 interrupt-map
340 };
341
342 pci_bridge@10,0 {
343 compatible = "
344
345
346
347
348 reg = <0x8000
349 interrupts = <
350 interrupt-pare
351
352 #interrupt-cel
353 interrupt-map-
354 interrupt-map
355 };
356
357 pci_bridge@11,0 {
358 compatible = "
359
360
361
362
363 reg = <0x8800
364 interrupts = <
365 interrupt-pare
366
367 #interrupt-cel
368 interrupt-map-
369 interrupt-map
370 };
371
372 pci_bridge@12,0 {
373 compatible = "
374
375
376
377
378 reg = <0x9000
379 interrupts = <
380 interrupt-pare
381
382 #interrupt-cel
383 interrupt-map-
384 interrupt-map
385 };
386
387 pci_bridge@13,0 {
388 compatible = "
389
390
391
392
393 reg = <0x9800
394 interrupts = <
395 interrupt-pare
396
397 #interrupt-cel
398 interrupt-map-
399 interrupt-map
400 };
401
402 pci_bridge@14,0 {
403 compatible = "
404
405
406
407
408 reg = <0xa000
409 interrupts = <
410 interrupt-pare
411
412 #interrupt-cel
413 interrupt-map-
414 interrupt-map
415 };
416 };
417
418 isa@18000000 {
419 compatible = "isa";
420 #address-cells = <2>;
421 #size-cells = <1>;
422 ranges = <1 0 0 0x1800
423 };
424 };
425 };
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