1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 2
3 / { 3 / {
4 pch: bus@10000000 { 4 pch: bus@10000000 {
5 compatible = "simple-bus"; 5 compatible = "simple-bus";
6 #address-cells = <2>; 6 #address-cells = <2>;
7 #size-cells = <2>; 7 #size-cells = <2>;
8 ranges = <0 0x10000000 0 0x100 8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 9 0 0x20000000 0 0x20000000 0 0x10000000
10 0 0x40000000 0 10 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
11 0xe00 0x000000 11 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
12 12
13 pic: interrupt-controller@1000 13 pic: interrupt-controller@10000000 {
14 compatible = "loongson 14 compatible = "loongson,pch-pic-1.0";
15 reg = <0 0x10000000 0 15 reg = <0 0x10000000 0 0x400>;
16 interrupt-controller; 16 interrupt-controller;
17 interrupt-parent = <&h 17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec 18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2> 19 #interrupt-cells = <2>;
20 }; 20 };
21 21
22 rtc0: rtc@100d0100 { <<
23 compatible = "loongson <<
24 reg = <0 0x100d0100 0 <<
25 interrupt-parent = <&p <<
26 interrupts = <52 IRQ_T <<
27 }; <<
28 <<
29 ls7a_uart0: serial@10080000 { 22 ls7a_uart0: serial@10080000 {
30 compatible = "ns16550a 23 compatible = "ns16550a";
31 reg = <0 0x10080000 0 24 reg = <0 0x10080000 0 0x100>;
32 clock-frequency = <500 25 clock-frequency = <50000000>;
33 interrupt-parent = <&p 26 interrupt-parent = <&pic>;
34 interrupts = <8 IRQ_TY 27 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
35 no-loopback-test; 28 no-loopback-test;
36 }; 29 };
37 30
38 ls7a_uart1: serial@10080100 { 31 ls7a_uart1: serial@10080100 {
39 status = "disabled"; 32 status = "disabled";
40 compatible = "ns16550a 33 compatible = "ns16550a";
41 reg = <0 0x10080100 0 34 reg = <0 0x10080100 0 0x100>;
42 clock-frequency = <500 35 clock-frequency = <50000000>;
43 interrupt-parent = <&p 36 interrupt-parent = <&pic>;
44 interrupts = <8 IRQ_TY 37 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
45 no-loopback-test; 38 no-loopback-test;
46 }; 39 };
47 40
48 ls7a_uart2: serial@10080200 { 41 ls7a_uart2: serial@10080200 {
49 status = "disabled"; 42 status = "disabled";
50 compatible = "ns16550a 43 compatible = "ns16550a";
51 reg = <0 0x10080200 0 44 reg = <0 0x10080200 0 0x100>;
52 clock-frequency = <500 45 clock-frequency = <50000000>;
53 interrupt-parent = <&p 46 interrupt-parent = <&pic>;
54 interrupts = <8 IRQ_TY 47 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
55 no-loopback-test; 48 no-loopback-test;
56 }; 49 };
57 50
58 ls7a_uart3: serial@10080300 { 51 ls7a_uart3: serial@10080300 {
59 status = "disabled"; 52 status = "disabled";
60 compatible = "ns16550a 53 compatible = "ns16550a";
61 reg = <0 0x10080300 0 54 reg = <0 0x10080300 0 0x100>;
62 clock-frequency = <500 55 clock-frequency = <50000000>;
63 interrupt-parent = <&p 56 interrupt-parent = <&pic>;
64 interrupts = <8 IRQ_TY 57 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
65 no-loopback-test; 58 no-loopback-test;
66 }; 59 };
67 60
68 pci@1a000000 { 61 pci@1a000000 {
69 compatible = "loongson 62 compatible = "loongson,ls7a-pci";
70 device_type = "pci"; 63 device_type = "pci";
71 #address-cells = <3>; 64 #address-cells = <3>;
72 #size-cells = <2>; 65 #size-cells = <2>;
73 #interrupt-cells = <2> 66 #interrupt-cells = <2>;
74 msi-parent = <&msi>; 67 msi-parent = <&msi>;
75 68
76 reg = <0 0x1a000000 0 69 reg = <0 0x1a000000 0 0x02000000>,
77 <0xefe 0x00000 70 <0xefe 0x00000000 0 0x20000000>;
78 71
79 ranges = <0x01000000 0 72 ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
80 <0x02000000 0 73 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
81 74
82 ohci@4,0 { 75 ohci@4,0 {
83 compatible = " 76 compatible = "pci0014,7a24.0",
84 77 "pci0014,7a24",
85 78 "pciclass0c0310",
86 79 "pciclass0c03";
87 80
88 reg = <0x2000 81 reg = <0x2000 0x0 0x0 0x0 0x0>;
89 interrupts = < 82 interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
90 interrupt-pare 83 interrupt-parent = <&pic>;
91 }; 84 };
92 85
93 ehci@4,1 { 86 ehci@4,1 {
94 compatible = " 87 compatible = "pci0014,7a14.0",
95 88 "pci0014,7a14",
96 89 "pciclass0c0320",
97 90 "pciclass0c03";
98 91
99 reg = <0x2100 92 reg = <0x2100 0x0 0x0 0x0 0x0>;
100 interrupts = < 93 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
101 interrupt-pare 94 interrupt-parent = <&pic>;
102 }; 95 };
103 96
104 ohci@5,0 { 97 ohci@5,0 {
105 compatible = " 98 compatible = "pci0014,7a24.0",
106 99 "pci0014,7a24",
107 100 "pciclass0c0310",
108 101 "pciclass0c03";
109 102
110 reg = <0x2800 103 reg = <0x2800 0x0 0x0 0x0 0x0>;
111 interrupts = < 104 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-pare 105 interrupt-parent = <&pic>;
113 }; 106 };
114 107
115 ehci@5,1 { 108 ehci@5,1 {
116 compatible = " 109 compatible = "pci0014,7a14.0",
117 110 "pci0014,7a14",
118 111 "pciclass0c0320",
119 112 "pciclass0c03";
120 113
121 reg = <0x2900 114 reg = <0x2900 0x0 0x0 0x0 0x0>;
122 interrupts = < 115 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
123 interrupt-pare 116 interrupt-parent = <&pic>;
124 }; 117 };
125 118
126 sata@8,0 { 119 sata@8,0 {
127 compatible = " 120 compatible = "pci0014,7a08.0",
128 121 "pci0014,7a08",
129 122 "pciclass010601",
130 123 "pciclass0106";
131 124
132 reg = <0x4000 125 reg = <0x4000 0x0 0x0 0x0 0x0>;
133 interrupts = < 126 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-pare 127 interrupt-parent = <&pic>;
135 }; 128 };
136 129
137 sata@8,1 { 130 sata@8,1 {
138 compatible = " 131 compatible = "pci0014,7a08.0",
139 132 "pci0014,7a08",
140 133 "pciclass010601",
141 134 "pciclass0106";
142 135
143 reg = <0x4100 136 reg = <0x4100 0x0 0x0 0x0 0x0>;
144 interrupts = < 137 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
145 interrupt-pare 138 interrupt-parent = <&pic>;
146 }; 139 };
147 140
148 sata@8,2 { 141 sata@8,2 {
149 compatible = " 142 compatible = "pci0014,7a08.0",
150 143 "pci0014,7a08",
151 144 "pciclass010601",
152 145 "pciclass0106";
153 146
154 reg = <0x4200 147 reg = <0x4200 0x0 0x0 0x0 0x0>;
155 interrupts = < 148 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-pare 149 interrupt-parent = <&pic>;
157 }; 150 };
158 151
159 gpu@6,0 { 152 gpu@6,0 {
160 compatible = " 153 compatible = "pci0014,7a15.0",
161 154 "pci0014,7a15",
162 155 "pciclass030200",
163 156 "pciclass0302";
164 157
165 reg = <0x3000 158 reg = <0x3000 0x0 0x0 0x0 0x0>;
166 interrupts = < 159 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-pare 160 interrupt-parent = <&pic>;
168 }; 161 };
169 162
170 dc@6,1 { 163 dc@6,1 {
171 compatible = " 164 compatible = "pci0014,7a06.0",
172 165 "pci0014,7a06",
173 166 "pciclass030000",
174 167 "pciclass0300";
175 168
176 reg = <0x3100 169 reg = <0x3100 0x0 0x0 0x0 0x0>;
177 interrupts = < 170 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-pare 171 interrupt-parent = <&pic>;
179 }; 172 };
180 173
181 hda@7,0 { 174 hda@7,0 {
182 compatible = " 175 compatible = "pci0014,7a07.0",
183 176 "pci0014,7a07",
184 177 "pciclass040300",
185 178 "pciclass0403";
186 179
187 reg = <0x3800 180 reg = <0x3800 0x0 0x0 0x0 0x0>;
188 interrupts = < 181 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-pare 182 interrupt-parent = <&pic>;
190 }; 183 };
191 184
192 gmac@3,0 { 185 gmac@3,0 {
193 compatible = " 186 compatible = "pci0014,7a03.0",
194 187 "pci0014,7a03",
195 188 "pciclass020000",
196 189 "pciclass0200";
197 190
198 reg = <0x1800 191 reg = <0x1800 0x0 0x0 0x0 0x0>;
199 interrupts = < 192 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
200 < 193 <13 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-name 194 interrupt-names = "macirq", "eth_lpi";
202 interrupt-pare 195 interrupt-parent = <&pic>;
203 phy-mode = "rg 196 phy-mode = "rgmii";
204 mdio { 197 mdio {
205 #addre 198 #address-cells = <1>;
206 #size- 199 #size-cells = <0>;
207 compat 200 compatible = "snps,dwmac-mdio";
208 phy0: 201 phy0: ethernet-phy@0 {
209 202 reg = <0>;
210 }; 203 };
211 }; 204 };
212 }; 205 };
213 206
214 gmac@3,1 { 207 gmac@3,1 {
215 compatible = " 208 compatible = "pci0014,7a03.0",
216 209 "pci0014,7a03",
217 210 "pciclass020000",
218 211 "pciclass0200",
219 212 "loongson, pci-gmac";
220 213
221 reg = <0x1900 214 reg = <0x1900 0x0 0x0 0x0 0x0>;
222 interrupts = < 215 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
223 < 216 <15 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-name 217 interrupt-names = "macirq", "eth_lpi";
225 interrupt-pare 218 interrupt-parent = <&pic>;
226 phy-mode = "rg 219 phy-mode = "rgmii";
227 mdio { 220 mdio {
228 #addre 221 #address-cells = <1>;
229 #size- 222 #size-cells = <0>;
230 compat 223 compatible = "snps,dwmac-mdio";
231 phy1: 224 phy1: ethernet-phy@1 {
232 225 reg = <0>;
233 }; 226 };
234 }; 227 };
235 }; 228 };
236 229
237 pci_bridge@9,0 { 230 pci_bridge@9,0 {
238 compatible = " 231 compatible = "pci0014,7a19.1",
239 232 "pci0014,7a19",
240 233 "pciclass060400",
241 234 "pciclass0604";
242 235
243 reg = <0x4800 236 reg = <0x4800 0x0 0x0 0x0 0x0>;
244 interrupts = < 237 interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
245 interrupt-pare 238 interrupt-parent = <&pic>;
246 239
247 #interrupt-cel 240 #interrupt-cells = <1>;
248 interrupt-map- 241 interrupt-map-mask = <0 0 0 0>;
249 interrupt-map 242 interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
250 }; 243 };
251 244
252 pci_bridge@a,0 { 245 pci_bridge@a,0 {
253 compatible = " 246 compatible = "pci0014,7a09.1",
254 247 "pci0014,7a09",
255 248 "pciclass060400",
256 249 "pciclass0604";
257 250
258 reg = <0x5000 251 reg = <0x5000 0x0 0x0 0x0 0x0>;
259 interrupts = < 252 interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
260 interrupt-pare 253 interrupt-parent = <&pic>;
261 254
262 #interrupt-cel 255 #interrupt-cells = <1>;
263 interrupt-map- 256 interrupt-map-mask = <0 0 0 0>;
264 interrupt-map 257 interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
265 }; 258 };
266 259
267 pci_bridge@b,0 { 260 pci_bridge@b,0 {
268 compatible = " 261 compatible = "pci0014,7a09.1",
269 262 "pci0014,7a09",
270 263 "pciclass060400",
271 264 "pciclass0604";
272 265
273 reg = <0x5800 266 reg = <0x5800 0x0 0x0 0x0 0x0>;
274 interrupts = < 267 interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-pare 268 interrupt-parent = <&pic>;
276 269
277 #interrupt-cel 270 #interrupt-cells = <1>;
278 interrupt-map- 271 interrupt-map-mask = <0 0 0 0>;
279 interrupt-map 272 interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
280 }; 273 };
281 274
282 pci_bridge@c,0 { 275 pci_bridge@c,0 {
283 compatible = " 276 compatible = "pci0014,7a09.1",
284 277 "pci0014,7a09",
285 278 "pciclass060400",
286 279 "pciclass0604";
287 280
288 reg = <0x6000 281 reg = <0x6000 0x0 0x0 0x0 0x0>;
289 interrupts = < 282 interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-pare 283 interrupt-parent = <&pic>;
291 284
292 #interrupt-cel 285 #interrupt-cells = <1>;
293 interrupt-map- 286 interrupt-map-mask = <0 0 0 0>;
294 interrupt-map 287 interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
295 }; 288 };
296 289
297 pci_bridge@d,0 { 290 pci_bridge@d,0 {
298 compatible = " 291 compatible = "pci0014,7a19.1",
299 292 "pci0014,7a19",
300 293 "pciclass060400",
301 294 "pciclass0604";
302 295
303 reg = <0x6800 296 reg = <0x6800 0x0 0x0 0x0 0x0>;
304 interrupts = < 297 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-pare 298 interrupt-parent = <&pic>;
306 299
307 #interrupt-cel 300 #interrupt-cells = <1>;
308 interrupt-map- 301 interrupt-map-mask = <0 0 0 0>;
309 interrupt-map 302 interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
310 }; 303 };
311 304
312 pci_bridge@e,0 { 305 pci_bridge@e,0 {
313 compatible = " 306 compatible = "pci0014,7a09.1",
314 307 "pci0014,7a09",
315 308 "pciclass060400",
316 309 "pciclass0604";
317 310
318 reg = <0x7000 311 reg = <0x7000 0x0 0x0 0x0 0x0>;
319 interrupts = < 312 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
320 interrupt-pare 313 interrupt-parent = <&pic>;
321 314
322 #interrupt-cel 315 #interrupt-cells = <1>;
323 interrupt-map- 316 interrupt-map-mask = <0 0 0 0>;
324 interrupt-map 317 interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
325 }; 318 };
326 319
327 pci_bridge@f,0 { 320 pci_bridge@f,0 {
328 compatible = " 321 compatible = "pci0014,7a29.1",
329 322 "pci0014,7a29",
330 323 "pciclass060400",
331 324 "pciclass0604";
332 325
333 reg = <0x7800 326 reg = <0x7800 0x0 0x0 0x0 0x0>;
334 interrupts = < 327 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
335 interrupt-pare 328 interrupt-parent = <&pic>;
336 329
337 #interrupt-cel 330 #interrupt-cells = <1>;
338 interrupt-map- 331 interrupt-map-mask = <0 0 0 0>;
339 interrupt-map 332 interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
340 }; 333 };
341 334
342 pci_bridge@10,0 { 335 pci_bridge@10,0 {
343 compatible = " 336 compatible = "pci0014,7a19.1",
344 337 "pci0014,7a19",
345 338 "pciclass060400",
346 339 "pciclass0604";
347 340
348 reg = <0x8000 341 reg = <0x8000 0x0 0x0 0x0 0x0>;
349 interrupts = < 342 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-pare 343 interrupt-parent = <&pic>;
351 344
352 #interrupt-cel 345 #interrupt-cells = <1>;
353 interrupt-map- 346 interrupt-map-mask = <0 0 0 0>;
354 interrupt-map 347 interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
355 }; 348 };
356 349
357 pci_bridge@11,0 { 350 pci_bridge@11,0 {
358 compatible = " 351 compatible = "pci0014,7a29.1",
359 352 "pci0014,7a29",
360 353 "pciclass060400",
361 354 "pciclass0604";
362 355
363 reg = <0x8800 356 reg = <0x8800 0x0 0x0 0x0 0x0>;
364 interrupts = < 357 interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-pare 358 interrupt-parent = <&pic>;
366 359
367 #interrupt-cel 360 #interrupt-cells = <1>;
368 interrupt-map- 361 interrupt-map-mask = <0 0 0 0>;
369 interrupt-map 362 interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
370 }; 363 };
371 364
372 pci_bridge@12,0 { 365 pci_bridge@12,0 {
373 compatible = " 366 compatible = "pci0014,7a19.1",
374 367 "pci0014,7a19",
375 368 "pciclass060400",
376 369 "pciclass0604";
377 370
378 reg = <0x9000 371 reg = <0x9000 0x0 0x0 0x0 0x0>;
379 interrupts = < 372 interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-pare 373 interrupt-parent = <&pic>;
381 374
382 #interrupt-cel 375 #interrupt-cells = <1>;
383 interrupt-map- 376 interrupt-map-mask = <0 0 0 0>;
384 interrupt-map 377 interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
385 }; 378 };
386 379
387 pci_bridge@13,0 { 380 pci_bridge@13,0 {
388 compatible = " 381 compatible = "pci0014,7a29.1",
389 382 "pci0014,7a29",
390 383 "pciclass060400",
391 384 "pciclass0604";
392 385
393 reg = <0x9800 386 reg = <0x9800 0x0 0x0 0x0 0x0>;
394 interrupts = < 387 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
395 interrupt-pare 388 interrupt-parent = <&pic>;
396 389
397 #interrupt-cel 390 #interrupt-cells = <1>;
398 interrupt-map- 391 interrupt-map-mask = <0 0 0 0>;
399 interrupt-map 392 interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
400 }; 393 };
401 394
402 pci_bridge@14,0 { 395 pci_bridge@14,0 {
403 compatible = " 396 compatible = "pci0014,7a19.1",
404 397 "pci0014,7a19",
405 398 "pciclass060400",
406 399 "pciclass0604";
407 400
408 reg = <0xa000 401 reg = <0xa000 0x0 0x0 0x0 0x0>;
409 interrupts = < 402 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
410 interrupt-pare 403 interrupt-parent = <&pic>;
411 404
412 #interrupt-cel 405 #interrupt-cells = <1>;
413 interrupt-map- 406 interrupt-map-mask = <0 0 0 0>;
414 interrupt-map 407 interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
415 }; 408 };
416 }; 409 };
417 410
418 isa@18000000 { 411 isa@18000000 {
419 compatible = "isa"; 412 compatible = "isa";
420 #address-cells = <2>; 413 #address-cells = <2>;
421 #size-cells = <1>; 414 #size-cells = <1>;
422 ranges = <1 0 0 0x1800 415 ranges = <1 0 0 0x18000000 0x20000>;
423 }; 416 };
424 }; 417 };
425 }; 418 };
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